> Since aquiring the mutex is already on the 'slow' track,
> couldn't you
> just aquire a second (pointless) mutex inside the first around only the
> 'initialized=1;' assignment? If mutexes resolve the initial situation
> then they must be implemented with a memory fence (in the itanium
> model),
Please see proposed patch for "crypto/engine/eng_cnf.c".
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David Schwartz wrote:
I mean that if the order of memory write visibility between
processors can't
be g'teed, than a whole lot MORE than just DCLP crashes and burns ... How
in that case can anyone write safe MP code?
D.
The only correct and safe way to do it is with mutexes or their
equ
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How do I check to see how many days are left for the
validity of a certificate. Is there a openssl command which tells me the days
or time left?
X509_cmd_current_time returns a positive integer if a
certificate is till valid? What does this signify? Is there a way to convert
this to th
> I mean that if the order of memory write visibility between
> processors can't
> be g'teed, than a whole lot MORE than just DCLP crashes and burns ... How
> in that case can anyone write safe MP code?
>
> D.
The only correct and safe way to do it is with mutexes or their
equivalent.
D
Anyone ever contemplated coding openssl support for
p2q 'rsa' moduli with Hensel lifting? Or does this
already live in the codebase somewhere?
marius
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OpenSSL Project http://www.openssl.org
Develo
Check out "A Formal Specification of Intel Itanium Processor Family Memory
Ordering" (http://www.intel.com/design/itanium/downloads/25142901.pdf). It
describes in excruciating detail how reordering of memory operations can be
observed by other processors. Example A.1 (in Appendix A) is a simple
e
ARGH!
Are you absolutely sure that this is the case - that's scary - I thought
that the whole issue of SMP cache coherency and write order was solved years
ago.
I mean that if the order of memory write visibility between processors can't
be g'teed, than a whole lot MORE than just DCLP cra
Hi David,
I know that Scott is very busy at the moment, so he may not respond. I'll
drop his address on the next reply.
The implementations below suffer from the same general problem as the
implementations I've been playing around with recently. On processors that
reorder memory accesses it is
oops ... First test should of course read:
Singleton* Singleton::instance()
{
if (!initialised) // 1st test
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Behalf Of David C. Partridge
Sent: 06 April 2005 14:08
To: openssl-dev@openssl.org
Cc: [EMAIL PROTECTED]
Subje
I've just read the paper, and I believe that the following variation on
the code would work and would avoid the MP unsafe issues raised because
bool is defined to be a single byte.
Further-more, I'm pretty certain that it also resolves the issues with the
order of construction
and setting of the p
> -Original Message-
> From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]
> On Behalf Of Andy Polyakov
> Sent: Wednesday, April 06, 2005 5:34 PM
> To: openssl-dev@openssl.org
> Subject: Re: RC4 optimize for em64t
>
> >>>Or how about moving mozb (%rdi,%r10),%r8d upwards as movzb
> >>>(%rdi
OK,I'd like to report this as a bug to the IBM ikeyman folks. However,
when I look at PKCS#12 v1
(http://www.rsasecurity.com/rsalabs/node.asp?id=2138) I don't see any
discussion of this limitation of the localKeyID field. Is there a newer
spec I should be looking at?
BTW - the link on your
Or how about moving mozb (%rdi,%r10),%r8d upwards as movzb
(%rdi,%r10),%r14b and make inter-register move between r8 and r14
conditional?
I will try it.
I have tried it, not performance gain.
Does it mean that it's same or does it mean that it's slower? Was it
cmov or was it jump over mov
Hi All,
OpenSSL makes use of the DCLP (double-checked locking pattern) in a number
of places (rsa_eay.c and at least one engine; I haven't done an exhaustive
search), with code that usually looks like this:
if (x == NULL)
{
CRYPTO_w_lock(CRYPTO_LOCK_XXX);
/* Avoid a race
BTW, 272MBps at 3.6GHz? I get 262MBps out of [as just mentioned
virtually identical] 32-bit code at 2.4GHz P4...
In fact, Your implement on EM64t isn't that slow if
we change the inc and dec to add and sub. :)
With that change the throughput boost from 272Mb/s to 396Mb/s.
Huh? And what
Hi,
I found openssl-0.9.7f cannot be comipiled for Windows CE platforms. This
is mainly because some APIs takes Unicode strings as thier arguments. And
there are some minor problems such as unused local variables.
Here is a patch to fix the problems.
Thanks.
--
Satoshi Nakamura <[EMAIL PROTEC
On Wed, 2005-04-06 at 08:08, Zou Nan hai wrote:
> On Tue, 2005-04-05 at 18:17, Andy Polyakov wrote:
> > > Current OpenSSL (0.9.8-dev) rc4speed throughput on a Nocona (Em64t,
> > > b4bit) 3.6GHz is 272Mb/s, while this version of RC4 code can archive
> > > 536Mb/s in RC4Speed.
> > >
> > > ããWoul
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