On Wed, May 10, 2017 at 3:59 PM, Bartlomiej Zolnierkiewicz
wrote:
> On Monday, May 08, 2017 10:26:49 PM Linus Walleij wrote:
>> On Mon, May 8, 2017 at 12:47 PM, Bartlomiej Zolnierkiewicz
>> wrote:
>> So depending on whether they use an FPGA or
On Mon, May 8, 2017 at 12:47 PM, Bartlomiej Zolnierkiewicz
wrote:
> Also for all current drivers we just put timing values (or a logic
> to calculate them from the standard ATA timings) into the driver
> itself and not device tree (as they are based on values are
Hi Linus
On Sat, 6 May 2017, Linus Walleij wrote:
> This adds device tree bindings for the Faraday Technology
> FTIDE010 found in the Storlink/Storm/Cortina Systems Gemini SoC.
>
> I am not 100% sure that this part if from Faraday Technology but
> a lot points in that direction:
>
> - A later
This adds device tree bindings for the Faraday Technology
FTIDE010 found in the Storlink/Storm/Cortina Systems Gemini SoC.
I am not 100% sure that this part if from Faraday Technology but
a lot points in that direction:
- A later IDE interface called FTIDE020 exist and share some
properties.