Hi,
On Wed, Jan 27, 2016 at 07:03:58PM +0300, Anton Kalmykov wrote:
> Hi, 951G owners!
> I have RB951G-2HnD device with AR9344 rev 3. It is configured like that:
> - Balanced 2 WAN ports (mwan3)
> - ipsec LAN-to-LAN
> - OpenVPN server
> - about 30 clients (wi-fi, lan)
>
> My results for
Hi, 951G owners!
I have RB951G-2HnD device with AR9344 rev 3. It is configured like that:
- Balanced 2 WAN ports (mwan3)
- ipsec LAN-to-LAN
- OpenVPN server
- about 30 clients (wi-fi, lan)
My results for different ath79_eth0_pll_data.pll_1000 values:
0x3e00 - it worked fine with Barrier
On 27/01/2016 17:03, Anton Kalmykov wrote:
>
> Hi, 951G owners!
> I have RB951G-2HnD device with AR9344 rev 3. It is configured like that:
> - Balanced 2 WAN ports (mwan3)
> - ipsec LAN-to-LAN
> - OpenVPN server
> - about 30 clients (wi-fi, lan)
>
> My results for different
Hello John,
Of course this has been over a year since I submitted (
http://patchwork.ozlabs.org/patch/419857/ ); however I remember in one
of our e-mail threads that you ( or Felix? ) thought it was possible
to pull the correct pll_1000 value from the bootloader? Is that still
a possibility?
If
Hello John,
Sorry, I'm mistaken: my value is 0x6f00 (NOT 0x0600) and it works
correctly.
And, yes, taking value from the bootloader is a nice idea, it would be good!
Anton
27.01.2016, 21:28, John Crispin wrote:
On 27/01/2016 17:03, Anton Kalmykov wrote:
>
> Hi, 951G owners!
> I
Hi,
I'm bumping again, this patch is necessary to make the gigabit switch work
on the Mikrotik 951G-2HnD (tested on CC).
Thanks,
Baptiste
On Wed, Nov 25, 2015 at 06:18:29PM +0100, Baptiste Jonglez wrote:
> Hi,
>
> Sorry to bump up the thread again. Is there anything blocking to merge
> this
Hi,
Sorry to bump up the thread again. Is there anything blocking to merge
this patch?
If it helps, there are user reports about setting different values of
ath79_eth0_pll_data.pll_1000 here:
Hi,
On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
> Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface.
> The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable
> AR934X_ETH_CFG_RXD_DELAY.
I can confirm that this patch works on CC
On Sat, Dec 13, 2014 at 04:42:03PM -0700, Davey Hutchison wrote:
The boot loader on these boards is routerboot. I do not know if routerboot
provides a md like command or not.
Here's the RouterBOOT menu on my RB2011:-
RouterBOOT booter 3.18
RouterBoard 2011UiAS-2HnD
CPU frequency: 600 MHz
Hi,
thanks for the info, i found my poe injector, a cisco cable and my
keyspan. i will look into this during the coming days. sorry for the
delay, i want to double check that the fix is correct. what strikes me
as odd is that this used to work on older kernels. it might be related
to the enforced
Hello,
I don't think this is related to the kernel. This issue was also in
Barrier Breaker ( 3.10 ). The CPU was changed in the Routerboard
951G's from an ar9344 rev. 2 to a ar9344 rev. 3. I am wondering if the
processor revision change had anything to do with it. Here is the
OpenWRT Bug
Hi,
On 10/12/2014 22:33, Chris Green wrote:
On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface.
The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable
AR934X_ETH_CFG_RXD_DELAY.
On Sat, Dec 13, 2014 at 09:01:09AM +0100, John Crispin wrote:
Hi,
On 10/12/2014 22:33, Chris Green wrote:
On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
Fix pll_1000 value for eth0. Traffic would not flow from the eth0
interface.
The new PLL enables delay, use
The boot loader on these boards is routerboot. I do not know if routerboot
provides a md like command or not.
Sent from my iPhone
On Dec 13, 2014, at 1:01 AM, John Crispin blo...@openwrt.org wrote:
Hi,
On 10/12/2014 22:33, Chris Green wrote:
On Wed, Dec 10, 2014 at 01:40:42PM -0700,
Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface.
The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable
AR934X_ETH_CFG_RXD_DELAY.
Signed-off-by: Davey Hutchison dhutchi...@bluemesh.net
--- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c
+++
On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote:
Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface.
The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable
AR934X_ETH_CFG_RXD_DELAY.
Signed-off-by: Davey Hutchison
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