Re: [OpenWrt-Devel] Lantiq xrx200 - switch rtl8367rb controlled via builtin mdio (not gpio sck/sda!) in EasyBox 904xDSL
Hi Arnold, On Thu, Jun 18, 2015 at 11:15 PM, Jonas Gorski j...@openwrt.org wrote: There is no special chip, the RTL8367 provides several means of accessing the chip registers; using MDIO registers is one of them. Jonas seems to be right! Out of interested I just checked the source code again and found more information in the u-boot source of the 904 xDSL: [0] Make sure you check out int rtl_sw_reset(u32 delay_msec) (this seems to use GPIOs to reset the switch). Then there's rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) for writing data to the switch and rtk_int32 smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData) for reading data. I also added Gabor Juhos to the CC list, maybe he can suggest how to proceed with the RTL8367B switch driver: 1. Rewrite the existing driver so it can also control the switch using MDIO 2. Write a separate rtl8367b_mdio driver (this could use e.g. ADM6996 as an example) Regards, Martin [0] https://github.com/uwehermann/easybox-904-xdsl-firmware/blob/master/package/infineon-utilities/feeds/ifx_feeds_uboot/open_uboot/src.904dsl/drivers/net/vr9_sw.c ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Lantiq xrx200 - switch rtl8367rb controlled via builtin mdio (not gpio sck/sda!) in EasyBox 904xDSL
Hi,
On Sun, Jun 14, 2015 at 11:10 PM, Arnold Schulz arny...@gmx.net wrote:
Hi everyone,
for fun I have put efforts to solve some mysteries of the EasyBox 904xDSL.
(here thank you Sylwester and Martin B. for feedback).
Currently code in driver/net/phy/rtl8366_smi.c is used to control rtl836x
chips via bitbanging two gpio lines. This does not work for the 904 xDSL.
Disassembling code from the rtl8367rb.ko (oem firmware) shows that the
rtl8367rb is controlled via mdio registers at 0xBE10B120~128.
I'm pretty sure I identified all gpio usage in rt8367rb.ko. There is
one switch hw reset line (io41). Pin io42 and io43 are setup once
(AltSel1/0:=1/0; no open drain; Dir:=output for io43) and then left alone,
I guess to be driven by internal mdio logic responding to 0xBE10B120~128.
Access to the switch' registers looks somehow cumbersome, e.g.
u32 RTL83XX_SMI_READ(u32 addr)
{
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x1F, 0xE);
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x17, addr 0x)
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x15, 1);
ifx_vr9_mdio_write(0, 0x1D, 0x);
return ifx_vr9_mdio_read(0, 0x19);
}
So many more bits are banged over the bus as the code in rtl8366_smi.c
does. Me wondering: there must be a chip between, which relays control
info to the rtl8367rb?
There is no special chip, the RTL8367 provides several means of
accessing the chip registers; using MDIO registers is one of them. It
also understands SPI (likely using different pins though).
Regards
Jonas
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[OpenWrt-Devel] Lantiq xrx200 - switch rtl8367rb controlled via builtin mdio (not gpio sck/sda!) in EasyBox 904xDSL
Hi everyone,
for fun I have put efforts to solve some mysteries of the EasyBox 904xDSL.
(here thank you Sylwester and Martin B. for feedback).
Currently code in driver/net/phy/rtl8366_smi.c is used to control rtl836x
chips via bitbanging two gpio lines. This does not work for the 904 xDSL.
Disassembling code from the rtl8367rb.ko (oem firmware) shows that the
rtl8367rb is controlled via mdio registers at 0xBE10B120~128.
I'm pretty sure I identified all gpio usage in rt8367rb.ko. There is
one switch hw reset line (io41). Pin io42 and io43 are setup once
(AltSel1/0:=1/0; no open drain; Dir:=output for io43) and then left alone,
I guess to be driven by internal mdio logic responding to 0xBE10B120~128.
Access to the switch' registers looks somehow cumbersome, e.g.
u32 RTL83XX_SMI_READ(u32 addr)
{
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x1F, 0xE);
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x17, addr 0x)
ifx_vr9_mdio_write(0, 0x1D, 0x);
ifx_vr9_mdio_write(0, 0x15, 1);
ifx_vr9_mdio_write(0, 0x1D, 0x);
return ifx_vr9_mdio_read(0, 0x19);
}
So many more bits are banged over the bus as the code in rtl8366_smi.c
does. Me wondering: there must be a chip between, which relays control
info to the rtl8367rb?
Some more laboriously disassembled and pretty formatted functions are
listed in file disass_rtl8367rb.ko_mdio-smi.txt here:
http://arny.tjps.eu/OpenWrt/EasyBox904xDSL/oem-firmware-info/research/
Of course ifx_vr9_mdio_read/write() looks similar to xrx200_mdio_rd/wr()
in drivers/net/ethernet/lantiq_xrx200.c of current OpenWrt kernel code.
Guess I won't be able to provide a patch which utilizes these finding.
If this is of use for anyone, I would be glad to hear about it.
Arnold
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