*Role: VLSI HVL Verification * *Location: Chandler - Arizona*
strong automation experience, based on Python, makefile, and TCL, as well as ASIC RTL to GDS knowledge â¿¢ Experience defining or working with automation frameworks. â¿¢ Participates in architecting, designing, implementing, validating and deploying applications followed by continuous improvement based on user feedback. â¿¢ Designs, develops, debugs & tests ASIC EDA tools, including developing wrappers or scripts for EDA tools. â¿¢ Creates flows/scripts to analyze and test ASIC design methodologies, especially physical design validation. â¿¢ Works independently solving problems at various levels of abstraction. â¿¢ Programming languages such Python, makefile, and TCL in a UNIX/Linux environment is required. Best Regards, *Sumit Singh* | SYSMIND, LLC Phone: 609-897-9670 x 2192 Email: sum...@sysmind.com Website: sysmind.com Hangout: sumit.int...@gmail.com Address: 38 Washington Road, Princeton Junction, NJ 08550 -- You received this message because you are subscribed to the Google Groups "oraapps" group. To unsubscribe from this group and stop receiving emails from it, send an email to oraapps+unsubscr...@googlegroups.com. To post to this group, send email to oraapps@googlegroups.com. Visit this group at https://groups.google.com/group/oraapps. For more options, visit https://groups.google.com/d/optout.
