You’re absolutely right.
The difference with normal chassis is only the lack of output port.
It is determined in l2_lkp table. This is the only one reason to send packet to
ingress pipeline.
Regards,
Vladislav Odintsov
> On 18 Sep 2021, at 01:25, Numan Siddique wrote:
>
> On Fri, Sep 17, 2021
On Fri, Sep 17, 2021 at 5:59 PM Vladislav Odintsov wrote:
>
> Hi Numan,
>
> I’ve posted a new patch version here:
> https://patchwork.ozlabs.org/project/ovn/patch/20210917215602.10633-1-odiv...@gmail.com/
Thanks. I'll take a look.
If I understand correctly, packets coming from RAMP
Hi Numan,
I’ve posted a new patch version here:
https://patchwork.ozlabs.org/project/ovn/patch/20210917215602.10633-1-odiv...@gmail.com/
I’ve tried to answer your question about ACLs in documentation.
Please let me know if it is clear.
Regards,
Vladislav Odintsov
> On 17 Sep 2021, at 22:42,
On Fri, Sep 17, 2021 at 11:01 AM Vladislav Odintsov wrote:
>
> A packet going from HW VTEP device to VIF port when arrives to
> hypervisor chassis should go through LS ingress pipeline to l2_lkp
> stage without any match. In l2_lkp stage an output port is
> determined and then packet passed to LS
A packet going from HW VTEP device to VIF port when arrives to
hypervisor chassis should go through LS ingress pipeline to l2_lkp
stage without any match. In l2_lkp stage an output port is
determined and then packet passed to LS egress pipeline for futher
processing and to VIF port delivery.
