Re: [perfmon2] Difference in LAST_LEVEL_CACHE_MISSES and L2_LINES_IN:SELF values for kernel +user v/s user mode on xeon x5482

Thanks Kristian, I have some points to draw attaention on: - One counts requests while the other counts line allocations (that is not the same, as it is possible for multiple cache misses to the same cache line to be serviced by the same single allocation). ==That means LAST_LEVEL_CACHE_

[perfmon2] switch event set on PMD overflow

hi all, I am using perfmon kernel v2.6 with pfmlib v3.5. Can I switch event sets on overflow of a specific PMD register? On sample mode, I would like to switch event sets when the sample-based event PMD overflow. I guess one solution is set the size of sampling buffer to only one entry, and I

Re: [perfmon2] Difference in LAST_LEVEL_CACHE_MISSES and L2_LINES_IN:SELF values for kernel +user v/s user mode on xeon x5482

J K Rai writes: > I get same values for the two events (i.e. LAST_LEVEL_CACHE_MISSES and > L2_LINES_IN:SELF) in user mode while the two change when the same are > collected for kernel+user mode. E.g. FWIW, I see similar behaviour. I'm using libperfmon/pfmon 3.6 and kernel 2.6.27.9. Cpu is Inte