[perfmon2] Last Branch Record support?

Hi, all I am interested in the LBR (Last Branch Record), and I saw perfmon supports LBR for Intel Core i7. http://perfmon2.sourceforge.net/pfmon_intel_corei7.html How the LBR is used in perfmon? I cannot find anything about LBR from the output of `pfmon -l`. Or LBR only can be used by using

Re: [perfmon2] libpfm4 for SPARC

Hi, all The output of `showevtinfo` in the libpfm4/examples is a little bit strange to me. Here is my SPARC machine. $ uname -i UltraSparc T2 (Niagara2) And here is the output of `showevtinfo`. --- Supported PMU models:

Re: [perfmon2] libpfm4 for SPARC

Hi, It all depends on what your /proc/cpuinfo shows for the 'pmu' line. It needs to show nigara2 for libpfm4 to detect a Niagara 2 PMU. Send me the output of cpuinfo. thanks. On Fri, Mar 18, 2011 at 10:30 AM, 陳韋任 wrote: > Hi, all > >  The output of `showevtinfo` in the libpfm4/examples is a li

Re: [perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

Hi, PEBS guarantees that you will get the IP of an instruction that follows one that caused the event. The reason you get the next instruction is because the machine state is recorded at retirement of the instruction, thus IP already points to the next instr. Also note that the "sampled instructi

Re: [perfmon2] libpfm4 for SPARC

Hi, The attachment is the SPARC's /proc/cpuinfo. Regards, chenwj -- Wei-Ren Chen (陳韋任) Parallel Processing Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 cpu : UltraSparc T2 (Niagara2) fpu : UltraSparc T2 integrated FP