[perfmon2] Understanding libpfm4 perf_events attribute translation

anslates MEM_TRANS_RETIRED::LATENCY_ABOVE_THRESHOLD into *0x5301cd* and *0x3* instead of *0x1cd* ? Thanks Laksono Adhianto -- Check out the vibrant tech community on one of the world's most engaging tech sites, Slash

Re: [perfmon2] Understanding libpfm4 perf_events attribute translation

Stephane, Thanks for the info ! It's clear for me now. Laksono Adhianto On Wed, May 16, 2018 at 12:31 PM, Stephane Eranian wrote: > Hi, > > On Tue, May 15, 2018 at 11:48 AM, laksono wrote: > >> All, >> >> >> I want to profile using MEM_TRANS_RETIR

[perfmon2] spr::TOPDOWN:SLOTS and spr::TOPDOWN:BAD_SPEC_SLOTS events have the same codes?

ted transactional memory region (boolean) This is tested with Intel Sapphire Rapid CPU on Linux 4.18 using the latest libpfm4 from the git repository. Laksono Adhianto ___ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net ht

[perfmon2] Issues with some Intel Sapphire Rapids TOPDOWN.* codes

"EventCode": "*0xa4*", "UMask": "*0x10*", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", Can someone confirm if this is correct? Laksono Adhianto ___ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel

[perfmon2] Intel SPR: Missing EXE_ACTIVITY.EXE_BOUND_0_PORTS and EXE_ACTIVITY.2_3_PORTS_UTIL events

CTIVITY.2_3_PORTS_UTIL", Is it possible to include the missing umasks in `intel_spr_exe_activity`? We need these events to create Intel TMA metrics. Regards, Laksono Adhianto ___ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel