Søren Sandmann sandm...@cs.au.dk writes:
I can't think of a way to save the value of a 32 bit register that both
works on x86-32 and doesn't lose the upper 32 bits on x86-64, so in the
new version below, there are some #ifdefs to deal with this issue.
And that version didn't work on x86-32
Søren Sandmann Pedersen sandm...@cs.au.dk writes:
The changes to x86 are the most involved. There is now a
pixman_cpuid() function that uses inline assembly on GCC and the
cpuid__ intrinsic on MSVC. The assembly is written such that it will
work on both 32 and 64 bit; the main change required
Søren Sandmann Pedersen sandm...@cs.au.dk writes:
git://people.freedesktop.org/~sandmann/pixman
in the branch cpudetectfiles.
This got mangled by git send-mail. It should have said:
TL;DR:
Please test these patches, especially on MSVC, XO-1, MIPS and
mobile ARM. They are
On 06/29/12 01:44 PM, Søren Sandmann Pedersen wrote:
I was looking at making use of some of the newer x86 SIMD instruction
sets and realized that (a) we don't ever call cpuid on x86-64, we just
assume that MMX and SSE2 are present,
I thought the amd64 ABI guaranteed MMX SSE2 would always be
On Fri, Jun 29, 2012 at 5:20 PM, Alan Coopersmith
alan.coopersm...@oracle.com wrote:
On 06/29/12 01:44 PM, Søren Sandmann Pedersen wrote:
I was looking at making use of some of the newer x86 SIMD instruction
sets and realized that (a) we don't ever call cpuid on x86-64, we just
assume that MMX
Alan Coopersmith alan.coopersm...@oracle.com writes:
On 06/29/12 01:44 PM, Søren Sandmann Pedersen wrote:
I was looking at making use of some of the newer x86 SIMD instruction
sets and realized that (a) we don't ever call cpuid on x86-64, we just
assume that MMX and SSE2 are present,
I
On 06/29/12 02:36 PM, sandm...@cs.au.dk wrote:
Alan Coopersmith alan.coopersm...@oracle.com writes:
On 06/29/12 01:44 PM, Søren Sandmann Pedersen wrote:
I was looking at making use of some of the newer x86 SIMD instruction
sets and realized that (a) we don't ever call cpuid on x86-64, we
