It would be a really good thing to have one or more EC2 AMIs available that people could just spin up on whatever instance they want and it puts them into an emulated RISC-V Linux environment. Preferably taking advantage of all the available cores. User mode qemu with a chroot and binfmt_misc could be made to work right now, and full system qemu when that supports multiple cores. Or RV8 if that gets more syscalls implemented.
And/or Docker. I'd be happy to set that kind of thing up once I get freed up to work on RISC-V stuff full time. On Tue, Feb 13, 2018 at 9:41 PM, Palmer Dabbelt <pal...@dabbelt.com> wrote: > On Fri, 09 Feb 2018 02:57:21 PST (-0800), edward.nev...@gmail.com wrote: > >> Hi, >> >> I would like to voice my support for the creation of this project. >> >> The process for creation of a new OpenJDK project is described at >> http://openjdk.java.net/projects/#new-project >> >> The initial discussion should be sent to the general discussion list, >> discuss.at.openjdk.dot.java.dot.net. I have cc'd this to the general >> discussion list. >> > > Thanks. > > Assuming that the group lead of the porters project agrees to sponsor the >> project then the call for votes should be sent to >> announce.at.openjdk.dot.java.dot.net. >> >> Note that only current OpenJDK contributors may propose the creation of a >> new project. If you are not a current OpenJDK contributor I am happy to >> propose the project on your behalf. >> > > We never submitted the Tilera port, so I'm not a contributor at all. It > would be great if you could propose the project for me. > > http://openjdk.java.net/bylaws#contributor >> >> I am happy to devote some 'spare' time to this project, but this will me >> limited to a few hours per week. >> > > Well, that's about all the time I'll have as well :). I know that OpenJDK > is way more work than a spare time project, but I'm hoping that we can at > least get things started with a community effort and then see where things > go from there. > > I agree with the overall approach you outline below. You will probably end >> up doing C1 anyway. The s390 port tried to do it without doing C1 and they >> ended up doing C1. >> >> Andrew Haley's suggestion of using a built in simulator is a good one. >> This was the approach used on the aarch64 project and it was invaluable >> not just in terms of development time in the absence of hardware but in >> terms of debuggability. Also OpenJDK depends on a huge list of packages to >> build. Using this approach you can build and run on x86 while all the >> dependant packages are being ported. >> > > That makes sense. IIRC there were a lot of headaches involved in getting > this all together last time, and having a simulator seems like a good idea. > > > >> All the best, >> Ed. >> >> >> On Thu, 2018-02-08 at 08:38 -0800, Palmer Dabbelt wrote: >> >>> [Sorry for the second email, it appears my SiFive email doesn't want to >>> subscribe to porters-dev.] >>> >>> RISC-V is an open standard ISA stewarded by the RISC-V foundation >>> <http://riscv.org>. With the recent release of glibc 2.27 we now have >>> the full >>> RISC-V software base released from the various upstream repositories, >>> which >>> means it's time to start moving forward with the rest of the software >>> stack. I >>> ran into Erik at FOSDEM a few days ago and he suggested that we open up >>> the >>> discussion of an OpenJDK port for RISC-V. While I'm not familiar with >>> the >>> RISC-V Java efforts, I did part of a Hotspot port (a bit of the template >>> interpreter and much of C2) to Tilera's TilePro and TileGx architectures >>> a few >>> years ago so I know a bit about the OpenJDK internals. >>> >>> In the RISC-V community we view Java as a very important missing >>> component of >>> the software ecosystem, so I was thrilled when Erik found me at FOSDMEM >>> and >>> suggested there was community interest in a port. Unfortunately, I >>> won't have >>> time to properly help out with the port (I'm maintaining Linux, as well >>> as >>> co-maintaining binutils, GCC, and glibc). That said, I'd be very happy >>> to help >>> out where I can. I think a good way to move forward might be to: >>> >>> * Create a project to own the RISC-V port, which is what this email is >>> about. >>> I'm OK being the project lead, at least until we find someone who will >>> have >>> * Clean up our libffi port and submit it upstream. Stefan O'Rear is in >>> the >>> process of submitting the port now, so it should all be moving >>> smoothly soon. >>> Submit patches for our Zero port. While I didn't do the port I don't >>> mind >>> cleaning it up and submitting it. I've added Martin who was more >>> involved >>> with the original port. I think he's not working on RISC-V stuff now >>> that >>> he's at Google, though. >>> * Move forward with a proper OpenJDK port, starting with the template >>> interpreter and eventually adding C2. I'm not sure if C1 is actually >>> deprecated, but we decided not to bother with it at Tilera because it >>> didn't >>> seem worth the extra effort at the time. Of course, this would be up >>> to >>> whomever is actually doing the work :). >>> >>> There appears to be considerable community interest in a RISC-V OpenJDK >>> port, >>> so my hope is that while I don't have time to directly contribute much >>> myself >>> that we'll be able to get something sane up and running. Interested >>> users can >>> test on QEMU, and we've recently announced a board (and associated beta >>> program >>> that provide free boards to open source developers) so there's some >>> hardware to >>> run on as well. >>> >>> I'd like to request that the Porters Group sponsors this project with me >>> as the >>> lead. >>> >>> Thanks! >>> >> > -- > You received this message because you are subscribed to the Google Groups > "RISC-V SW Dev" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to sw-dev+unsubscr...@groups.riscv.org. > To post to this group, send email to sw-...@groups.riscv.org. > Visit this group at https://groups.google.com/a/gr > oups.riscv.org/group/sw-dev/. > To view this discussion on the web visit https://groups.google.com/a/gr > oups.riscv.org/d/msgid/sw-dev/mhng-793d8e1c-ea48-423c-8911- > 9fe97483f3e7%40palmer-si-x1c4. >
