Paul,
You don't say which version of Protel you are using, so I'm going to
assume 99SE. If you haven't allready done so, from the PCB go File/Print
Preview. From there select the Browse PCBPrint tab. Right click on the layers
you don't want and delete them e.g. TopOverlay to get rid of
Hi Andrew J Jenkins
I'm sorry to bother you. I'm a new user of Protel Forums but I don't know how
it works. I hope you can help me. I need the files for simulation of the
models:
TLC 2201 MFKB
TLC 271 FK
I like to you can tell me, the way to ask to everybody in the forum. I've
worked with
The trick is, to do the save lib command before the update schematic,
otherwise the schematic are not updated with the changes made in the lib
part.
Georg
[EMAIL PROTECTED]
-Urspr ngliche Nachricht-
Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
Auftrag von Gene Silvernail
Gesendet:
On 06:58 PM 5/02/2001 -1000, Cecil Waterhouse said:
One item I would like to see added to PCB is the use of a wild card (and a
range) when placing components etc.
i.e. 'edit' 'move' 'Component' U*. This would allow the user to place all
designated components starting with the lowest value of U
I think that
http://groups.yahoo.com/group/protel-users/files/
is a good place for us to put ddbs.
(It already has sample ddb named LayerStackSample.zip).
Please tell me if you find a better place. (I like the directory structure
Phillip suggests).
Jim Parr [EMAIL PROTECTED] on 2001-02-03
Hi ALL,
I am using 99SE SP6 on a nice new DELL and just finished auto
routing a 9 layer board and am going crazy trying to figure out what I am
really looking at in single layer viewing mode. (DUH! how about the current
selected layer?)
It appears that the artwork displayed does
Hi Geoff,
On 5 Feb 2001, at 11:59, Geoff Harland wrote:
In schematic, I was editing my button toolbar (power ports) and I
clicked on the Info button. Protel complained that it couldn't
find AdvSch.HLP. This file is in c:\Program Files\Protel99SE\Help.
How do I tell protel? Does anyone
- Original Message -
From: Gene Silvernail [EMAIL PROTECTED]
To: Multiple recipients of list proteledausers
[EMAIL PROTECTED]
Sent: Monday, February 05, 2001 12:43 PM
Subject: [PROTEL EDA USERS]: Whats With Global Replacement ???
What gives with global string replacement
I disabled my global clearance constraint.
Thanks for the help,
Ted Tontis
Design Engineer
Engage Networks Inc.
[EMAIL PROTECTED]
PH 414.273.7600 Ext. 7607http://www.engagenet.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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Hello everyone,
I am working on an RF design which has 2 boards, essentially a sandwich.
The bottom board has the digital stuff and 18 relays. The relays have
physical connections on the top and bottom of the case (Coil on the bottom
and contacts on the top). The top board has all the nasty
Hello, all:
I am trying to decide what video card to buy in my new PC (Athlon, DDR). I
would like to know what cards are stable and fast for use with 99SE and
Win2K. Also, I would like to know what cards to avoid.
My local PC shop will use any card I specify, but is recommending the Elsa
Hi Geoff,
On 6 Feb 2001, at 11:17, Geoff Harland wrote:
Yes, it looks as though its past behaviour has changed with the
release of SP6. (Prior to then, a dialog box was invoked, with which
you could then navigate to the folder containing the AdvSch.HLP file.)
I am still using SP5...
A
Hi Terry,
On 5 Feb 2001, at 18:27, Terry Harris wrote:
On Mon, 5 Feb 2001 11:10:20 +1100, you wrote:
Hi all,
In schematic, I was editing my button toolbar (power ports) and I
clicked on the Info button. Protel complained that it couldn't find
AdvSch.HLP. This file is in c:\Program
Glenn,
What I would do is place the bottom board with the relay coils on it and
lock the parts in location.
Then use one of the mechanical layer to place circles around the
locations for the contacts on the top board the same size as the pads.
Copy the mech layer and mirror if needed. You
On 11:03 AM 2/6/2001 +1100, Les Grant wrote:
Hi Andrew,
On 4 Feb 2001, at 22:26, Andrew Jenkins wrote:
I'd be interested to know if you find the same situation on your
system, ie, that it's more than just AvdSch.hlp.
I just tried the same experiment with the PCB editor - same
problem.
re split planes -- change PCB so that the plane layer must be the CURRENT
layer for the split to be editable. (How often do you edit the split,
compared to ALL the other parts on the board!)
I just did my first design that had one of these, and being CONSTANTLY
prompted to choose between the
Has anyone had any experience with the 3dxf Voodoo video cards
and Protel (good or bad)?
Thanks,
Steve Smith
Product Engineer
Staco Energy Products Co.
Web Site: www.stacoenergy.com
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* This message sent by: PROTEL EDA USERS
Who let this person on the list without doing the initiation rites!?!? ;-p
I wouldn't take it personally, these lists are voluntary. I've posted the
most innocuous questions to some other lists, and they took on a life of
their own. The flip side is your case... everyone checks it, then
I used to be able to show an inverted signal name on the schematic using
an
overbar. Depending on the settings of the options, I could overbar single
letters or an entire name. This no longer seems to work, at least not on
the
part type field of the connector (testpoint) where I'd like to
--- Kerry Murphy [EMAIL PROTECTED] wrote:
Forum members,
Does anyone know whether or not Protel can find
entities in a PCB design that are extraneous and
should be removed [like hangers of etch from removed
components, unnecessary vias, etc.]? I would think
that setting up the design
Expanding on Andrew's fourth suggestion. Enter your board outline and do
you component placement then get one or two sets of prototype boards made
with no etching. There will be copper all over one or both sides of the
boards. Maybe use one of those quick turn around places. While they are
The nodes for the controlling input of the controlled sources are set in
brackets in the models supplied from analog devices, like Gx 1 0 (2,0) 1
Try without brackets like Gx 1 0 2 0 1.
The analog models from protel are ok like this.
I think there is an article in the protel knowledge base that
If all you want to do is a lot of cad spread sheet stuff, the Matrox
G4xx series seems to be fine. If you will be using opengl direct3d, you
will probably be better off using an Nvidia chipset based card. I recommend
a Geforce 2. At high resolution + high scan rate, the Matrox seems to
Guess - I'm in a phase of, not complaining but improving mode, today.
Hi everyone.
before I actually go any step further I should clarify that I've got
nothing in comon with the schematic-capture side of things.
All my pcb designs come as third-party schem. and netlists.
Inhouse tools will
Steve,
Using a \ backslash before any character will produce an overbar for
net labels and pin names (in SchLib). Fired up Protel 98 just to check if it
worked with part type fields, but no. So to the best of my knowledge its not a
facility that has disappeared with SP6 of some kind.
Ivan,
Thought I'd pass along this gem from Protel CSC, its their response to the
*brand new* problems with my ATI All-in-Wonder Pro card. Didn't ever have
problems before service pack 6.
Just FYI,
Frank
Frank,
We have encountered some issues with the ATI video card, it is not a good
At 11:15 AM 2/7/01 -0800, you wrote:
I also need to do these translations. Currently I am trying to get from
Orcad Capture 7.2 to Protel 99 SE. That is from an Orcad schematic to Protel
layout. I am not interested in bring the schematic into Protel, only the
netlist. I have tried various Orcad
Hi Georg -
I do realise what you're trying to point out. I believe, an instance like
that won't happen to often.
A schem. designer, will always be ware of the pcb-size and the components
chosen for the design.
However - I won't deny it - it can happen, but then there is still the pcb
designer,
AJ,
Am I correct in thinking that a poofteenth is the Imperial
equivalent to the US measure, LikeRillyRillyLikeSmall ?
Maybe, what's a LikeRillyRillyLikeSmall ?
And secondly, can you provide all of us technicrats with the
mathematical relationship between the aforementioned
poofteenths
Thanks for the suggestions Ian. I will try some of your suggestions over the
next few days, first I have this one into P99SE via P98 and have to finish
it off.
I do concur with your comment that usually items will simply be
missing. That has been my experience as well, until now. It
Paul,
Why don't you just make it from scratch? It's only 8 pins...
(I could understand if you were asking for some large part 100+ pins or
whatever, but an 8 pin SOIC??) It probably took you more time to write the
email, and read your first response.
No disrespect intended :)
Tony
Andrew Lowy Sybrandy wrote:
I still have a one question:
1. Why is it important to change the X and Y size to zero before production.
It was said this prevents flashing from within the Gerber file, but I
don't know what that means.
There are varying opinions here, but one reason is that
Why does not the DRC tell the planes are shorting?
Henrik Thurfjell
Megatron Engineering
Direct 408 737 1718
FAX Messages 408 739 2429
email: [EMAIL PROTECTED] or [EMAIL PROTECTED]
- Original Message -
From: Andrew Lowy Sybrandy [EMAIL PROTECTED]
To: Multiple recipients of
Hello,
I have a person here that wants a 50mil X 250mil rectangle plated
through hole. I am having trouble figuring out the best way to do this
with Protel so that the board house will know what I want. Any
suggestion/comments are appreciated.
Thanks,
Brad Marshall
* * * * * * * * * * * * *
Fabian,
you seem to have misread one crucial word in my post, Import. I
was trying to import DXF from ACAD into Protel P99SE, even a DXF file that
reads into P98 without problems.
Thanks for the reply anyway.
Sincerely,
Brad Velander
Lead PCB Design
Norsat International Inc.
#100 -
That's because the system resources that are monitored are not related to
the total memory that you have. It measures the amount of system table area
that is remaining. And that is a fixed and very small size by today's
software requirements. I think it totals to 64K, the amount addressable by
Andy,
As far as why AC said the holes shorted, I'll take a guess: If you made the pads
single-layer (e.g., Top Layer) instead of
MultiLayer, that's why. If you look at the PCB in single-layer mode (Shift-S), for a
single layer pad there won't be 'negative
copper' on the inner planes to keep
HI EVEREBODY!
AGAIN ME. I WONDER IF SOMEONE CAN TELL ME THE WAY TO SELECT A SIMULATION MODEL
THAT IT IS THE MORE SIMILAR TO
TLC2201 AND TLC271
OF ANYWAY IF I WANT TO USE A IDEAL OPERATIONAL AMPLIFIER WHICH OF THE
SIMULATION MODELS INCLUDED IN PROTEL 99 CAN I USE.
I THANK YOU VERY MUCH TO
Hi all,
I have just noticed (after my client told me!) that Protel gerbers of
octagonal pads end up as rounded pads. Is this just a configuration
problem or does Protel not like octagonal pads or is there some
other good reason for this behaviour? The actual problem is that the
PCB
Glennster wrote:
Hello everyone,
I am working on an RF design which has 2 boards, essentially a
sandwich.
The bottom board has the digital stuff and 18 relays. The relays
have physical connections on the top and bottom of the case (Coil on
the bottom and contacts on the top).
Hello all,
I have a one-page schematic that I created mostly by block copying parts of other 99SE
schematics. Some of the reference designators are duplicates, others are new with
question marks and so-forth. I have tried to reset designators and then annotate, and
I also tried to annotate
Very simple:
Use a pad.
Choose a hole diameter and place it in the Hole Size, X-size, Y-size.
For layer, choose MultiLayer. (Helps prevent a potential bug.)
Additional:
If you are using a screw to mount, it is better to enlarge the X-size
Y-size to the diameter of the screw head.
Hi Protel users...
I notice that when I create a BOM with the Schematic program sometimes parts
that are on the schematic do not show up in the BOM.
After some trouble-shooting I discovered that the parts were being dropped
from the BOM ...if... the 'Part Type' field was empty.
Is it supposed
This problem appears to have just started happening with SP6: I have a single DDB,
with its window maximized. If I open enough
documents (sch, pcb, text, whatever) so that the document tabs along the top of the
window no longer fit, and scroll arrows appear,
then using the tabs becomes
Micky,
I assume you are monitoring your User and GDI stack resources with this
system monitor? Or what are you referring to? Is that a CPU usage graph?
Got my curiosity up,
Frank
At 09:38 AM 2/8/01 -0600, you wrote:
Kind of cool?
I have been curious about the system performance while
Hello all,
I relatively new to Protel use, but I've been noticing something
related to this discussion. When I have a via that is used to connect a top
layer signal to a mid layer signal, I drop the via down and Protel makes the
connection, but there is no pad around the plated through
Dwight,
As a general rule I cover all vias except on prototypes when acess to the
via is useful. With very fine pitched and high
density stuff this gets pretty esential. Exposed vias can lead to bridging from one
via to another or from a via to a pad because of
scrap solder paste.
Are you saying the graphs are not a true indication of the system
performance?
I wouldn't expect Windows to do something that wasn't real! LOL!!
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Tim Hutcheson
Sent: Thursday, February 08, 2001 10:16 AM
To:
We, here in the south of germany, call this a
' muggeseckele'
what is real small.
I do not translate it.
Georg
[EMAIL PROTECTED]
-Urspr ngliche Nachricht-
Von: TSListServer [mailto:[EMAIL PROTECTED]]Im
Auftrag von Darren Moore
Gesendet: Freitag, 9. Februar 2001 06:07
An: Multiple
No, he wasn't saying that The Resource monitor monitors system
resources, which, as others have mentioned, are a bit cramped in Windows
98SE no matter how much total memory you have.
At 10:49 AM 2/8/01 -0600, Micky Blain wrote:
Are you saying the graphs are not a true indication of the
I've been using Protel 99se for several months and regularly import dxf
files not only from AutoCAD, but from SolidWorks as well, without the
problems you are describing - so I don't think the release is the problem.
During the time I've described, I have installed service packs 5 and 6, so
it
Brad Velander wrote:
a typical shop might have a 32mil diameter
router as their smallest size
router bit and therefore your corners will have a 16mil radius.
It is a bad idea to use an inside radius same as your router bit radius. This
requires the router to come to a complete stop and then
Mr. Lomax,
Yes, it is reproducible. The reset option has no effect.
I have tried every option available to me even though it is only one sheet.
Drew
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Abd ul-Rahman Lomax
Sent: Thursday, February 08, 2001
great tip, I never realized that!
thanks
Dennis Saputelli
Hamid A. Wasti wrote:
It is a bad idea to use an inside radius same as your router bit radius. This
requires the router to come to a complete stop and then start moving at 90
degrees. There will invariably be some chatter and the
1. just go bit on a big order with power plane clearance. It seems that the
gerbers generates the plane all the way to the edge of the keep out layers.
Is there anyway to control the power plane and manually draw them in without
doing them by split planes?
Micky Blain
* * * * * * * * * * *
Dear Bryan Bernesi,
I run ERC all the time (Tools | ERC | OK), and I've never seen it change any
of my schematic symbols. Would you be so kind as to help me reproduce this
problem ? You could put a file that demonstrates this weird behavior in
Protel 'power planes' go forever.
I place primitives like tracks or area fills on the power planes to create
clearances.
Remember that primitives on power planes are 'anti-copper', and this will
also produce a warning when you run a drc.
I often also pull in the power planes more than the ground
I usually draw the board outline on Mech 1 and then select the board
outline and copy to one of the power planes. I then select just the
outline on the power layer and change the track width. I select the
track width depending on the required clearance between the plane and
the board edge. I then
Micky,
I have always placed rectangular fills around the edges of my boards
on the power planes. Protel will warn you that there are primitives on the
planes in the DRC. Check these are only the fills you intended then proceed to
generate gerbers. I have to say that I would expect a
Hi Bryan.
I am making a multi-layer board (2 signal, 2 power)
with 24 exact modules.
Even when you have repeated modules within a design, at the very least
component designators have to be unique. If you're not using Ports only
Global or Sheet Symbols/Port Connections then your netnames
I place a track (maybe 20 mil) on each power plane around the edge of the
outline
of the board to prevent the power planes from extending too far.
___
Clive Broome
IDT Sydney Design CentrePh: +61 2 9763 3513
8
Suggestion for a nice powerplane - clearance.
Set your relative coordinates to, say the bottom lefthand corner of your board.
Set a snap of 50 or 100 mils.
With reference to the bottom lefthand corner, highlight and copy the
board-outline - in your case this will probably be the lines on your
The main problem is attempting to cut and paste arrays of components in PCB and
getting them to match up with your schematic. Protel matches the designators
only
and if you do a normal cut and paste array it will try to help you by
renumbering your
designators.
The problem is it renumbers
Alright, forget my message unless it is just to confirm that the automatic
process for adding Mech layers to printouts is broken. I found the
work-around by adding the layers within the individual drawing prints
within
the Browse PCB Print.
Hi all,
now I believe a fair while ago I had seen
Thanks, I thought I was loosing it...
heheh.. anyway, we are using it too, but I am fixing some old schematics and
didn't notice the dropping of the parts until checking the BOM. We put 'DNP'
into the part field when we wish not to stuff a part... it stands for Do
Not Populate... :)
- Bill
snip
Configuration file. There is a dialog box which can be used to select
which Mechanical layers will be included in Printout definitions. But the
layers so selected apply only *after* these have been set up, and as such,
are not applied retrospectively to any currently/previously defined
Alright, forget my message unless it is just to confirm that the automatic
process for adding Mech layers to printouts is broken. I found the
work-around by adding the layers within the individual drawing prints within
the Browse PCB Print.
Hi all,
now I believe a fair while ago I had
Sorry folks,
I just sent a file to the group instead of my work address. Too late in the
evening...Many apologies. It's benign, but hopefully the forum admin can kill the
message before it's resent...
Irreverence for the pustule-filled decrepitude of the patriarchy is a proud, 400 yr
Iris,
the TLC271 has programmable bias setting capability. If you do not need this
feature for simulation take the LMC6081 from National, which is close to the
Texas OP. The model is supplied by protel with the standard simulation
models for OPAMPS, to be found in the ..\Design Explorer 99
I got an error that said access violation at address OE271BF0 in module
AdvSch.dll read of address 0046 and now Protel won't open any file or
respond in any other way. Any suggestions. Should I reload Protel? I was
just starting to get some progress and had my first board ready for layout.
At 05:40 PM 2/13/01 +1100, Geoff Harland wrote:
The idea of putting tracks on a Mechanical layer, and then including the
contents of that (Mechanical) layer with just *some* of the Gerber files
produced, to wit, the (Gerber) files produced from the internal power plane
layers (only), raises the
Micky Blain wrote:
I have deleted a power plane from my design. It seems that SP6 is not taking
this off of the design. I think I remember this subject being discussed but
I was swamped at the time and it was a few weeks back.
Does anyone know how to get the plane off the design?
Open
I have been trying to send this for over four hours. Please accept my apologies if it
gets duplicated as our ISP seems to think [EMAIL PROTECTED] does not
exist.
Robi,
Will W2k tolerate modem-sharing?
Yes. ICS is included with W2K, though I recommend and use a hardware solution
instead.
Thanks for the kind words.
I was not too concerned about looking foolish, I KNEW I had a virus and it
appeared at the same time I opened the schematic file in question. I did not
understand how it happened, but wanted to warn the rest of the list members
*just in case* there was some new
sorry, it's my lame term for the 'update free primitives from component
pads' function in the netlist manager menu option
Dennis Saputelli
Brad Velander wrote:
Dennis,
can you be more specific in your learning the board? I think I
know what you mean but I am not exactly sure there
PVDTS -- (Post Valentines Day Traumatic Syndrome).
regards,
Tim Hutcheson
Institute for Human and Machine Cognition
40 S. Alcaniz ST.
Pensacola, FL 32503
[EMAIL PROTECTED]
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I've quoted the full headers and cc'd this to Mr. Lundsten as well; perhaps
this will be of some use.
Sometimes list servers can be configured to send copies of incoming posts
to all subscribers except the author. Usually, I think, the default is that
the author also gets a copy; on
Apparently it's possible to put a sheet entry called e.g. RST# and
regardless of whether the corresponding sheet has a RST# port, the nets
will be connected. This relates to my earlier post regarding an ERC
check for unmatched ports and sheet entries.
Is this sensible? I can't think of any good
Andrew J Jenkins wrote:
I'd still like to know some more specifics regarding optimizing this new
rule. My 31's DO live a much shorter life than the 62's, on average, and I'm
sure everyone else would ultimately benefit from the information too. A rule
is only useful if its substance can be
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Peter Bennett
Sent: Tuesday, February 13, 2001 8:14 AM
To: Multiple recipients of list ProtelEDAusers
Subject: Re: [PROTEL EDA USERS]: having W2k installed, can I run...
And I just discovered a
Yes, I think it is the same as I had with the company - logo on the
schematic.
In the sheet ( or library part ) there is a link to the graphic file and
not
the
graphic itself. Your collegue has probably not the same graphic in the
same
path.
Georg
I have also had similar experiences. So
Perhaps I should read ahead, instead of popping in so quickly. I see that
Mr. Wasti has at least partially answered my questions (under the subject
of Optimum Routing inside radius, was: Rectangle holes):
At 09:52 AM 2/15/01 -0800, Hamid A. Wasti wrote:
...
It is a fact of life that the
At 08:42 PM 2/12/01 -0800, Marty Beck wrote:
I got an error that said access violation at address OE271BF0 in module
AdvSch.dll read of address 0046 and now Protel won't open any file or
respond in any other way. Any suggestions. Should I reload Protel? I was
just starting to get some
OK that is what happened, I will try and rename the plane prior to deleting.
Thanks!
-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Le, Phan
Sent: Tuesday, February 13, 2001 4:10 PM
To: Multiple recipients of list proteledausers
Subject: RE: [PROTEL EDA
Marty,
What did you do before the message?
I got that same message when I tried to open two design databases in
the same Protel window (99SE SP5). I think the second DDB was corrupted, but
regardless, I had to go use a back-up copy that I had. Periodically, I will
copy
Andrew W. Riley III
Talon Instruments
150 East Arrow Highway
San Dimas, California 91773
(909) 599-0690 [voice]
(909) 599-6529 [fax]
www.taloninst.com
[EMAIL PROTECTED]
ICQ#: 100686794
-Original Message-
From: Andrew W. Riley III [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, February 13,
Just very busy here.
Brad Marshall
Coleman, Tim wrote:
??
Just checking, I've seen only a few posts from the forum today and that was
this morning.
Time is 5:09PM GMT
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*
I hope Ian Wilson fixes the link so it points to
http://www.angelfire.com/electronic/protelarchive/threads.html
...
Steve Smith [EMAIL PROTECTED] on 2001-02-14 02:44:15 PM
Please respond to [EMAIL PROTECTED]
To: Multiple recipients of list proteledausers
[EMAIL PROTECTED]
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