[PEDA] integrating effort ?

2002-04-19 Thread Robison Michael R CNIN
hello, we've got a pcb that really needs to be in here by may 1. the problem is that its a 10 layer board with very complex polygon pours, and everything must match closely with some legacy raster images of the layers. with just one person working on it, there's little chance that we can make

Re: [PEDA] integrating effort ?

2002-04-19 Thread Simon Peacock
your best bet is to do a round the world processing.. that way the board can be worked on 24 hours a day by people in different time zones :) .. but expect to pay through the nose :) Simon. P.S. I've done this before.. and it works as long as you have CAD operators of equal stature.

Re: [PEDA] Power plane clearance rule

2002-04-19 Thread David Palombo
Your right. I keep forgetting that a pad on a plane layer is a void, so that would be included in the clearnace. Thanks, Dave At 04:20 PM 4/19/02 -0700, you wrote: The terminology for the clearance rule can be a bit confusing. The clearance you are specifying is not an expansion to clear a

Re: [PEDA] PLCC Socket reliability

2002-04-19 Thread Brian Guralnick
My rule of thumb for 68 pin PLCC sockets Don't exceed 24Mhz replace the IC in the socket no more than 4 times. Passing analog signals through the socket is a no-no... When using 48Mhz, do not replace the IC more than 2 times. These are my personal rule and they do not conform to any standards