Re: [PEDA] Simulation Function Block, PWLR
Thomas, i did have a look at the devices PWL and PWLR. you mentioned. PWL works ok (default as a voltage type). The PWLR (default as a differential voltage type) demands a part type attribute must be a value, but i think its just a protel bug. The parameter list of the PWLR includes the %vd(pin1, pin2) statement, what simply means that the differential voltage between pin1 and pin2 should be taken as an in- or output parameter. An additional '%' (%%vd) should prevent protel from interpreting the '%v' to insert the part type as a parameter here. But it doesn't ! Seems to be a simple protel bug (precompiler does not recognize the '%%vd' but sees a '%v' and wants a value !). If you give the part type any legal value (e.g. '1' instaed of 'PWLR') the simulation works and the given value has absolutely no influence on the result (the netlist contains the '%vd()' statement, protel does not inserts the value of the part type instead of '%v', the compiler itself seems to know how to handle '%%vd'). Rolf Molitor Ing.Buero i2e Remscheid / Germany -Ursprüngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Sonntag, 29. September 2002 22:27 Betreff: Re: [PEDA] Simulation Function Block, PWLR Rolf, I am using a current source to send a current proportional to the total number of ampereturns through a resistor. I am planning to use the resistor as an amplification control, but it could be set up differently of course. I connected this function block to measure the voltage across this resistor. The array values models the flux in a particular magnetic material as a function of the ampereturns. I have not deliberately specified if it is a current or voltage source, I thought it automatically was a voltage source, but maybe that is a part of the problem? You can find the model in the Protel component library, got to; http://www.protel.com/resources/libraries/library_search.asp and search for Generic Components, Simulation and Function Block. The search should return roughly 32 matches on one page. You should find two variants of the model; PWL and PWLR. I am not sure I understand what you mean with 'part type as a parameter', could you explain? Thomas handled The output from this - Original Message - From: Rolf Molitor [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, September 27, 2002 3:15 AM Subject: Re: [PEDA] Simulation Function Block, PWLR Thomas, but what kind of signal do you want to model with the 'PWLR' ? Is it a voltage like with VPWL or a current as with IPWL (with time/value pairs as parameters) ? Where can i find this part 'PWLR', where can i find the library you got it from (what .ddb is it in) ? Maybe the 'PWLR' does take the part type as a parameter (%) ? Rolf Molitor Ing.Buero i2e Remscheid / Germany -Urspr ngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Freitag, 27. September 2002 03:41 Betreff: Re: [PEDA] Simulation Function Block, PWLR I am working with 99. The component seems to be a table with (input) x-values in one array and (output) y-values in a second array. The output/input is interpolated to create the correct output from any input value. From the model description it seems to be similar to the Simcode model PWL_TABLE. Thomas - Original Message - From: Rolf Molitor [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, September 26, 2002 2:56 AM Subject: Re: [PEDA] Simulation Function Block, PWLR Thomas, is it DXP or 99SE you are working with ? Never seen this 'simulation function block' library in 99SE and never seen the component PWLR. Is it a piece-wise linear resistor ? Just know the IPWL and VPWL sources. Rolf Molitor Ing.Buero i2e Remscheid / Germany -Urspr ngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Donnerstag, 26. September 2002 02:57 Betreff: [PEDA] Simulation Function Block, PWLR I am trying to use the piece-wise linear controlled source from the Simulation Function Block Sch.Lib to create a non-linear magnetic circuit model. As a start I hooked the PWLR to a previously verified circuit and got the following error message; U1 Error: PART TYPE attribute must be a value. What value am I supposed to use? Grateful for a detailed explanation (or a reference to where I can find a detailed explanation) since I am new to this software package. Thanks Thomas The Netlist contains the following statement; AU1 %VD(AT,0) %VD(NETLABEL26,0) AU1PWL .MODEL AU1PWL PWL(X_ARRAY=[0 10 20 30 40 50 60 70 80 90 100] Y_ARRAY=[0 0.005 + 0.010 0.025 0.040 0.075 0.125 0.2000.290 0.380 0.475] input_domain=0 fraction=0) * * * * * * * * * * * * * * *
Re: [PEDA] 1020-pin BGA out-routing question (some add)
Hi, I changed the footprint, 40mil pitch with 20mil pads. VIAs between SMD pad are 16mil pad and 8mil hole, we want use this because there will be more room for routing and SOLDERMASK is bigger between SMD pad and VIA (I have 4mil opening for SMD pads and VIAs are tentd or 0mil opening; which one is better). Traces are 4mil and gap is also 4mil, need to route two trace between SMD pads, do not want make over 10 layer board... Should I use two powerplanes for FPGA core voltage, I/O voltage for FPGA (there is 8 bank, so we might need 8 different I/O voltages), VREF voltage for each bank (8 bank), 3.3V for memory and other chips... how to manage all those different voltages...??? How about making splitplanes on GNDplane for different GNDs? (memory, I/O, of cource there will be own GND splitplane for FPGA chip...???) JaMi wrote... This will keep your vias as far as possible from the actual BGA pad, and you want as much here as you can get. This wili also allow you to use a bigger via (see below). Our VIAs are 16mil pad and 8mil hole, isn't this ok? The board size could be x=8000mil y=4900mil (do not know yet...) I am still intrestd in what kind of board stack up you GURUs recommend! -Jupa -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: 27. syyskuuta 2002 22:03 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add) Juha, Just looked at your database. First, your vias are misplaced, and need to be exactly in the center of the opening between the pads, which appear to be on a 1mm grid, which means that you vias should be on a .5mm grid. This will keep your vias as far as possible from the actual BGA pad, and you want as much here as you can get. This wili also allow you to use a bigger via (see below). Secondly, you will possibly want a larger pad to drill ratio on your vias if at all possible, to prevent massive breakouts, which while acceptable by some standards. may be excessive with that current ratio. One of routing numbers being batted around by some board houses is somthing they call the five fours, which is three 4 mil gaps with two 4 mil traces, all between a 20 mil pad with 10 mil holes for 40 mil spacing on a BGA. If your spacing on the BGA is actually 1mm, which is .03937 . . . , instead of 40 mil, then you have to slightly adjust the size of the pad, and everything else will fit. Even here you are gonig to possibly see breakout, which once again is allowable, providing that you are using teardrops for all of your pad entries. How big is your board anyway, overall size wise. The above numbers are based on standard alignment of all features within 5 mil, and unless your board is fairly large. everything seems to be very do-able with out too many layers, or the need to go to micro vias, or ever to blind or burried vias. JaMi - Original Message - From: Juha Pajunen [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, September 27, 2002 1:09 AM Subject: [PEDA] 1020-pin BGA out-routing question (some add) Hi again, What is the best PCB layer stack for this type of BGA? http://groups.yahoo.com/group/protel-users/files/junk/ There is 1020-pin 1mm pitch BGA. It would be very pleasing to have some information and help how to route that huge BGA. What are trace width and cap between different tracks and so... It would be very nice if you couldedit that file (how to route it) and then send it to me to this addrss [EMAIL PROTECTED] I really need all useful information about routing this BGA! :) Sincerely, Juha Pajunen, Hw Engineer Bitboys Oy E-mail: [EMAIL PROTECTED] NOTE: This message, and any attached files, may contain privileged or confidential information. It is intended for use only by the designated recipients. Any disclosure, copying or distribution of, or reliance upon, this message by anyone else is strictly prohibited. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout?
they were meatball 10/10 mostly 12/12 bds there was a giant pour on the entire top the clearance on the pour was 20 mils all the way around the pads (to make it easy and not get shorts!) they said with a big plane it is harder to etch there must be at least a bit of truth to that because i have had this trouble with this type of board from 3 different shops - albeit not the highest tech shops kicking around I did this type of pour and had the board house slap my wrists and tell me because of it they would have to electrically test the boards even though they were very simple. The explainattion was that if you have a big pour with lots of copper on one side you need about the same copper on the other side to balance it. Otherwise the acid on one side gets weak while the other side remains strong, resulting in overetching on one side or underetching on the other. Better circulation in the acid bath helps, but yield still goes down and thus cost goes up. If you do a big pour on only one side you should do it with a crosshatch pattern so that the copper is balanced and etching is even. After that wrist slapping I've have learned my lesson and I try hard to keep the copper even. Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Best settings for polygon fill on signal layer?
Hello all, I'm finalizing my PCB for first proto. Its a 4-layer board w/o internal planes but uses signal layer polygon fill on each layer for the GND, SGND, +15, -15 planes. My question today is: What considerations need to be made when selecting the polygon fill parameters, relative to the gerbers and photoplotter etc. I presently am using 13mil track and 13mil gap on 45 degrees with octagon surrounds on pads, which gets the computations done reasonably quick and seems to look ok. Do the gerber routines emit optimized large aperture settings with steps to minimize the photo operations, etc? TIA Sincerely, Tim Hutcheson Institute for Human and Machine Cognition University of West Florida 40 South Alcaniz St. Pensacola, FL 32501 - There are 10 types of people in the world; those that read binary and those that don't. -- Anonymous Poster -- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Best settings for polygon fill on signal layer?
Tim, first my observations. I have always found that 45 degree polygons are a lot slower than 90 degree polygons at repouring. Since yours is completely filled I don't see where 45 degree is doing anything for you. Second, rather than using a grid matching the track width, I normally use a 0 grid which spaces the tracks according to the track width. Just a couple of tips from my experiences. As for your other questions, I have never observed Protel to do any gerber optimization for polygons. It will draw the polygon using the same aperture as your track width and draw line for line what is in the database. There is a setting in the gerber advanced tab that will optimize gerber elements for drawing but this is just a distance travelled optimization similar to the drill travel optimization in the NC Drill generation. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Tim Hutcheson [mailto:[EMAIL PROTECTED]] Sent: Monday, September 30, 2002 8:16 AM To: peda Subject: [PEDA] Best settings for polygon fill on signal layer? Hello all, I'm finalizing my PCB for first proto. Its a 4-layer board w/o internal planes but uses signal layer polygon fill on each layer for the GND, SGND, +15, -15 planes. My question today is: What considerations need to be made when selecting the polygon fill parameters, relative to the gerbers and photoplotter etc. I presently am using 13mil track and 13mil gap on 45 degrees with octagon surrounds on pads, which gets the computations done reasonably quick and seems to look ok. Do the gerber routines emit optimized large aperture settings with steps to minimize the photo operations, etc? TIA Sincerely, Tim Hutcheson Institute for Human and Machine Cognition University of West Florida 40 South Alcaniz St. Pensacola, FL 32501 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Best settings for polygon fill on signal layer?
what about the question of octagon vs arcs on the pours? we use the arcs (without notable problems) for whatever that is worth they look nice anyway Dennis Saputelli Brad Velander wrote: Tim, first my observations. I have always found that 45 degree polygons are a lot slower than 90 degree polygons at repouring. Since yours is completely filled I don't see where 45 degree is doing anything for you. Second, rather than using a grid matching the track width, I normally use a 0 grid which spaces the tracks according to the track width. Just a couple of tips from my experiences. As for your other questions, I have never observed Protel to do any gerber optimization for polygons. It will draw the polygon using the same aperture as your track width and draw line for line what is in the database. There is a setting in the gerber advanced tab that will optimize gerber elements for drawing but this is just a distance travelled optimization similar to the drill travel optimization in the NC Drill generation. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Tim Hutcheson [mailto:[EMAIL PROTECTED]] Sent: Monday, September 30, 2002 8:16 AM To: peda Subject: [PEDA] Best settings for polygon fill on signal layer? Hello all, I'm finalizing my PCB for first proto. Its a 4-layer board w/o internal planes but uses signal layer polygon fill on each layer for the GND, SGND, +15, -15 planes. My question today is: What considerations need to be made when selecting the polygon fill parameters, relative to the gerbers and photoplotter etc. I presently am using 13mil track and 13mil gap on 45 degrees with octagon surrounds on pads, which gets the computations done reasonably quick and seems to look ok. Do the gerber routines emit optimized large aperture settings with steps to minimize the photo operations, etc? TIA Sincerely, Tim Hutcheson Institute for Human and Machine Cognition University of West Florida 40 South Alcaniz St. Pensacola, FL 32501 -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Best settings for polygon fill on signal layer?
Thanks Brad. I thought the 45 degree might match up with the octagonal surrounds for the pads but if it isn't needed I'll change it. Thanks for the info. Sincerely, Tim Hutcheson Institute for Human and Machine Cognition University of West Florida 40 South Alcaniz St. Pensacola, FL 32501 - There are 10 types of people in the world; those that read binary and those that don't. -- Anonymous Poster -- -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Monday, September 30, 2002 11:37 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Best settings for polygon fill on signal layer? Tim, first my observations. I have always found that 45 degree polygons are a lot slower than 90 degree polygons at repouring. Since yours is completely filled I don't see where 45 degree is doing anything for you. Second, rather than using a grid matching the track width, I normally use a 0 grid which spaces the tracks according to the track width. Just a couple of tips from my experiences. As for your other questions, I have never observed Protel to do any gerber optimization for polygons. It will draw the polygon using the same aperture as your track width and draw line for line what is in the database. There is a setting in the gerber advanced tab that will optimize gerber elements for drawing but this is just a distance travelled optimization similar to the drill travel optimization in the NC Drill generation. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Tim Hutcheson [mailto:[EMAIL PROTECTED]] Sent: Monday, September 30, 2002 8:16 AM To: peda Subject: [PEDA] Best settings for polygon fill on signal layer? Hello all, I'm finalizing my PCB for first proto. Its a 4-layer board w/o internal planes but uses signal layer polygon fill on each layer for the GND, SGND, +15, -15 planes. My question today is: What considerations need to be made when selecting the polygon fill parameters, relative to the gerbers and photoplotter etc. I presently am using 13mil track and 13mil gap on 45 degrees with octagon surrounds on pads, which gets the computations done reasonably quick and seems to look ok. Do the gerber routines emit optimized large aperture settings with steps to minimize the photo operations, etc? TIA Sincerely, Tim Hutcheson Institute for Human and Machine Cognition University of West Florida 40 South Alcaniz St. Pensacola, FL 32501 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Best settings for polygon fill on signal layer?
Dennis, Tim, I use the arcs as well, with no problems to date. I don't know if there is any optimization to using arcs or octagons. Personal preference rules here. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Monday, September 30, 2002 10:00 AM To: Protel EDA Forum Subject: Re: [PEDA] Best settings for polygon fill on signal layer? what about the question of octagon vs arcs on the pours? we use the arcs (without notable problems) for whatever that is worth they look nice anyway Dennis Saputelli * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Simulation Function Block, PWLR
Rolf Since you have PWL working, I tried it again. The netlist generation worked without generating any errors, result for the PWL was; AU1 AT FLUX AU1PWL .MODEL AU1PWL PWL(X_ARRAY=[0 10 20 30 40 50 60 70 80 90 100] Y_ARRAY=[0 0.005 + 0.01 0.025 0.04 0.075 0.125 0.2 0.29 0.38 0.475] input_domain=100 fraction=1) The simulation did however stop before it was completed with the following error message; INPpas2: Invalid code-model syntax or connection Error on line 9: au1 at flux au1pwl ERROR - model: au1pwl - Bad Boolean value Error: circuit not parsed. What does it mean? What am I missing? Have I given input_domain and fraction wrong values? Thomas - Original Message - From: Rolf Molitor [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 30, 2002 3:13 AM Subject: Re: [PEDA] Simulation Function Block, PWLR Thomas, i did have a look at the devices PWL and PWLR. you mentioned. PWL works ok (default as a voltage type). The PWLR (default as a differential voltage type) demands a part type attribute must be a value, but i think its just a protel bug. The parameter list of the PWLR includes the %vd(pin1, pin2) statement, what simply means that the differential voltage between pin1 and pin2 should be taken as an in- or output parameter. An additional '%' (%%vd) should prevent protel from interpreting the '%v' to insert the part type as a parameter here. But it doesn't ! Seems to be a simple protel bug (precompiler does not recognize the '%%vd' but sees a '%v' and wants a value !). If you give the part type any legal value (e.g. '1' instaed of 'PWLR') the simulation works and the given value has absolutely no influence on the result (the netlist contains the '%vd()' statement, protel does not inserts the value of the part type instead of '%v', the compiler itself seems to know how to handle '%%vd'). Rolf Molitor Ing.Buero i2e Remscheid / Germany -Urspr ngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Sonntag, 29. September 2002 22:27 Betreff: Re: [PEDA] Simulation Function Block, PWLR Rolf, I am using a current source to send a current proportional to the total number of ampereturns through a resistor. I am planning to use the resistor as an amplification control, but it could be set up differently of course. I connected this function block to measure the voltage across this resistor. The array values models the flux in a particular magnetic material as a function of the ampereturns. I have not deliberately specified if it is a current or voltage source, I thought it automatically was a voltage source, but maybe that is a part of the problem? You can find the model in the Protel component library, got to; http://www.protel.com/resources/libraries/library_search.asp and search for Generic Components, Simulation and Function Block. The search should return roughly 32 matches on one page. You should find two variants of the model; PWL and PWLR. I am not sure I understand what you mean with 'part type as a parameter', could you explain? Thomas handled The output from this - Original Message - From: Rolf Molitor [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, September 27, 2002 3:15 AM Subject: Re: [PEDA] Simulation Function Block, PWLR Thomas, but what kind of signal do you want to model with the 'PWLR' ? Is it a voltage like with VPWL or a current as with IPWL (with time/value pairs as parameters) ? Where can i find this part 'PWLR', where can i find the library you got it from (what .ddb is it in) ? Maybe the 'PWLR' does take the part type as a parameter (%) ? Rolf Molitor Ing.Buero i2e Remscheid / Germany -Urspr ngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Freitag, 27. September 2002 03:41 Betreff: Re: [PEDA] Simulation Function Block, PWLR I am working with 99. The component seems to be a table with (input) x-values in one array and (output) y-values in a second array. The output/input is interpolated to create the correct output from any input value. From the model description it seems to be similar to the Simcode model PWL_TABLE. Thomas - Original Message - From: Rolf Molitor [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, September 26, 2002 2:56 AM Subject: Re: [PEDA] Simulation Function Block, PWLR Thomas, is it DXP or 99SE you are working with ? Never seen this 'simulation function block' library in 99SE and never seen the component PWLR. Is it a piece-wise linear resistor ? Just know the IPWL and VPWL sources. Rolf Molitor Ing.Buero i2e Remscheid / Germany -Urspr ngliche Nachricht- Von: Thomas Josefsson [EMAIL PROTECTED] An: Protel EDA Forum [EMAIL PROTECTED] Gesendet: Donnerstag, 26. September 2002 02:57 Betreff: [PEDA] Simulation Function
Re: [PEDA] 1020-pin BGA out-routing question (some add)
Juha, First, sorry about the delay in responding, but the different time zones make it hard to keep up. Secondly, I an certainly no guru on the subject, but can only offer you a few things to think about as you approach this board, and hopefully if someone out there knows better than I, they will step in and offer better advice. I have read both of your responses, and will try to combine all of my responses here. Ok, to start, why don't you see below,'' JaMi - Original Message - From: Juha Pajunen [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 30, 2002 2:52 AM Subject: Re: [PEDA] 1020-pin BGA out-routing question (some add) Hi, I changed the footprint, 40mil pitch with 20mil pads. VIAs between SMD pad are 16mil pad and 8mil hole, we want use this because there will be more room for routing and SOLDERMASK is bigger between SMD pad and VIA (I have 4mil opening for SMD pads and VIAs are tentd or 0mil opening; which one is better). Traces are 4mil and gap is also 4mil, need to route two trace between SMD pads, do not want make over 10 layer board... Do not change your spacing to .040 unless that is the actual spacing of your device. I only offered that because it was used in a presentation that I attended on the subject, but if I actually understand correctly, your BGA is 1.00mm spacing (actually .03937 and not .04000), and the cumulative error would definitely cause a problem on a pattern this large. Stick with what the databook calls for on the pitch, and adjust everything else to match that. If you are using an 8 mil hole in a 16 mil pad, that requires a 8 mil overall feature registration (.004 true position), which is pretty tight for an 8 by 5 inch board, and that would allow zero for annular ring, which is acceptable (for certain manufacturing specs), but forces you to use teardrops on all of your vias. I would think that you would be much better off tightening up your solder mask, and it's registration, and using the extra slop (as it were) in the rest of the design. Even if you stuck with the 8 mil hole, and kicked your pad up to 18 mils, but kept the same feature registration, you could at least avoid breakouts. Anyway, something to think about. Remember that Protel does allow you to remove unused internal pads when you generate gerbers, but I would not want to depend on this for any clearances (I would prefer to make a special via for the specific occasion and location in which I juggled the pad stack (s it were), if I had a tight spot or two and needed a little extra space. I will try and locate the number of the IPC Spec that discusses breakout in this specific situation. Also remember that when you consider overall feature registration and breakout, you also have to consider the effect on plane clearance, and remember that hole size is usually based on final hole size, after plating, while the plane clearance itself has to take into account the max drill size (including any etchback (if present)). This brings up the related subject of thermals. The via farm under a BGA usually has the effect of making swiss cheese out of any planes that run under the BGA, and you have to be very careful about how you use thermals here, because you can literally destroy any plane that is left after the normal clearance for the tightly packed vias if you are not careful. Some people demand the use of thermals under a BGA, regardless of the number of perforations in the plane due to vias, in which case, I would say that you need to be very very careful with the specific dimensions if the thermal (make one specifically for use under the BGA if necessary) and make sure that your final gerbers look OK before you ship them out and make the board. My own opinion in this case, is to NOT use a thermal at all on the via, but rather the connections to the plane direct, and then make sure that the trace that goes between the via and the actual BGA pad, is small enough (say 8 mils) that it acts as a thermal relief itself (in just the same manner as if you have a surface mount pad on an outer layer that you had to isolate from a plane (just as the Polygon Plane fill does)). This is usually enough thermal isolation from the plane itself, to not affect the soldering of the BGA, but you had better check with your assembly house (it might require some special profiling) and get their approval on this one, before you go this route, since I am sure that many people out there would disagree with me on this point. With the trace between the via and pad at about 8 mil, it will provide thermal isolation that is required for the soldering operation, but at the same time it is short enough so that it does not become too much of an inductor for those power and ground connections. You might want some other opinions on this one. Two traces per routing channel is very do-able, and respecting the actual number of layers you will need, I can't help you there, as it will take
Re: [PEDA] 1020-pin BGA out-routing question (some add)
Is there an actual datasheet for the specific device you are using? Can you provide a Mfg and PN, and possibly a link? It would help alot in seeing what you need. Thanks, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 1020-pin BGA out-routing question (some add)
Juha, OK, I looked at the layout, and the part number device, EP1S30, and did a search on the net, and came up with ALTERA STRATIX. Yes, the LVDS is in fact controlled impedance, 100 ohm differential, or you could probably route individual lines at 50 ohm. It does appear that some of the Stratix devices have the required 100 ohm termination built in, but I am not sure about yours, and this may be good providing that you are using the Stradix device as the differential receiver, however if you are using it as the LVDS driver / transmitter, then you will probably have to provide your own termination at the other end of the line. The first thing that you might want to do is look at the following ALTERA links: Ap Note for High Speed Board Design: http://www.altera.com/literature/an/an075.pdf Using High Speed Differential I/O Interfaces in Stratix Devices: http://www.altera.com/literature/an/an202.pdf These should give you some idea of just what you need to do in terms of routing, at least in the LVDS area. I looked around for some real life pinout diagrams, and only found some fairly poor tables, which would take me forever to map out. The mapping in your sample layout doesn't look quite right (although possibly it is and I am just not looking at it correctly), but I don't have the time to go over it. Can you point me to some ALTERA maps or pin out pictorals if there are any? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
