At 05:06 PM 4/10/01 -0600, Gladieux, Jed wrote:
Does anyone know how to create new design rules. For example, I would like
to flag instances where component outlines on the silkscreen layers overlap.
[using Protel 98]
Component interference rules did not exist in Protel 98. They've been added
At 09:18 AM 4/17/01 -0700, Brooks,Bill wrote:
I have a schematic that was edited by another user here that looks fine on
his machine... but when I pull it up the ports all change in length and are
not connected properly. Anyone seen this effect? Maybe I have some setting
that's wrong? or he
At 03:58 PM 4/18/01 -0600, Carlos Claveria wrote:
Hi everyone,
I have a board design complete and I have been trying to generate print
previews. Protel crashes every time I insert the bottom layer to my bottom
layer printout.
I don't have an answer as to why this might be occurring, but I can
At 10:54 AM 4/18/01 +0200, Juergen Paape wrote:
Hello User,
who can tell me , how I can get the
* component count
* pin count
* net count
report from a (hirarchical) sheet (Protel99SE (SP6))?
For me as a member of a design service company is it important to
know this for my calculation.
Here
At 04:35 PM 4/25/01 -0400, Ken Henrich wrote:
I've been unsuccessful in pulling the solder mask back around mounting holes
to let the ground plane through. My method was to place a keep out circle
around the hole on the solder mask layer and generate the ground plane. What
did I do wrong?
At 11:10 PM 4/27/01 +0100, Terry Harris wrote:
On Fri, 27 Apr 2001 07:55:37 -0400, you wrote:
Bottom line, the format is a netlist as we understand a net list plus the
physical location and dimensions of the pads.
I hope it isn't that simple - testers, particularly roving probe testers
only
At 01:26 PM 4/28/01 +0100, Terry Harris wrote:
[in response to:]
Not if it is pulled directly from the database. The Gerbers can be wrong for
many reasons.
And why can't D-356 files be wrong? Gerbers come from the database too.
Obviously any data translation has a possibility of being
At 12:07 PM 4/27/01 +1000, Geoff Harland wrote:
The following URL provides some information on the IPC-D-356 format (though
this is not necessarily the last word on this):
http://www.aceeng.com/ipc-356.html
Thanks to Mr. Harland
Bottom line, the format is a netlist as we understand a net
At 12:01 PM 5/1/01 -0700, Tony Karavidas wrote:
Has everyone received the price increase flyer from Protel? I wonder how
expensive our next 'upgrade' will be?
I haven't. So how about sharing the information, Mr. Karavidas?
Without that information, I'm going to guess that the next upgrade will
At 03:50 PM 5/1/01 -0700, Tony Karavidas wrote:
Yeah I guess thas WAS kind of a teaser.
The tools are going up $2000 starting in July (so it becomes.. what,
$8000?).
Don't exaggerate. It would be $7995. :-)
In that case, it would not be surprising to see the upgrade price be $1995.
That would
At 10:18 AM 5/1/01 -0600, Gordon Price wrote:
I am on a mission to get
PROTEL awareness of these nasty bugs! No luck yet!
It shouldn't be that difficult. They do read this list, we know, and they
pay great attention to it.
But to be more specific, if one has found a bug -- and anything that
At 09:41 PM 5/1/01 -0700, Jim Mcgrath wrote:
This was regarding my reply about Ecam.
Mr. Lomax apparently did not read it thoroughly.
Actually, I did read it; it was ambiguous on the point under discussion.
However, Mr. McGrath had written another post in which he explicitly
acknowledged the
At 05:38 PM 5/1/01 -0600, Jim Muehlberg wrote:
According to Rick Wilson, Manager of Corporate Services, from whom I
just received training at a seminar, the upgrade price will be $795 to
$995.
Let's hope he's right. That would be very reasonable, and in line with
previous upgrades.
Of course,
At 11:09 AM 5/1/01 -0700, Tony Karavidas wrote:
[...]save the tango files in ASCII
format, open them in Protel 2.8, save them in Protel, then you can open it
in Protel 98 or 99.
Last time I asked, Protel supplies a copy of Advanced PCB 2.8 to any
licensee for a subsequent PCB version.
If you
At 02:19 PM 5/2/01 +0100, Jason Morgan wrote:
[...]
Opening a document reported that the access record is in use, crashing the
machine.
Any other machine opening the same sheet now crashes with the same error.
Shall we assume that there has been an attempt to repair the database with
the repair
At 12:51 PM 5/2/01 +1000, Linden Doyle wrote:
My apologies if this reply appears ignorant - I have not been following
this thread as it has no immediate relevance.
On the contrary, Mr. Doyle has scooped us. No one else writing in this
thread seemed to be aware of the Protel IPC-D-356
At 04:02 PM 5/4/01 -0500, Ted Tontis wrote:
What about [...] the recent
partnership with P-CAD 2001 []
Actually, if you go to buy a Protel license now, in the U.S. you order it
from
Accel Technologies.
That's full circle from a dozen years ago.
(It's not a partnership, Protel now
At 09:03 AM 3/26/01 -0500, Robison Michael R CNIN wrote:
well i must have got wires crossed, cuz i went to the lafayette
room at 7:30 thursday evening
7:30 Thursday morning
Yes, I know, kind of hard to believe
oh well... disappointed i didn't get to meet some of you, though.
Me too.
with a lifetime
license.
i.e., lifetime upgrades. A highly-placed Protel employee actually once told
me you should not have to pay another penny for the rest of your life. I
take that as an enthusiastic thank you, not as a contract
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design
Okay, so now my question:
I used to frequently specify 65 mil max radius for inside corners,
imagining that this would allow the fabricator to use a 125 mil diameter
router bit. Now, generally, these corners were, in fact, not very critical.
What router bits would be standard and what would
At 09:53 AM 5/7/01 +0100, [EMAIL PROTECTED] wrote:
Dear Mr. Lomax,
that would be good news, but is there any chance in getting this a little
more precise?
That's up to Protel. For all I know they could be upset that someone
spilled the beans. Or they could be glad that a little information is
A publicly accessible archive has been established for this list.
http://groups.yahoo.com/group/protel-users-PEDA-Archive/messages
Generally, this archive does not show user e-mail addresses unless they are
in the body of the message. Archiving on yahoogroups began yesterday; we
will be
At 01:51 PM 7/6/01 -02-30, Fabian Hartery wrote:
I do know if it is unique to my installation, but the relative origin for
the placement of power ties and grounds seems to change almost at random.
What I mean by this is, the zero (mouse) location for the power tie changes
and I have to recenter
At 01:52 PM 7/6/01 -0700, Dennis Saputelli wrote:
my god, i never saw the Layer Stackup Legend menu item on the Tools Menu
It seems to me that I remember seeing it. But it is not there now in my
installation of 99SE SP6. I'm going to go search the Knowledge Base.
[EMAIL PROTECTED]
Abdulrahman
At 11:51 AM 7/9/01 -0500, Frank Gilley wrote:
Wow, I never knew that hidden Tab box was in the layer stackup
legend. That feature has suddenly become useful !
Who would have guessed that it was only available after selecting the
first corner? How is it that we are supposed to just know about
At 02:19 PM 7/9/01 +0200, [EMAIL PROTECTED] wrote:
Hi all,
in the definition of the rule for Matched Net Length there is an item
called gap. Does anyone know what this is supposed to be and how to alter
it? In the respective properties window there is no such item.
At 03:33 PM 7/9/01 +0200, Joop Reekers wrote:
Yes, this way they are properly copied and pasted.
I only need the resulting tracks of the polygons to build a simple cluster.
Thanks for the tip (or workaround)!
If you only need the resulting tracks, you could also explode the polygon,
which
At 10:19 AM 7/9/01 -0400, you wrote:
I wonder if it's possible after creating a lot of duplicates, you
could export all the copied parts fields into a spread sheet, in the
spread sheet, import past over the fields from you supply data base
directly into Protel's spread sheet and make
-- a $50 credit toward publications, *and* you get the publications at the
member prices.
The sizes of FR-4 material marked in the chart as low cost are, in mm.:
0.07
0.11
0.13
0.18
0.26
0.32
0.37
0.43
0.53
0.61
0.64
0.74
1.52 is not given the lowest cost value, but it is very available.
Abd ul
At 09:21 AM 7/9/01 -0700, Brad Velander wrote:
Mark,
I read your comments and went to my IPC-. I am no IPC expert by
any stretch but aren't the tables you specify (4-2 ... 4-6) only for copper
clad laminates, where are the prepregs? Or is this a typical IPC f***up and
they have
First of all, none of what I have written was intended as a personal
attack, you stupid idiots!
***JOKE!!!*** No one writing here is stupid, though sometimes some of us
could use a little coffee.
At 05:41 PM 7/9/01 -0400, Michael Reagan wrote:
Abdul and Brad,
If your design is critical to a
At 08:55 PM 7/9/01 -0400, Mike Reagan wrote:
I would like to correct you about the discount IPC offers. The coupon they
issue to the designers council members is not redeemable, you must be an IPC
member not a member of the designers council. They must have started this
policy this year
At 07:22 AM 7/10/01 -0400, Mike Reagan wrote:
I know what the website says, I also know what my hard earned money
says... I just purchased manuals about 2 months ago and had to pay full
price.Read my last post again , The IPC will not accept your coupon
unless you are full member of the
At 09:18 AM 7/11/01 -0700, Tony Karavidas wrote:
Here's one for that support person:
I recommend you find another way to get a paycheck.
Ok, sillyness aside, that was a stupid answer on their part. They could have
said can you temporarily try another printer to see if the problem goes
away?
At 02:31 PM 7/11/01 +, Joe Morris wrote:
I have a requirement for a very long board ( 1m) but am
having difficulty finding anyone capable of producing this size of
board. It would seem that 600mm is the normal max. If anyone in the
group knows of any specialist PCB houses that could help me
At 09:43 PM 7/11/01 +1000, Ian Wilson wrote:
Does sound like a bug - I will await other comments before adding it to
the bug database. I suppose someone will try to call it a feature...
It's not a bug, in my opinion, but neither is it a feature. The lack of a
facility is almost never a
At 09:21 AM 7/12/01 +1000, Ian Wilson wrote:
{I wrote:]
It's not a bug, in my opinion, but neither is it a feature. The lack of a
facility is almost never a feature. Perhaps I missed something, but if I
did not:
Your right - you did miss something. Look at the advanced options for Sch
At 02:04 PM 7/12/01 -0400, Brian Guralnick wrote:
Actually, there might be a dirty way to do almost exactly what you want.
Brian's dirty way, I think this should work, haven't tried it yet.
I did try it before writing my post on this subject, and I gave the results:
Another path, through the
At 02:18 PM 7/12/01 -0400, [EMAIL PROTECTED] wrote:
I just ran the full DRC and it's a bit worked up. I'm not sure I understand
what it's trying to tell me.
Violation Net NetR100_2
Warning - Connection to overlapping split planes
I think this means that R100 is placed over two
At 04:03 PM 7/12/01 -0400, [EMAIL PROTECTED] wrote:
Protel is doing its job. I'm looking for a better way to do my job.
Yes. Some designers would just suffer through, perhaps cursing the program
because it is limited in certain ways. But it is not as limited as it might
seem, so the small
At 05:17 PM 7/12/01 +0100, Steve Wiseman wrote:
Hmm. If you use numeric allocation offset (start this sheet at 100, etc),
the annotator gets it completely right - no allocation re-use. This is a
straightforward, easy to understand, bug. We've all done similar.
Actually, it does not get it
At 07:30 AM 7/13/01 -0700, John Williams wrote:
Take a look at the (freeware) server called Reference Designator
Modifier on the downloads page of:
http://www.qualecad.com/
It can add arbitrary suffixes and/or increment reference designators of
user selected schematic and PCB components.
At 10:27 AM 7/13/01 +0100, Steve Wiseman wrote:
[some response which was rooted in a misunderstanding of the full meanings
of my statements. It appears that we both agree on how the program actually
works and any differences were only semantic. It is moot who said it the
most correctly.]
If
Because the question frequently arises of how to connect two or more
grounds while maintain DRC and the separation of the grounds except at a
single point, and because the instructions as to how to do this can be
misinterpreted, I have uploaded to the protel-user filespace a PCB file
with two
At 01:05 PM 7/17/01 -0400, Darryl Newberry wrote:
Given that:
a) I have a new PCB with final placement of footprints whose ref
designators I wish to retain,
b) some footprints specified in the schematic are not in the PCB but are
in a project library local to the DDB,
c) the PCB contains some
At 11:36 AM 7/17/01 -0700, Konrad Iten wrote:
In the Client99SE.ini under system preferences is a line called
DisplaySplashScreen=True.
Just change true to false and there will be no splash screen anymore.
I too had been afflicted by this annoying little bug and had not noticed
the conditions
At 09:07 AM 7/18/01 +0200, Edi Im Hof wrote:
Place a pad (on grid) outside of your set of components and select it also.
Then this pad will be on one of the four corners of the movin box and you
can use it sa an on grid anchor.
The problem the user was having is probably related to a bug that
Hey, folks, please delete the extra stuff at the bottom of your message
when you reply!
At 05:03 PM 7/18/01 -0400, Jeff Adolphs wrote:
Thank You!
When I tried moving the files to a new directory the .ddb file did not
recognise the new file names.
I deleted the .ddb file, tried to open the .prj
At 12:07 PM 7/19/01 -0500, Frank Gilley wrote:
I have had a few DDBs get corrupted, and there really isn't any fix for
them that I know of. Be prepared to lose every file in the DDB, although
you usually won't. Please don't depend on the the Fix Database option- it
usually doesn't help
At 02:06 PM 7/19/01 -0400, Jeff Adolphs wrote:
Do you have any problems with Data Base Files crashing? I was thinking
maybe the reason I had a data base corrupt was because I was using the
Windows File System. I want to use which ever is more stable.
It is not clear to me that either system is
At 01:50 PM 7/23/01 -0500, Ted Tontis wrote:
Would there be any interest in a PCB footprint lib. with all the parts you
would ever need for free. I ask this because I am working on trying to get a
large lib. in Protel. It would have the silk screen, a fence that would be
on the last electrical
At 02:25 PM 7/23/01 -0500, Frank Gilley wrote:
I do an autobackup every 15 minutes. That means that if the database were
corrupted, all I would lose would be fifteen minutes of work. There are
*also* backups made every time a file is overwritten. So save often. But
I haven't lost a file since
At 11:22 PM 7/23/01 +0200, Edi Im Hof wrote:
At 14:25 23.07.01 -0500, you wrote:
snip
5. Every 15 minutes, the BKx files are progressively overwritten with a
corrupt file. Go have some lunch or something and they are all
corrupted, depending on your settings.
Protel is, as far as I know,
At 12:03 PM 7/25/01 +1000, [EMAIL PROTECTED] wrote:
Taking just the
semiconductor footprints, thats
1067 footprints that will be bundled into the super library that someone
will be
remaking. Or will these footprints
just be copied from the existing Protel libraries? If these seperate
At 09:29 AM 7/25/01 -0500, Ted Tontis wrote:
As designers we sometimes have to make the impossible happen, and we
do make it happen. So why then all the negative remarks?
All I know is that if you want to accomplish something valuable, get used
to it. It is *much* easier to sit back
At 01:11 PM 7/25/01 -0400, Bagotronix Tech Support wrote:
As far as verification of parts goes, I oppose any bureaucratization that
would hinder or slow down the footprint distribution process. This sounds
like more total quality management business school bullsh*t. The buyer
beware - free
At 02:07 PM 7/25/01 -0400, Andrew J Jenkins wrote:
The problem, as I see it, with traffic in multiple locations is that it's
end result is fragmentation of the group and
Meeting in committee is hardly fragmentation. The records of the
committee are open to the public and will remain so, and
At 03:06 PM 7/26/01 -0400, chris mackensen wrote:
because
cadence's files are all OPEN and TEXT based and NOT ENCAPSULATED in a
DATABASE (and NOT BINARY), it was a matter of my perl script just parsing
Excel sheets of pin data (automatically saved as text files over the web)
and generating the
At 12:29 PM 7/27/01 -0700, Schattke, Carl wrote:
I have test points on both sides due to the high density of the product.
I am using vias for test points in some locations, so if I give them a
negative expansion
then I will be covering my testpoints with mask.
Making parts for each
At 06:16 PM 7/27/01 -0400, Bagotronix Tech Support wrote:
I am trying to open an Orcad DSN file into Protel 99SE with no success. The
message I get is:
Error reading Orcad Cache!
Try to Cleanup Cache first!
Any idea what that means and how to work around it? Or is this another
Protel
I find this discussion rather weird. Here's why:
UCE, unsolicited commercial e-mail, is considered particularly offensive
when it is not targeted, such as a mailing to a million addresses with
Need to make money fast? I think we all would agree that this is *spam*.
It wastes a small amount of
At 05:40 PM 9/3/01 +1000, Don Ingram wrote:
Just got PCB Fab Magazine noticed that they are running 10 micron wide
traces.
Better make the virtual shorts way less than the customary 1mil
The customary gap for virtual shorts based on unfabricatable gaps is on
the order of 4 micro-inches, which
Indeed, with the default font, the dot on the i is missing in gerber. It
also disappears in draft display mode.
I looked directly at the gerber file; there is no attempt to draw the dot.
It is not a case of a zero-length draw.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA
/Measure Distance, you may need to be
on a fine grid.
Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
Easthampton, Massachusetts, USA
(413) 282-0013, efax (419) 730-4777
[EMAIL PROTECTED
At 08:56 AM 9/5/01 +1000, Ian Wilson wrote:
Abd ul-Rahman, I agree with your comment that it can be depressing when you
are told not to do something rather than how...but...
I agree completely with:
We take the view that any socketed items are actually part of a higher
level assembly than
At 09:56 AM 9/5/01 +0200, Florian Finsterbusch wrote:
On our multilayer board the top and bottom layer should be connected to GND.
For that purpose we have placed polygons on both layers.
The polygons are connected to the GND net.
The pads should be surrounded by arcs.
Grid Size = 0.2 mm, Track
At 01:23 PM 9/5/01 -0700, Brad Velander wrote:
With your method, which works just fine, I find that having EBC, GDS
or AK on the schematic is just too stupid and redundant. Who needs it?
Well, EBC etc. is explicit, whereas 1,2,3, etc. depend on additional
context. If you have to work
At 04:23 PM 9/5/01 -0400, Phillip Stevens wrote:
How does one specify a Net not be routed, but still be checked
for in the ERC? I have a pretty simple 2 layer board. 2 X 2.7
with a few parts on it. I'm using P99SE SP6 on Win98
What I wanted to do was to route all the signal lines first and
At 09:10 AM 9/6/01 +1000, Ian Wilson wrote:
I am searching (part time) for a better method of maintaining the bug
list. I am thinking something along the lines of the Bugzilla project as
used by the Mozilla people (http://www.mozilla.org/bugs/). Or something
similar.
What I would like is:
I'm just letting the list know that I'll be at the Protel Users meeting
sponsored by Altium at the conference next week. See you there!
Abd ulRahman Lomax
Chair, Protel Users Association
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
At 01:48 PM 9/6/01 -0400, [EMAIL PROTECTED] wrote:
Well, this one got out to me. But I just got one of the bounce messages that
I've seen from several users today. It seems TechServ has a problem at their
end. Sure would hate to get unsubscribed - this list has been a lifeline at
times.
Since
At 11:09 AM 9/7/01 -0400, [EMAIL PROTECTED] wrote:
Does anyone else have this problem
and have you found a work around other than the test Engineer changing the
pad designators globally. Changing the pads works, but there is a risk that
the file could leak out of his dept and into the released
At 02:54 PM 9/8/01 +0200, Soren Juel Andersen wrote:
If you support the EBC, AK system, how many pin does a package need to have
before you switch to
numbers?
I think that was previously answered, but I will answer it again. When
there is a standard numbering for a part, one uses numbering.
At 05:53 PM 9/6/01 -0500, Jeff Stout wrote:
I really hesitate to follow up this thread because nobody is
going to change anybody else's mind.
I am not writing to change people's mind, at least not the mind of people
who are set in their ways. Rather, I'm writing to examine the issues, and,
as
At 11:55 AM 9/10/01 -0500, Mark E Witherite wrote:
Does anyone know how to move/remove the credit text from the Camtastic
printouts? I tried to use the printouts to check my Gerbers and CAM
products 2000(TM): file name is printed right in the middle of my
plots. It would be nicer if it were
At 08:15 AM 9/13/01 -0700, Brad Velander wrote:
2) Yes, there is an independent Protel Users Association archive on Yahoo
groups. I do not know how complete it is or any other specific details about
it. You will have to setup an account for yourself and find the Protel
groups. A search for the
At 02:15 PM 9/14/01 -0700, Jeff Lewis wrote:
Come on Samuel! Direct your anger where it'll do some good! Misspelled words
are just that!
~j
Perhaps as a Cadence employee he's taking his frustration out on us! :-)
(That's a joke, just as I trust Mr. Cox's comment was intended to be, but
he
At 06:04 PM 9/14/01 -0700, Mike Ingle wrote:
I need to keep several mm clear around an op amp input. On the power planes
this is easy, as I just place a fill on the plane, and that removes the
copper (I hope).
I am also placing a gnd pour on the top and bottom layers. I have found
that a fill
At 07:18 AM 9/18/01 -0500, Robison Michael R CNIN wrote:
this is just a comment post and not a question.
i wrote about a month ago about a problem i was having with not
being able to assign multiple names to the same net. although
this sounds like an unreasonable, unnecessary, and dubious
At 10:36 AM 9/18/01 -0700, Afshin Salehi wrote:
I have been having a problem trying to create a pad with a .125 hole
and .225 pad size. I am trying to place six smaller holes on the pad
area of the large hole to create a screw hole with very hood through
board connection.
I'm puzzled
At 01:36 PM 9/18/01 -0400, Richard Sumner wrote:
I tried that, it finds all unconnected pins (which I have a lot of) and
did not find a named net with only one connection (just a net name on
only one unused pin). The single pin net does appear in the netlist
(generated from the pcb), so it
At 02:22 PM 9/18/01 -0500, Ted Tontis wrote:
I believe he is trying to put supporting holes around the top of the PTH.
I'd like to know what a supporting hole is, since holes remove physical
support.
Holes placed for additional ground connection would be likely to make only
a negligible
At 01:12 PM 9/18/01 -0700, Brad Velander wrote:
Abd ul-Rahman or others,
if I read his description correctly he is trying to do a plated
mounting hole with additional vias within the diameter of the larger pad for
the plated thru-hole. I am guess that he is trying to make this as a
At 03:16 PM 9/18/01 -0500, you wrote:
if one was to use a hole for mounting the PCB to a fixture, they might put
plated through holes around the mounting hole for reinforcement. The extra
copper in the vias around the hole would support more pressure in that area.
I have never implemented this in
At 10:10 AM 9/20/01 +1000, Saddle wrote:
The problem I seem to have alot is knowing where the edges
(boundaries) of an existing polygon are when laying down the next one beside
it. This may sound strange, say just lay one over the other, but sometimes
protel wants to redraw/recreate the polygons
At 04:34 PM 9/21/01 -0500, Mark E Witherite wrote:
I was going to let the group how I made out with the virtual short I was
planing on using on my internal planes. After a short discussion We
decided not to do it. Our main concern was there was no way to test the
PCB to be sure that the nets
At 08:23 AM 9/25/01 +0200, Edi Im Hof wrote:
At 11:47 24.09.01 -0700, you wrote:
At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote:
The issue with the virtual short is that it must be cut to test
the two nets.
Has somebody tried to make the virtual short not virtual but real?
I mean,
At 07:50 AM 9/25/01 -0700, Dwight Harm wrote:
I want to have a non-rectangular void on a ground plane, but it appears I
can't put a polygon there, only a rectangular fill. When I place a polygon,
my plane layers don't show up in the drop-down box for choice of layer.
Right. Protel reserves
At 02:47 PM 9/28/01 -0700, [EMAIL PROTECTED] wrote:
Only the fact that nets are never assigned in a footprint editor.
But the field in the properties window is there with 'No Net' assigned,
and the pull down menu works with only that one option.
Sure, after all, why write a different pad
At 11:38 AM 9/29/01 -0400, Bob Wolfe wrote:
Just have a
little reservation about converting any free trace to a net it was attached
to, so I ran DRC's before
running this function.
After running the update function, reloading the net list (through the
Synchronizer, not the direct Netlist Load)
***
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At 11:07 AM 10/1/01 +0100, Richard Thompson wrote:
***
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At 01:46 PM 10/1/01 +0100, Richard Thompson wrote:
If
***
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At 09:27 AM 10/1/01 -0500, Robison Michael R CNIN wrote:
i'm not sure
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At 03:27 PM 10/1/01 -0500, Jon Elson wrote:
However, what I would have
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At 02:02 PM 10/1/01 -0700, Dwight wrote:
Yes, the part type is often
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At 02:50 PM 10/1/01 -0700, Brooks,Bill wrote:
the BOM utility doesn't
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At 01:05 PM 10/2/01 -0500, Mark E Witherite wrote:
I'm now viewing the
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At 01:05 PM 10/2/01 -0500, Mark E Witherite wrote:
When back to PCB
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At 09:47 AM 10/3/01 +0300, [EMAIL PROTECTED] wrote:
By the way, why do
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At 08:21 AM 10/3/01 -0400, [EMAIL PROTECTED] wrote:
The RSI.com that I
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