Re: [PEDA] OT Veroboard design tool

2003-02-20 Thread Danny Bishop
WHICH YOU CAN PURCHASE FOR AS LITTLE AS $40.00 EACH WHICH INCLUDE SOLDER MASK AND SILK IF REQUIRED, AND TURNING YOUR SCHEMATIC INTO A PCB DESIGN MAY NOT BE MUCH MORE. GOOD LUCK, MIKE - Original Message - From: Danny Bishop [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL

Re: [PEDA] OT Veroboard design tool

2003-02-19 Thread Danny Bishop
hi All Does anyone know of a cheap program to assist in designing a board for manufacture from veroboard cheers Danny * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: *

[PEDA] Placing a ground link on the PCB

2002-12-19 Thread Danny Bishop
hi ppl what is the easiest way to stop short circuit DRC errors (but still keep the grounds separate elsewhere) on a component that is just a copper trace that connects two different grounds in one spot. thanks Danny * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a

Re: [PEDA] Placing a ground link on the PCB

2002-12-19 Thread Danny Bishop
should make this a feature) There is a description of how to do this in the archive. Ian Capps - Original Message - From: Danny Bishop [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Friday, December 20, 2002 9:59 AM Subject: [PEDA] Placing a ground link

Re: [PEDA] OT - Complex boards and time to Layout?

2002-09-25 Thread Danny Bishop
funnily enough it never happened to me, I have never found a fault on my boards, and hence don't concern myself too much with the tests on basic double sided. -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Thursday, 26 September 2002 9:54 AM To: Protel EDA

Re: [PEDA] Copper fill for thermal reason.

2002-08-25 Thread Danny Bishop
hi Ian interesting requirements. What is the application, and what sort of temperature levels and stability do you require? Why do you need to connect the thermal areas to system EARTH (is this power earth, if so you will be trying to cool rather a large thermal mass!) I will be monitoring to

Re: [PEDA] Matched Lenghth Constraint

2002-08-15 Thread Danny Bishop
? - Original Message - From: Andrew Jenkins [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Thursday, August 15, 2002 10:02 AM Subject: Re: [PEDA] Matched Lenghth Constraint -Original Message- From: Danny Bishop [mailto:[EMAIL PROTECTED]] ... I

Re: [PEDA] Matched Lenghth Constraint

2002-08-15 Thread Danny Bishop
Warning Unable to process data: multipart/mixed;boundary==_NextPart_000_004E_01C2451C.2159A880

Re: [PEDA] Matched Lenghth Constraint

2002-08-14 Thread Danny Bishop
hi I wonder what conclusion we can draw from any potential benefits of using a thick trace for a tricky trace, but thinning it down when required to get through tight spots? cheers -Original Message- From: Harry Selfridge [mailto:[EMAIL PROTECTED]] Sent: Thursday, 15 August 2002

Re: [PEDA] Well, here it comes.....

2002-07-22 Thread Danny Bishop
their their Darren (and Tony) -Original Message- From: Darren [mailto:[EMAIL PROTECTED]] Sent: Monday, 22 July 2002 4:29 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Well, here it comes. That may be so, but it was not the way the real release had had it, it was made by

Re: [PEDA] 90 degree C?

2002-07-18 Thread Danny Bishop
: Thursday, 18 July 2002 5:22 PM To: Protel EDA Forum Subject: Re: [PEDA] 90 degree C? Most of the ICs we use are only rated to 85 deg. C operating range. I'd hate to troubleshoot a board running 130degC components. -Original Message- From: Danny Bishop Sent: Wednesday, July 17, 2002

Re: [PEDA] 90 degree C?

2002-07-17 Thread Danny Bishop
hi Basically FR4 should run up to 130degC, and your semiconductor can most likely handle this temperature (but need to assess the reliability based on the manufacturers rating and your derating req's). I would consider thermal transients that can cause The biggest problem I have had is the

Re: [PEDA] 90 degree C?

2002-07-17 Thread Danny Bishop
Warning Unable to process data: multipart/mixed;boundary==_NextPart_000_0076_01C22E52.7E613150

[PEDA] Auto Placing

2002-07-03 Thread Danny Bishop
HI All I have a very tight design, and want to see whether I can physically fit all my components on the board - this seems to be an appropriate use of the auto placer. Whenever I use the statistical placer the file crashes, and the cluster placer seems to ignore the keep out layer and component

Re: [PEDA] Auto Placing

2002-07-03 Thread Danny Bishop
EDSI - Original Message - From: Danny Bishop [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, July 03, 2002 8:52 PM Subject: [PEDA] Auto Placing HI All I have a very tight design, and want to see whether I can physically fit all my components

[PEDA] LT1161 Simulation Model

2002-06-30 Thread Danny Bishop
HI everyone I would like to find the a simulation model for the LT1161 chip, I have checked LT and Protel, are there any other avenues to investigate. Danny * Tracking #: F2DCC47C4C75004BB70E2F4168CA0E8955DE4973 *

Re: [PEDA] Issues related to Excellon Format and Scoring

2002-06-04 Thread Danny Bishop
HI all with regards to below: scoring (or v-grooving) is a cheaper way to manufacture boards as the scoring tool has to remove less material, so it can move a lot faster. The boards will be a lot cheaper with this method. The tradeoff is that you need more clearance from copper and components

Re: [PEDA] Size of New Component Designator and Comment

2002-06-04 Thread Danny Bishop
drives me crazy! can't fix it either -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 5 June 2002 6:29 AM To: Protel EDA Forum Subject: Re: [PEDA] Size of New Component Designator and Comment At 06:27 AM 6/4/2002 -0400, [EMAIL PROTECTED]

Re: [PEDA] Issues related to Excellon Format and Scoring

2002-06-04 Thread Danny Bishop
thing! must have slipped) anybody know any scientific method of specifying V groove depth for the given board weight and size? sometimes the fabricator will ask me this question and i usually answer to do what you usually do Dennis Saputelli Danny Bishop wrote: HI all with regards

Re: [PEDA] Soldering Techniques

2002-05-31 Thread Danny Bishop
technique (e.g some fab houses recommend that rectangular SMD chips like SO-16 packages be placed parallel to the horizontal axis of the board so that pins on both sides receive equal intensity wave). Regards, Adeel -Original Message- From: Danny Bishop [mailto:[EMAIL PROTECTED

Re: [PEDA] Soldering Techniques

2002-05-30 Thread Danny Bishop
HI Adeel Wave soldering is only choice for soldering through hole parts in bulk. You can potentially save money by putting SMD parts on the opposite side to the thru hole parts and solder them all in one go. Wave soldering is not as reliable as reflow however, and requires adherence to fairly

Re: [PEDA] footprint for smd or through-hole oscillator

2002-05-27 Thread Danny Bishop
can I suggest that you make the schematic symbol with four pins, one for each of the four pads, number them one to four, and connect pin one and two, and three and four in the schematic editor. alternatively place pins one and two on top of each other, and three and four on top of each other.