[PEDA] [PROTEL EDA USERS]: ftp place for ddbs

I think that http://groups.yahoo.com/group/protel-users/files/ is a good place for us to put ddbs. (It already has sample ddb named LayerStackSample.zip). Please tell me if you find a better place. (I like the directory structure Phillip suggests). Jim Parr [EMAIL PROTECTED] on 2001-02-03

[PEDA] [PROTEL EDA USERS]: Why does symbol change shape ?

Dear Bryan Bernesi, I run ERC all the time (Tools | ERC | OK), and I've never seen it change any of my schematic symbols. Would you be so kind as to help me reproduce this problem ? You could put a file that demonstrates this weird behavior in

Re: [PEDA] [PROTEL EDA USERS]: Archive not working

:(bcc: David Cary/TULSA/BRUNSWICKOUTDOOR) Subject: [PROTEL EDA USERS]: Archive not working I tried to look at some of the archived postings at http://angelfire.lycos.com/electronic/protelarchive that Ian Wilson set up, but it doesn't seem to be working. The thread date view lead to http

Re: [PEDA] [PROTEL EDA USERS]: Best layer arrangement

: From: David Cary I suspect this interlayer capacitance idea is a red herring ... Don't you believe it! The interplane capacitance is far and away the highest performance capacitor available on a board. An 0603 size, 1000pF capacitor will have a self resonant frequency in the order of 70MHz

Re: [PEDA] [PROTEL EDA USERS]: Library Management

a ``gate decal'') and naming footprints (which Baldwin calls a ``pcb decal''): PCB Design Guidelines:Naming Conventions http://www.baldwin-tech.com/designgu.htm I keep thinking there ought to be a better way. -- David Cary

Re: [PEDA] Printing drill marks on Gerber output

Dear Nicolas, Have you tried making a drill guide ? Under CAM Manager, right-click Gerber outputs and choose Properties, then look at the Drill Guide tab to see that it's enabled. While you're there, go to Advanced and do Position on film: Reference to absolute origin. This draws a little

Re: [PEDA] 72 pin SIMM board outline

Dear Steve Smith, Maybe you could find some info here ? The uCsimm module is a microcontroller module [on] a standard SIMM form factor. http://www.uclinux.org/ucsimm/ has been used as ... a webserver -- David Cary original message Steve Smith [EMAIL PROTECTED] on 2001-03

Re: [PEDA] BOM

of text in the BOM. Is there an easier way ? I've seen some drawings that have a schematic, assembly drawing, and bill of materials all on one piece of paper. I think they were done with AutoCad. -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto

Re: [PEDA] Info about PCI specs

conservative, they usually still work OK, as long as the motherboard and all the other cards stay within spec. -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com

Re: [PEDA] PCB printed self

#short . What is a ``self'' on a PWB ? -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email

Re: [PEDA] Reference

with general (non-Protel-specific) design tips. Is there a single ``electronics design tips and traps'' FAQ somewhere I could link to, rather than have this duplicated in the FAQ of each and every CAD tool ? -- David Cary Peter Schoepe wrote: you could look into the data books from different CMOS gate

Re: [PEDA] [PROTEL EDA USERS]: graphic images lost

Dear Tim Coleman, [I haven't actually done this, I'm just speculating.] You have the image in a .gif file, right ? (.png is a little bit better, but I don't think paint can handle it yet). Try importing the file itself into your .ddb: while inside Design Explorer, click the Explorer tab

[PEDA] schematic library tips

the same relative position. Is there a standard way to indicate (on paper) which pins are input and which pins are output on a (b)-flavored schematic symbol ? Does anyone actually use the Hi-Z pin type ? -- David Cary schematic design tips: http://groups.yahoo.com/group/protel-users/files

Re: [PEDA] Schematics to Netlist Integrity question.

are wires. Please tell us if you find any other cases where connections on the schematic don't show up on the netlist -- that would be a serious bug. -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list

Re: [PEDA] Arc's in the keepout

with layer-specific keepouts ? For example, pick the BottomLayer tab and use P (Place) K (Keepout) T (track) -- those tracks block stuff on the bottom layer, but let stuff on the top layer through. -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto