Re: [PEDA] Solder and Paste Masks for Via in Pad BGAs
Ian, For some reason when I originally went to put a pad on the top solder layer, I could not find it! I am not sure what I had done, but my best guess is that I was trying to place a via rather than a pad. Thanks for getting me to recheck this, as I do not like to use the update primitives unless I really have to. The only disadvantage I see is that you must specify the solder mask pad size to include the expansion around the BGA pad in the component library, rather than allowing it to be specified in the board rules (I am not real sure if a rule can be set up to allow expansion for a pad that exists on the TopSolder layer. I tried it and it did not appear to work, but I need to investigate further.) David Ian Wilson wrote: On 01:12 PM 1/06/2002 -0500, David W. Gulley said: Richard Sumner wrote: David, Talk to your assembler before you invest time in this. The paste mask becomes a metal stencil for applying the solder paste. So donuts will not work (the donut hole is unsupported). Actually my idea was to make the width of the track greater than 2x the radius of the arc so I would end up with a filled donut. (For example if I want a 30 mil opening in the paste mask, I could use a 20mil wide arc with a radius of 5mil.) However, what I have just tried that seems a bit simpler is to use a pad and a via (gee a via in a pad!) where the pad is TopLayer only and the via is set for tenting. Do an update free primitives after import to the PCB and viola... Alternatively, you can use thru-hole pads fully tented (see the advanced tab of the pad properties) and add another single layer 0mm hole size pad on just the *top mask* layer. Make sure you don't tag this one as tented - a tented mask pad makes for nothing (a small improvement in P99SE would be that single layer pads on the mask layers can't be tented). This works OK. So you fully tent and then open the mask manually in a controlled fashion. P99SE allows pads to exist on non-copper layers - a great thing I think. This way may have a small advantage over your method as it does not require two copper primitives - that then have to be updated to force the pads nets onto the accompanying vias. You may need to muck about with the paste layer as well to close it off as required - but you have this issue regardless. Ian Wilson Considered Solutions Pty Ltd mailto:[EMAIL PROTECTED] ABN: 96 088 410 002 5 The Crescent CHATSWOOD 2067 Ph: +61 2 9411 4248 Fax: +61 2 9411 4249 -- David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Solder and Paste Masks for Via in Pad BGAs
I am doing some via-in-pad BGAs and need to figure out if there is a good way to provide the top solder and top paste masks while keeping the bottom solder mask and bottom paste masks off. I defined the BGA pads as multilayer since I am doing via-in-pad (sort of like it was a PGA) except I do not want holes in solder mask on the bottom and I do want holes in the paste mask on the top. I have tried several rules combinations without success, and so far the only way I can see to do it is to: 1) set the solder mask for tenting (no openings top or bottom) in pad specification (advanced tab). This makes sure I have no openings in the bottom solder mask. 2) draw arcs (donuts) on the top solder and top paste layers for each pad where the trace width of the arc is such that there is no hole in the donut and the outer edge matches the opening required in the masks. Does anyone have a better solution? David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Solder and Paste Masks for Via in Pad BGAs
Richard Sumner wrote: David, Talk to your assembler before you invest time in this. The paste mask becomes a metal stencil for applying the solder paste. So donuts will not work (the donut hole is unsupported). Actually my idea was to make the width of the track greater than 2x the radius of the arc so I would end up with a filled donut. (For example if I want a 30 mil opening in the paste mask, I could use a 20mil wide arc with a radius of 5mil.) However, what I have just tried that seems a bit simpler is to use a pad and a via (gee a via in a pad!) where the pad is TopLayer only and the via is set for tenting. Do an update free primitives after import to the PCB and viola... Big BGA's are a pain. If you could only get the designer to use only the two outer rows ... Unfortunately, I am the designer on this one and I have to go 10 rows deep (31x31 with all positions used! At least the inner most pins are power and GND. Actually the 4 corners are missing so its only 957 pins.) In the past I have always used dogbone connections between BGA pad and via, but this time there are requirements for via-in-pad (which I do not like or trust, however the customer is always right if he persists in a decision that he has been warned against!). But, I really wish for better control of the pad stacks (including ALL layers). David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Solder and Paste Masks for Via in Pad BGAs
I do not want a circular block in the center of the pad. For this board using Via in Pad: The board fabrication process drills a through hole through the board and plates the holes (so far just like any other plated hole). Then they plug the hole in the BGA pads using a process that leaves the BGA pad flat. If I use a though-hole pad, I do not get a hole in the paste mask (but I do get holes in both top and bottom solder masks). I still need a circular hole in the top paste mask. I was considering using an arc placed on the paste mask layer over each of the BGA pads. If the width of the trace used to create the arc is greater than 2x the radius, there will be no hole in the donut. Using the example of a 20mil wide track used for a full circle arc with a 5 mil radius (measured to the center of the track); the outside edge of the track makes a 30mil circle, the inner edge of the track covers (by 5mil) the center of the arc. Its a filled donut! How would you place a circle on the paste mask layer? David Dwight Harm wrote: If I understand this, it still can't work. The paste-mask stencil has an opening for the pad, and you want a circular block in the center of the pad -- but there's nothing to support it. -Original Message- From: David W. Gulley Sent: Saturday, June 01, 2002 11:13 AM Richard Sumner wrote: David, Talk to your assembler before you invest time in this. The paste mask becomes a metal stencil for applying the solder paste. So donuts will not work (the donut hole is unsupported). Actually my idea was to make the width of the track greater than 2x the radius of the arc so I would end up with a filled donut. (For example if I want a 30 mil opening in the paste mask, I could use a 20mil wide arc with a radius of 5mil.) However, what I have just tried that seems a bit simpler is to use a pad and a via (gee a via in a pad!) where the pad is TopLayer only and the via is set for tenting. Do an update free primitives after import to the PCB and viola... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Too many hole sizes
[EMAIL PROTECTED] wrote: SNIP 1. Drill bit manufacturers normally make tools with diameters in the range 0.3 - 6.5mm (0.012 - 0.256) in step of 0.05mm (0.02). SNIP I believe that should be 0.05mm (0.002) If all I could get was 20mil increments I would be in a real predicament! David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Too many hole sizes
I just spent a morning trying to resolve why my Drill Drawing Gerber plot was showing a whole bunch of holes as size 0 mil (99SE-SP6). It seems that since there are only 16 symbols defined for the drill drawing, once you have more than 16 different drill sizes the CAM Drill drawing lumps drill sizes together and assigns a hole size of 0 mil. Apparently the NC drill file does contain the correct information. It is a Knowledge Base Item (# 1472), however when something like this sneaks up on you it is very disconcerting, as I was assuming lots of possibilities from corrupted design files to invalid design rules. I guess I would have preferred some indication that a limit had been reached and the system was compensating, rather than just arbitrarily assigning several different holes to 0 mil. Just a reminder to any of you who might see something funny in your Drill Drawing regarding hole sizes... David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Too many hole sizes
Brad Velander wrote: David, thanks for the warning to everyone. Does assigning letter characters to your drill drawing assignments solve the problem? There should be a limit of 26 at least then. Have you tried this? The KB 1472 is so nice, they don't even suggest that letter characters might solve the problem so you are left to wonder. Is there a limit of 16 sizes even with the letter symbols? I tried using the letters and it works (at least for 18 different hole sizes). I do not have any idea of what would happen beyond 26 hole sizes, but I hope I never have to find out! I really do not like having so many different hole sizes, however, this board has a lot of devices each requiring its own special sized alignment hole with tolerances that do not allow grouping several sizes together. Why can't all the alignment pins be just one or two sizes? ;) David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Netlist Import take too long?
I am not positive this is the best way (or even a good way), but what I do is: Design/Netlist Manager/Menu/Clear All Nets just before I do a: Design/Load Nets Note there is a LONG pause before the Load Nets Window comes up (10-15 seconds) but much less than the 25+ I have seen waiting without clearing all nets. David W. Gulley Destiny Designs Michael Biggs wrote: Does anyone use a third party schematic capture program then import the netlist each time to Protel99SEsp6? Well I do and it works great always has. The problem I'm having is that some of the more sophisticated boards netlist take 10-15 minutes to load each time I need to import a new netlist due to schematic changes or pin swapping. Does anyone know of a fix for this or a way to accelerate the netlist import? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Shortened Designator on Silkscreen
What I have done is to unhide the Comment field and use it to label small components so the Ref Des is not changed and therefore corresponds with the schematic/netlist. Obviously everybody involved needs to understand and approve such a shortcut. I then show the Ref Des on the Assembly drawing where the IC is to be placed. On one design that had multiple identical channels, a box (Top Overlay and Bottom Overlay) was drawn around the identical sections and a Text Field added to the Box saying Channel N and then the individual components were just labeled (using the Comment) as you indicated using the shortened designator. Since all Rn in the channels were identical and there were no other Rns (i.e. make sure that if you have R1-1, R1-2, etc. there is no R1 in the non repeated section of the board) the assembly personnel had no difficulty stuffing the boards. On another design, I was asked to use Alpha characters for the indicators (again using comments) so I had sections that looked like alphabet soup! JaMi Smith wrote: I have a small problem with small parts in a small area on a small board (so what else is new?). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Shortened Designator on Silkscreen
Actually, this is a VERY good point, the Comment IS updated on a netlist load. I have used two methods: a) Set the Comment field in the schematic (assuming I have control) b) edit the macros generated by the netlist load to delete any changes to the comments (these are usually the last macros generated so they are easy to find) It really depends on how many revisions the design will be going through and making sure that ALL non standard design flows are carefully and fully documented within the project. I have not tried it with sync, but would assume that the comments are over written there as well. David W. Gulley Destiny Designs Dennis Saputelli wrote: WARNING after i sent this it occurred to me that the comment field may get trashed by a netlist load david can you confirm that this works? do you use the sync or netlist load? Dennis Saputelli * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
Abd ul-Rahman Lomax wrote: At 10:03 AM 3/25/2002 -0800, JaMi Smith wrote: Michael, If the little grey cells are functioning properly, they tell me that it was ANSI Y14.15 and Y32.2. As for the T, all of the companies that I have worked for wanted the connection dot regardless. In my view, the best practice is to avoid crossed connections *and* to use connection dots on the T connections. I also remember that there are a few exceptions to the 4 way connection rule, specifically where there were symmetrical circuits involved such as a dual power supply (positive and negative) where all the capacitors came together at ground in the middle. I disagree that this is best represented with a cross wire tied with a connection dot. It is quite simple to jog one or both connections, or to stagger the capacitor placements. The former takes a little less space. When I am trying to show a multi-signal connection to a point (e.g. single point ground) I usually go non orthogonal, that is I have the symmetrical signals come into the point from an angle (not a right angle). The single point is readily apparent, and there is no confusion over whether or not a tie point is present. I avoid X 4-way connections, as schematics in the past have gone through many photocopy cycles and a dot on a 4-way junction disappears into the noise and dots appear where there were none. Even though PDF distribution is more prevalent, most of my clients like to know that if the signals cross, there is NO connection (regardless of there seeming to be a dot present). David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] 4 character pad name limitation
Ian Wilson wrote: SNIP ... (like the 4 character pad name limitation) ... SNIP Ian Wilson I have not tried if for a while, but does this 4 character pad name limitation still exist in 99SE? (I remember having to rename ANODE and CATHODE to ANOD and CATH on some designs imported from OrCad a while back ...) David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Specific Keep out.
The simple answer to your question is yes, draw a trace on the layer, double click on the trace and then check the keepout box in the trace properties dialog box. The complex answer may receive some criticism; however, I like to take the simplistic approach to board design, either signals are the same or they are not. If the GND signal IS the same as the polygon, let them touch; If the GND signal IS NOT the same, then rename one of them! I prefer to have multiple GND signals (GND, AGND, GNDXYZ, ...) that connect at a common point (or as I otherwise may specify) rather than have a single GND running the gamut of the board that I then have to coax to behave as I desire. The program knows only what you tell it, not what you mean! David W. Gulley Destiny Designs Tim Fifield wrote: Is it possible to have a layer specific keep out? I want a GND trace connecting two components, however, there is a GND polygon between the two components as well. I do not want the trace to touch the polygon. Is there a way to do this without drawing the polygon around the track? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is it possible to create short circuit component (sch+pcb)
Juha Pajunen wrote: Is it possible to create a design without short circuit error (sch + pcb) where two different nets can be connected together? For example, I need to connect two different ground nets in one point of my PCB design and I do not want to use R0 resistor or jumpers, I need a wire that connect those nets. I have used the virutal-short method discussed many times on this list for most of the occasions where I am shorting two different nets; however, occasionally I like to place a trace that will give me the DRC error just so it is very apparant what is going on. (For me, it is not my goal on every project to have no DRC errors as much as it is to make sure any DRC errors are understood and intendeded.) I also create a document that I maintain with the files that provides any notes regarding that particular design. This text file is pretty much boilerplate information about the design, who it was for, what versions of tools were used to create the design, and I also include any special information that pertains to what I have done whether it is the addition of virtual shorts, traces or clearances to ignore on DRC or what combinations of layers to use for generation of the output data. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autorouter
Tim Fifield wrote: Just curious... Does anybody use the 99SE autorouter for large PCB designs? Do the majority of board designers do everything manually? I don't even bother with the autorouter anymore, it's to messy. Perhaps I'm not setting it up properly. What do you people do? I have used it for medium designs (3 560-pin BGAs, 4 100/144-pin QFPs, 30 or so smaller SM ICs and several hundred discrete R, C, L and XTAL, plus connectors, test points, etc.) I hand routed the speed critical and analog sections, set up many design rules (layers, clearances per IC, per via, etc.) and then turned the AR loose. Spent about 2 hours cleanup, but I feel like I had good results and it did the job MUCH faster than I could have done by hand. For large designs, I typically use Specctra. For small designs, I may hand route or throw the AR into it just to see how it does. Often I am surprised by how well it performs! Sometimes, I setup keepout lines (constraining the traces within specific regions) and turn the AR loose doing analog and speed critical signals as well as the rest of the board. I usually have a good bit to clean up (setting length, max parallel and length rules on signals and verifying they are within tolerance), but even then I find the AR did as well as or better than some layout shops had done on designs which were similar but using other tools. My advice is set up every rule you can find (even if the AR does not obey them) and then DRC/tweek until YOU are satisfied. If you think the cleanup will take too long either add some constraints (new rules or keepout guides), or do it by hand. Don't get me wrong, I complain about the AR because there are a LOT of quirks which I think Altium (nee Protel) should put serious effort into correcting; but for the price, it does a reasonable job. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB process engineers - PCB quoting
Jeff Adolphs wrote: Hello, How many of you out there talk with the PCB manufacturers Process Engineer to see how they will do the PCB Layer Stackup? A IPC lecturer recomends I always talk to the Process Engineer and should be doing extensive documentation on my PCB Fab Drawing. I always only talk with the Sales contact (if that). I don't feel I have time to go to the detail of contacting the Process Engineer to find out what Cores they stock, what Prepregs they stock, how they intend to do the PCB Layer Stackup, and then add this PCB Layer Stackup information to the Fab Drawing after the vendor is chosen. I usually quote 3 to 4 PCB Manufacturers using their PCB Quote on-line. I shop for best price because the PCB shops all seem to have the quality I need. I only order Prototypes. Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio, USA The key words here are the PCB shops all seem to have the quality I need. If this truly is the case, then you may be fine. However, my experience has demonstrated that many (local) shops say they have capabilities that are not demonstrated in the boards delivered. Years ago, I started learning what questions to ask and incorporating a board specification into the information provided both for the quote and actual fabrication. On boards with specific requirements (e.g. tight impedance control), I will specify both the requirements AND a recommended layer stackup. At the shops that I have found to be most reliable, once the job is submitted, the shop provides me with a contact name (other than the salesman), with whom I can discuss all the particulars and point out any areas that are critical. I use a variety of vendors depending on the specific requirements or quantities of the board. Unfortunately, I have come across shops that either can not meet the specs or just ignore them and by having the requirements clearly present, I do not have to eat any bad boards... David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [PROTEL EDA USERS]: Just a hole
Andrew Lowy Sybrandy wrote: I still have a one question: 1. Why is it important to change the X and Y size to zero before production. It was said this prevents flashing from within the Gerber file, but I don't know what that means. There are varying opinions here, but one reason is that tightening a screw on the pad surrounding a hole may abrade metal from the pad which can then cause shorts elsewhere in the system. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: Inner Power Plane clearances
I usually draw the board outline on Mech 1 and then select the board outline and copy to one of the power planes. I then select just the outline on the power layer and change the track width. I select the track width depending on the required clearance between the plane and the board edge. I then copy this outline to the other power plane layers. If I use a 50 mil track width, I get a 25 mil separation of the plane and the edge of the board. I usually draw the keepout layer along the edge of the track used on the power plane area so that my traces do not extend past the edge of the plane. David W. Gulley Destiny Designs Micky Blain wrote: 1. just go bit on a big order with power plane clearance. It seems that the gerbers generates the plane all the way to the edge of the keep out layers. Is there anyway to control the power plane and manually draw them in without doing them by split planes? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: Deleted Power Planes
Micky Blain wrote: I have deleted a power plane from my design. It seems that SP6 is not taking this off of the design. I think I remember this subject being discussed but I was swamped at the time and it was a few weeks back. Does anyone know how to get the plane off the design? Open the Layer Stack Manager (under Design) and delete the plane there. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: CAM Manager issue
Geoff Harland wrote: big snip That is not the only grumble that I have about the CAM Manager server, and it is not necessarily the biggest shortcoming associated with it. But what I have written in this post is something to be kept in mind in the event that the contents of one or more Mechanical layers are to be included within only *some* of the Gerber files produced. Which is why I copy the board outline to the inner planes, adjust the plane setback with the trace width, setup the CAM manager once, and the I am sure all of my Gerber files are created with a single button push. Even with RS274X Gerbers, my board fab shops typically want to see the aperture file. I do really desire the capability of setting up various combinations of which Mechanicals are included with which layers, creating a SINGLE aperture file, and creating ALL of the Gerbers with a single button push. (The Gerbers can still either be all RS274D or all RS274X as the user desires.) David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: ASSIGNING NETS TO A POWER PLANE
Bryan Bernesi wrote: I have 24 isolated -6V nets that I would like to pass on the power plane, and 24 isolated GND that i would like to pass on the GND plane. my question is, can I use the power plane as a regular internal plane? i.e. passing traces on the plane layers? I see two ways to go: 1) use a regular internal layer for the 24 isolated nets and then use fills and/or polygons for any required plane areas. 2) draw 24 split planes on a plane layer. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: Annular Ring
Interestingly, Although the design rules now show the correct diagram for annular ring (pad radius - hole radius) and the design rules interpret the rule correctly; however, the board report still shows annular rings calculated as pad diameter - hole diameter. (This is 99SE-SP5.) This is not a major problem, except a customer wanted to know why I was being so generous with the annular rings on the board when he saw the report! David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: node not found
Bryan Bernesi wrote: I am an ex-OrCad user who ran into the same problem in Protel. When transfering the netlist from SCH to PCB (using Update PCB); following the excellent notes that Colby shared with us, I came across an error that used to drive me nuts in OrCad. The pins on any diode (LED) found in the miscellaneous devices.lib are not the same as the pins found on the PCB footprint diode.(LED) due to different pin names/numbers. Now, I remember Mr.Lomax telling me that editing the components that came with Protel was a no-no, and to have multiple footprints for the same component is also a no-no. What can I do? Start with the Protel component and save the edited copy to another (YOUR OWN library). I NEVER reference the Protel libraries in my projects but may check their parts and then use/edit/build my own in my own set of libraries. I think Abd's point was to: a) not edit and return a part to the Protel library (since an upgrade may overwrite that updated part) b) not have multiple footprints of the same device referenced within a project (since it is not obvious which is the correct version). David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
[PEDA] [PROTEL EDA USERS]: Resizing Fills (was Suggestions forimproving Protel...)
Geoff Harland wrote: snip - (Pcb Server): Add support for *resizing* of a currently-focused fill primitive using the *mouse*. That is, if you click on an edge or corner of a currently-focused fill, then you can change the location of that (by dragging it with the mouse) (rather then repositioning the entire fill, without changing its overall width or height, which is the current behaviour). If you want to reposition the fill (current behaviour), then click on the *centre* of this (and then drag it). snip I wasted several minutes on my last project trying to grab the corner of a fill before I finally remembered to edit the size in the dialog box! This proposal sure makes sense to me. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * __ To post a message: mailto:[EMAIL PROTECTED] To unsubscribe or subscribe we recommend using the form at our web site: http://www.techservinc.com/protelusers/subscrib.html You may also unsubscribe directly by email: mailto:[EMAIL PROTECTED]?body=leave%20edaforum however this may fail if you're trying to unsubscribed an old email address, an alias mail account, or if your mail client uses an unusual encoding format. To contact the Forum Administrator: mailto:[EMAIL PROTECTED]
Re: [PEDA] auto-routing layers
Michael Reynolds wrote: Where is the layer setup in the DRC? Design = Rules = Routing Layers This enables routing on various layers and controls (in a limited way) the preferred direction of routing on specific layers. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
Abd ul-Rahman Lomax wrote: At 10:23 AM 3/14/01 +0100, [EMAIL PROTECTED] wrote: As chip designers tend to show ambition in specifying three and more power supplies for one chip, there is not much use in the hidden pin feature any more. The vast majority of integrated circuits in designs which cross my desk are single-supply, and the majority of designs have only two power nets: ground and one other. And as has been demonstrated so many times, one person's experience with designs is vastly different from an other's! A design I am currently working on has five digital power supplies (5.0, 3.3, 2.5 1.8 and 1.2) as well as two analog supplies. The design uses several SN74LVC14A Schmitt-trigger inverters for cleaning up some slow edges. Interestingly one SN74LVC14A provides 6 inverters, which is how many are required on the board; however, I need 2 at 3.3V, 3 at 2.5V and 1 at 1.8V. Using the hidden pins would be a killer, as would just allowing individual gates. So the three 14-pin packages are used in their entirety to insure that the next guy to just add an inverter has to decide which of the 3 packages he intends utilize. I do have designs where I use hidden pins, but (for me) they are getting rarer. As to the rest of Abd's message, I agree wholeheartedly: Further, it should be considered that there is a huge base of legacy designs which would be wrecked if Protel no longer supported hidden pins. *But* it would not be difficult to provide tools that would make the use of hidden pins less hazardous, or the elimination of hidden pins in a design easier. Yes! Yes! Except for the following: A warning that there are hidden power pins on a design would not be a bad idea. With this sentence, I totally disagree with Abd, I think, A warning that there are hidden power pins on a design *should* be REQUIRED! David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] MM's VS Mils
Jim Mcgrath wrote: Accurate conversion is the key. NOT that metric rules. But what do you do when you live in both worlds? I had a client with a somewhat funnel shaped board and he wanted the assembly drawing for one end dimensioned in mm and the other in mils. Note, as soon as you change measurement units, the values in the dimensions change accordingly! So just to compensate, I explode the dimension to free primitives. Hey Protel, why not allow the user to assign a measurement unit to each dimension. (and while you are at it provide BOTH mil and mm on the measure distance function to avoid the constant swap between the two...) David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Use Pad Stack
N-Luo/Yu-Ming ( INC) wrote: I try to use the pads on multilayer using pad stack. I set the top and middle layer pad to 0, and set the hole as a NPTH, But when I chech the gerber file, I noticed a round flash with 8mil diameter on the top solder mask layer. How to solve that? and subsequently wrote: I get it. I use the default sloder mask expansion setting 4 mil, To move the unwanted solder mask on the top solder mask layer, I should set the top pad to -8 mil but not 0 mil. You did not specify if you were actually going to drill the pad. It seems to me that you may be trying to define a bottom layer pad (since the multilayer and top are both 0) with drill size 0 (since you want top solder mask set to 0). If this is the case, change the layer of the pad in the properties tab to bottom, and the internal layer and top layer features are removed. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] MM's VS Mils
Jim Mcgrath wrote: I'm with you. I and most designers live in both worlds. We just need Protel to fix the conversion so we can toggle between worlds without introducing roundoff errors. Your process works for you to GET IT DONE just not easy. If I understand you, when you explode the things they are no longer text and can not be moved as such. Tools=Convert=Explode Dimensions to Free Primitives will convert a normal dimension line and associated text into individual elements, (multiple lines for the arrows and making the measurement into a text field). The text can be moved as a unit, but association with the arrows and dimension lines is lost. There are so many features I could imagine for dimensions, but they are probably not nearly as important as some of the other bu..oops features. (For example being able to grab the end of a dimension line and drag it to a new position and the dimension text is updated to the new length. Or then there are angular dimensions. And ...) David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Split plane modifications
Abd ul-Rahman Lomax wrote: SNIP If, however, that is too complex, allowing a midpoint pickup by clicking on a segment but not at a vertex, in which case the midpoint associated with that segment would jump to the cursor as a new pending vertex. This would allow two clicks per segment, one to select the direction of movement around the polygon and the second to place the new vertex. If, then, a new vertex in the same direction of rotation automatically popped to the cursor, we'd be back at one click per vertex. And now that I think of this, I think it better than having two modes as suggested in the last paragraph One selects the direction of motion by picking a segment to be the first new segment of the polygon, which defines the direction of rotation, and then one can continue placing segments until the command is terminated by escape or rt-click. Here, Here! This would be a GREAT addition to the tool. Too many times have I had to fiddle with the grid to get the midpoint selected when trying to add a vertex. David W. Gulley Destiny Designs * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
