Re: [PEDA] Net with large clearance and polygon
Cam, Firstly, what rule for polygon clearance of 12mil are you talking about? There is a rule under Manufacturing for Polygon Connect Style and also one for Power Plane Connect Style and also Power Plane Clearance, but not one for Polygon Clearance. You may be speaking of some specific Clearance Constraint that you have set up that you have named polygon clearance, but you will have to explain that one to me. I believe that the simple answer to your question would be to set the Polygon Connect Style rule under Manufacturing to Relief Connect, and then than set up an additional Clearance Constraint rule which applies to Scopes of Board, Board, and the Connectivity of Same Nets, with the clearance of 12 mils, and enable this Clearance Rule at the same time that you Pour your Polygon Planes with a Clearance Constraint rule enabled which applies to Scopes of Board, Board, and the Connectivity of Different Nets with the clearance set to 97 mils (i.e. enable both rules, but only these two rules, at the time of the Pour of the Polygon Plane). If that fails, read on. I am not quite sure that what you want can be done in P99SE with a specific rule that would be set up by class etc., that wouldn't apply to the whole net EARTH as a whole, or otherwise be complex enough to screw up. I encounter the problem all of the time, where I want my Polygon Planes to have a larger clearance or setback than my normal clearances, which sounds something like what you are trying to describe below. The trick is to remember that a Polygon Plane clearance is really pretty dumb, in that it is actually defined by the clearance rule (Clearance Constraint) in effect at the time of the actual Polygon Pour (i.e.: Each time you generate a Polygon or Re-Pour (Rebuild) it). I generally make a Design Rule for Clearance Constraint which I name Clearance PP (for Polygon Plane), with the Scopes of Board, Board, and the Connectivity of Different Nets, and the specific clearance that I want, which in your case would be 12 mils, but in my case it would be larger than the normal clearance for everything else. Normally, this rule would be off (no check in the Enabled box) for normal routing and board work, but then when I am ready to make my Polygon Planes, I disable (turn off) all of the other Clearance Constraint rules, and enable (turn on) only my Clearance - PP (Polygon Plane) rule, and than make or Pour my Polygon Planes. Again, please remember that every time that you Pour or Re-Pour (Build or Rebuild) a Polygon Plane, that it Pours at the Clearance Constraint in effect at that time, and that this means that if you have a Polygon Plane already set up, and you double-click on the Polygon Plane to open it's Dialogue Box for any reason, that if you click Yes to the question Rebuild 1 Polygons?, that you are liable to change the clearance of your Polygon Plane. If you really do have to Re-Pour the Polygon Plane, you will have to go into your Design Rules and enable and disable the appropriate rules, and then change them back again when you are done with all of your Pours. Needless to say, if you want to have different clearances for different Polygon Planes, such as for example for Polygon Planes on different layers, then the trick to accomplishing this is simply to Pour (or Re-Pour) them with different Clearance Constraints in effect at the time of each Pour (or Re-Pour). Sometimes you may even need different segments of a single Polygon Plane in different areas to have different clearances, such as for example an area around certain controlled impedance transmission lines which may need larger clearances. This can be easily done by actually making up your Polygon Plane with not a single Polygon Plane, but using several different but overlapping Polygon Planes of the same net name, and Re-Pouring the different segments with different Clearance Constraints in effect for each Pour. You may end up with a few little uglies here and there, where the planes overlap, but that's what an occasional little floating piece of track of the same net name (overlaid on the plane at that spot) is designed to be used for, to clean it up, aesthetically speaking. Yeah, I know it's a pain, but that's Protel. What else would you expect? While someone else may come up with some other way to accomplish what you want to do, for me this is a simple and effective way to accomplish the task that works reliably for me from board to board (design to design), without any repercussions or side effects, excepting the Re-Pour issue. Unfortunately, in this case, like so many other things in Protel, you simply have to manually override the system to get it to do what you want it to do, and every time that you have to do something like this, you have to take the chance that it will not be seen or understood by someone else down the line, which means that someone else could easily screw up the design, in this case simply by Rebuilding 1 polygons [sic] (I don't think that
Re: [PEDA] Video Board Recommendations ?
If my memory serves me correct, most of the gripes that I have seen here in the forum, and also from my own useage going back to P98, and additionally from a few comments from our glourious vendors own tech support people, has been: Stay away from ATI - ATI has caused the most problems! Of course I do not know if this still holds true for their current modle line, and whether or not it would still be true today. The most importand thing to remember is all that Protel Products, and I believe that this includes dxP04, all use only 2D for all of their graphics, including any 3D renderings, which are themselves actually only done in 2D, so that any of the sophicistated 3D junk or 3D video boards that are so highly prized in the gaming world, are actually worthless for Protel, and in fact may in fact cause problems in Protel, or at least I was told a while back by some of the big A's Technical Support people. They also told me that on some video cards it may be necessary to scale back some of the video acceleration so as to not cause problems with Protel. This was their advice for Protel 99 SE, and I am not quite sure that that would be applicable on DXP or what I call dxP04 (which I still have not installed). Respecting the dual output capability of a video card which you discuss below, I thought I had it on my nVidia Ge Force 4 FX5200 128Mb until I read Terry Cheers post and yours below. JaMi - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, August 25, 2004 10:03 AM Subject: Re: [PEDA] Video Board Recommendations ? For basic support, (neither cheasy nor caviar-based) with continually upgraded video driversets from the chipset mfg, I suggest an Nvidia-based MX440, 64M-128M memory, dual video out. I purchased my last one from EVGA, (www.evga.com), though the popularity, ease of use, performance, cost, etc. of the chipset, has made it easy to find from a variety of mfgs. Mine cost me $79 and has performed flawlessly, as did the last two. New driver packages are available for download from Nvidia on a regular basis (every month or so), because as we all know from using Protel, bugs are everywhere. Other chjipset mfgs will often be less than forthcoming with driversets. SO much so, in fact, that one of the most often cited competitors has lost theior once supreme status with the very customer base that launched them, ie, Apple customers, because the video mfg is sucvh a poor performer when it comes to supporting their products. Shiny on the outside, smelly on the inside. Make sure to verify that the card your purchase has dual video out or has a DVI as the secondary AND comes with a DVI-to-VGA converter included. Due to their overall performance, Nvida's unrivalled firm/soft support, and the entire line's low cost relative to their competitors, there are large numbers of Nvidia-based cards on the market, and many are single output devices, have a VGA and a DVI connector for dual, only have TV out for the secondary channel, or require the user to purchase a DVI converter... You can expect to pay somewhere between $80-$110 for a dual-output card of the ilk described above. Again, examine to ensure that the card does dual video, and if possible, has dual vga connections direct. A VGA and DVI combination is quite prevalent, but if you choose this route, then make sure you get a DVI/VGA adapter w/the card. aj -Original Message- From: Linden Doyle [mailto:[EMAIL PROTECTED] Sent: Wednesday, August 25, 2004 12:58 AM To: PEDA Subject: [PEDA] Video Board Recommendations ? Greetings all, I have heard that some brands of video cards can show problems when running Protel. Does anyone have any recommendations as to whose video boards work well and those I should steer clear of? I'm not after the latest and greatest video gamers mega-card just something that will reliably display Protel PCBs and Schematics preferably upgradable to a dual monitor setup (either a board with 2 outputs or the ability to operate with 2 seperate boards) Best Regards, Linden Doyle Product Development Engineer Zener Electric Pty Ltd. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mouse Driver
Mouse . . . Mouse . . . Did someone say Mouse . . . Steve, I've always had good luck with Logitech drivers (and eliminated almost all (99.999%) of my unexplained crashes), and personally like the feel of their Mice. Many of their newer Mice have many additional buttons, and the nice thing here, even though it doesn't say so on the outside of the package that they come in, all of the buttons are programmable. This means that you can take some of these additional buttons such as the ones mounted on the sides that are stated to be for things like Back and Forward on your internet browser, and reprogram them as PgUp and PgDn, which give you your zoom in and zoom out in Protel 99 SE (yeah, it is not quite like the AutoCad scroll in and scroll out, but it does work quite well none the less). Don't forget that most scroll wheel Mice also have a button built into the scroll wheel which you can also press as well as scroll, and sometimes you can re-define this middle button (scroll button) as either PgUp or PgDn all by itself (I know you can in Logitech Mouseware). Unfortunately, zooming in and out the way that you describe is usually a function of the application software itself, and unfortunately that specific function simply does not exist in Protel 99 SE , and since we never got enough support for SP7 . . . Although . . . Someone mentioned a utility that does something along those lines here in this forum not to long ago, so you might just check the archives . . . While a longshot, you might be able to find that some video card actually incorporates and supports such a function all on it's own simply as a part of the hardware . . . As a final note, such a capability would probably make for an interesting server for someone who likes to diddle around with the SDK and would appreciate the accolades of his (or her) fellow Protel 99 SE users (however it should zoom in or out in very fine steps, and not just emulate pressing PgUp or PgDn 57 times, and of course use my preferred method of centering with each zoom (don't anyone get too upset - that last part really was a joke (see :-) ) ) . . . Take it easy on all that Mousing around . . . Happy 99ing (still seems the best way to go . . . ) . . . JaMi - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, July 21, 2004 11:41 AM Subject: [PEDA] Mouse Driver At risk of reopening the mouse wars of yesteryear, I need to ask what's the best driver to install to use a Microsoft Intellipoint (Dell branded) mouse with Protel 99SE. I had a pretty decent setup and should have left well enough alone, but I tried to install a newer mouse with dual scroll wheels etc, and that didn't work out. I can't seem to get back to the configuration I had before using either the v4.1 driver I thought I was using nor the freshly downloaded (from microsoft.com) v5.0 drivers. What I'd really like, and what I thought I was getting when I bought the mouse, was the ability to use the scroll whele for zoom. With the way Protel zooms, that's all I need, and I'd never scroll at all. Just roll the wheel one way to zoom out till the area of interest is in view, move the mouse pointer over there, and roll the wheel the other way to zoom back in. Who needs scroll bars? Steve Hendrix * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel ASCII File Formar
Protellers, At least once in the past someone has sent me a copy (I believe it was a PDF) of the Protel ASCII File Format document that defines everything in the file format. Being as braindead as I am, I cannot find that copy anywhere. Can someone either please send me another copy or point me to one? Thanks muchly, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel ASCII File Formar
Well, it seems that I answered my own question. I went to the Protel Users Group on Yahoo! and found it under the files section there. It came up as a PDF file, and I went to save it in the directory that I logically thought it should go in, and it said I already had a copy there when I tried to save it. Duh ! ! ! That's the hard way to find where you stored something ! ! ! Well, I never said I was perfect, and at least I found the document that I was looking for. Thanks to any who may have replied or were about to reply. JaMi - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Wednesday, May 26, 2004 11:07 AM Subject: [PEDA] Protel ASCII File Formar Protellers, At least once in the past someone has sent me a copy (I believe it was a PDF) of the Protel ASCII File Format document that defines everything in the file format. Being as braindead as I am, I cannot find that copy anywhere. Can someone either please send me another copy or point me to one? Thanks muchly, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Flipping a PCB layout - 99SE
There is a way, and it works, but it is a slow and careful process.
You can even do the different layer vias, but you have to be real real careful and
have your wits about you so as not to either make duplicates of forget something.
I have a very long winded writeup that I started but never finished, and I could
possibly dig it up and finish it up if I can get some time here shortly.
For now I would recommend the archive.
JaMi
- Original Message -
From: Ian Wilson [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Monday, May 17, 2004 5:30 PM
Subject: Re: [PEDA] Flipping a PCB layout - 99SE
On 09:14 AM 18/05/2004, Nukien said:
I was able to do it simply in 99SE. Just select the entire board,
everything. Then click and hold something on the board, and hit x. It
will warn you that you are about to flip a component to the other side of
the board, and that you shouldn't do this ... Click yes to continue, and
there's your entire board, flipped.
Umm, probably better to do this to a copy ...
You are right you should do this to a copy as this will make an
unmanufacturable board - you will have to reverse the direction of pins ion
the components unless they are trivial unpolarised components. A simple 'x'
while moving a selection is not sufficient to make a manufacturable board -
there are a number of other steps that must be done.
There is a method to flip a design in P99SE. The main problem in P99SE is
the 'L' key layer flip does not preserve the correct relationship of
tracks, via and components. Components are flipped to the other layer in
place rather than about the desired location.
There is a method of flipping a design in P99SE. It is somewhat complex,
or more correctly it takes a number of steps. JaMi Smith was going to
write it up for us all as it is basically his method with a few corrections
thrown it. It seems to work correctly for the main entities. I think
there is a small issue with dimensions but I can' recall fully. It would
almost certainly not work on complex boards with blind and buried vias and
complex region based rules - at least not without significant work. You
may be able to figure out the method by looking back through the archive
for a thread labeled flipping board that started on 10/10/2002 and went
through to about12/10/2002 (in sensible dd/mm/ format :-). Be careful
and read fully there are corrections and mis-information throughout the thread.
As a general alternative to flipping a board there is a simple server
available that will allow you to see a flipped version of the board in a
floating window:
http://www.considered.com.au/Protel01.htm
Look for the CSFlipViewer server
(There are problems with my web host at the moment and has been for a few
days, definitely time to get a new host. Keep trying if you can't get
through initially.)
The flip server Geoff Harland and myself were working on is very unlikely
to be released as DXP and P2004 correctly do the layer flip ('L' key) on
selections that include components.
Ian Wilson
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Re: [PEDA] Flipping a PCB layout - 99SE
- Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, May 17, 2004 9:04 PM Subject: Re: [PEDA] Flipping a PCB layout - 99SE snip I get bored typing the same stuff over and over... I know what you mean ... Unless you are saying what they want to hear, they look right past it and never see it ... JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] CirCAD and 99 SE
Anyone out there familiar with a program named CirCAD, which is used (and I use the term lightly) for Low Budget Schematic Capture and PCB Layout? It can output a netlist in Protel/Tango Format, and save a PCB in Protel/AutoTrax format, both of which readily load into rotel 99 SE. I have not however had any luck in getting a schematic across. I have also gone backwards from Protel to CirCAD, but with some problems, but I am sure that some of these can be ironed out. Anyone got any experience and advice on such transfers? I may have occasion to do a few of these. Thanks, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Simulation Book Online
Thanks everyone for your input, I was able to go to the link below and eventually find it. When I get time I will investigate the other links such as the www.archive.org that was posted here below and also some of the links in the other replies. I was able to find http://www10.edacafe.com/book/SpiceHandBook/01_TOC.php which does appear to be the link that I was looking for, and although the individual chapters are in html format, and not PDF as I had thought, I think that my best option is to copy them all off to a mini CD, so that I do not loose them again, and that way I can go thru them as I have the time to study and do all of the exercises. Thanks again everyone for your help in finding these again for me, and also thanks to Clive for the original post. JaMi - Original Message - From: RogerHead [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, April 15, 2004 12:36 AM Subject: Re: [PEDA] Simulation Book Online I missed the original request, but you can find it at http://www.edacafe.com/ Just click on Books and Courses Roger At 10:33 AM 15-04-04, you wrote: Try this: http://web.archive.org/web/20030320113556/http://www.edatoolscafe.com/EDATools/EDAb ooks/SpiceHandBook/01_TOC.html Or cut and paste your old link into the web wayback machine here: http://www.archive.org/web/web.php The following was posted to the forum several months ago, and I flagged it, figuring that I would go back and look at it later. If I remember correctly, while the TOC was in HTML format, the chapters themselves possibly were in PDF format, and I had considered downloading them, but did not get arount to doing it. Well, as I should have anticipated, the link is no longer good, and I have nosed around the site to no avail. Did anyone download this stuff, or know where else it can be found? Thanks, JaMi - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, December 04, 2002 4:18 PM Subject: [PEDA] Simulation Book Online For anyone interested in Protels sim tools, here is a link to a book online: http://www.edatoolscafe.com/EDATools/EDAbooks/SpiceHandBook/01_TOC.html BR Clive * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Simulation Book Online
The following was posted to the forum several months ago, and I flagged it, figuring that I would go back and look at it later. If I remember correctly, while the TOC was in HTML format, the chapters themselves possibly were in PDF format, and I had considered downloading them, but did not get arount to doing it. Well, as I should have anticipated, the link is no longer good, and I have nosed around the site to no avail. Did anyone download this stuff, or know where else it can be found? Thanks, JaMi - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, December 04, 2002 4:18 PM Subject: [PEDA] Simulation Book Online For anyone interested in Protels sim tools, here is a link to a book online: http://www.edatoolscafe.com/EDATools/EDAbooks/SpiceHandBook/01_TOC.html BR Clive * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] The Protel 99SE router (router?)
- Original Message - From: Abd ulRahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, April 08, 2004 7:56 AM Subject: Re: [PEDA] The Protel 99SE router (router?) snip One of the 99SE router's poor features was weak cleanup. When dealing with off-grid pads, the router would route close to the pad on grid, then, sometimes, put in a whole series of meandering track segments in order to finally reach pad center. It would then leave this garbage. Somehow it could not recognise that the shortest distance from point A to point B was a straight line, even if that line was not orthagonal or semiorthagonal. This should not have been difficult to fix. But it apparently had to wait until Situs. ? ? ? I thought that this problem still existed in Situs, at least thru DXP PreSP3. Has it now been fixed? snip . . But in general, from the reports, it seems that Situs is a better router, already, and there is reason to expect that it will continue to improve. ? ? ? What reports? I Have not seen these reports and would like you to tell me where I could find them. Please give some specific references. Thank you, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Nanoboard
- Original Message - From: Rene Tschaggelar [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, April 02, 2004 1:21 AM Subject: Re: [PEDA] Nanoboard JaMi Smith wrote: Has anyone reverse engineered the Nanoboard yet? Where's the schematic? I had a look at it when I got 2004. The schematic appears to be there as well as the schematic for the daugtherboards. The nanoboard is an evalboard, as I see it. I haven't received anything yet, still checking the mailbox, but it is nice to know that that information has atleast been been made available. The whole development with cpu core and debugger has to run on a hardware of your own to be useable, doesn't it? As I understand it, that is the Nexar part of the equation (in conjunction with Nanoboard). It is kind of hard to figure everything out, and just what does what, and what goes with what, when you are only able to follow the postings in the forums, and haven't regeived anything yet. Maybe it will become much clearer if and when it all arrives. I appear to be on the very bottom of their mailing list, appropriate to my status as their favorite customer. Thanks, JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Nanoboard
John, I am not quite sure just what I am supposed to be getting here in the mail as an upgrade as nothing has arrived yet (but I have been assurred that it is in the mail), so I will have to look for those files when everything comes. But key to understanding how to use it to it's fullest is to understand what it is comprised of, so I am glad that all of that is availavle somewhere. Thanks much, JaMi - Original Message - From: John A. Ross [Design] [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, April 02, 2004 3:43 AM Subject: Re: [PEDA] Nanoboard Jami A printed version is at the rear of the Nanoboard tech manual The design is located in the P2004 examples sub directory C:\P2004\Examples\Reference Designs\NanoBoard-NB1 In my case its C:\2004\ so just change to wherever yours is. Best Regards John A. Ross RSD Communications ltd Email [EMAIL PROTECTED] WWWhttp://www.rsd.tv == -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED] Sent: Thursday, April 01, 2004 7:22 PM To: Protel EDA Forum Cc: JaMi Smith Subject: [PEDA] Nanoboard Has anyone reverse engineered the Nanoboard yet? Where's the schematic? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Nanoboard
Has anyone reverse engineered the Nanoboard yet? Where's the schematic? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Release Notes
Firstly let me apologize for not yet responding to a few unresolved issues that people have asked me about, but to which I have not had the time to answer. I will get back to those posts and answer them as soon as I can. On to the current issue. I have been puzzled by the DXP Service Pack 3 (aka DXP 2004 (aka Protel 2004)) Release Notes ever since they have been posted on the Protel Website at: === http://www.protel.com/2004releasenotes.pdf It seems that much is being made about the supposed fact that there are so many New Features in Service Pack 3 that Altium is justified in calling it a New Product, as opposed to just the long awaited and long overdue Release of Service Pack 3. As evidence of all of these New Features, one is pointed to, among other things, this Release Notes PDF list of things that have been fixed or resolved since the Release of Service Pack 2. The problem that I have with looking at this list, is that it uses DXP Service Pack 2 as a reference, or baseline, and thus the list looks quite impressive, at least until you realize that many, if not most, of these issues have actually been fixed or resolved by the first DXP Pre-Release Service Pack 3, and the second DXP Pre-Release Service Pack 2 (Build 104). Is there any way to tell just what 'issues have been fixed or resolved by the two Pre-Releases of Service Pack 3, as opposed to what has been fixed or resolved since those two Pre-Releases have been issued. In reality, I do not believe that when the two Pre-Releases are taken into account, and subtracted from the list, that you will have anywhere near 16 pages of fixed and resolved issues. When you look at what is left, is there really enough there to warrant calling the final release of Service Pack 3 a New Product? It is not my intent here to discuss the differences between a Service Pack and an Upgrade to a New Product (which even some Protel employees agree is vastly different), which would be an appropriate topic or subject for another discussion, but rather the real question that I am posing here is just what parts of this list in the Release Notes has been previously resolved by the two Pre-Releases of Service Pack 3. Does anyone out there know the answer to this question, or how we can go about finding it? Respectfully submitted, JaMi Smith * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2004 DXP Looks Great,
that that might be what was holding up the final release of Service Pack 3, and to now here that Completion is a New Feature is beyond comprehension. Haven't they done anything else to improve Situs? I guess the final blow, the final humility, is that after I purchased DXP under ATS 2 years ago, and after Altium promised to do away with ATS, and since I have patiently waited for these 2 years for them to deliver a functional DXP Product to me, they have now relegated me to a second class citizen, since I did not renew my ATS this last year when it expired, since I was out of work, and couldn't afford it, and I now have to listen to Nick as he graciously extends me a free Upgrade to the New Product, but at the same time tells me that I am not entitled to a printed manual, since after all, I am only a second class citizen and second class customer. BS! Absolute BS! Nick, Altium - You are not giving me anything! I Purchased DXP 2 years ago on your promise to deliver a fully functional and fully operational DXP Product, and I am entitled to a fully functional and fully operational DXP Product! You have been living off of my purchase of DXP for the last 2 years, and not just my purchase alone, but the purchases of hundreds if not thousands of others just like me that have purchased DXP either thru ATS or directly, on your promise to fix the damn thing. I am in fact very very pleased that it finally appears that you may actually have finally fixed most of the shortcomings of DXP, and that I may in fact finally receive a functional and operational DXP Product in my mail box here in the next few days, but please please please stop treating me as if I am a second class citizen and a second class customer. You are not giving me anything! I have paid for a fully functional and fully operational DXP Product, and I expect to get it! Altium, please also let me remind you of the fact that Phil Loughhead has made it perfectly clear in a series of posts in the DXP Forum, that the name change from DXP to Protel 2004 was strictly for clarification to clear up the ambiguity over calling both the Design Explorer Platform and also the Schematic and PCB portions of the product, by the name DXP, and that Protel 2004 is in fact still DXP, and not a new or different Product. So Please stop trying to tell me that Protel 2004 is a new Product, and that you are graciously going to give me a free upgrade to it. And yes, thank you, I would appreciate a new Printed Copy of the New Manual, just as I believe all of your Customers who have paid for the DXP Product would, even those who you have relegated to second-class status. Sorry to go off like this, but I am tired of being treated like I, and all of the other DXP Customers who have been waiting for so long, and even have been intentionally ignored for the last 6 months, are not entitled to what we paid for, and not entitled to a Printed Manual. And yes Altium, I would gladly accept your apology for treating your loyal customers this way. And please Abd, getting back to you, you are really not qualified to speak out on this issue, so please don't. Respectfully submitted, JaMi Smith - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Monday, March 08, 2004 9:20 PM Subject: Re: [PEDA] 2004 DXP Looks Great, [sigh...] At 09:34 PM 3/8/2004, JaMi Smith wrote: This is kind of what I was trying to address in the DXP Forum with a post there, before Nick stepped in and totally side-stepped the issue by telling me to go read a link. Pesky fellow, he, distracting us from our monomanias. People keep calling Protel 2004 an Upgrade. Yes. With the exception of the Nano-Board stuff, it occurs to me that this is not a real Upgrade in anything but name only, and that in respect to DXP Schematic and DXP PCB that this is really nothing more than the long long overdue Realease of Service Pack 3. There is an SP3 in Beta. My understanding is that Protel 2004 includes a lot more than SP3. There is enough improvement in 2004 that the term Upgrade is earned. A major service pack is often tantamount to an upgrade. 99SE was an upgrade more than a simple service pack, which might be confined to bug fixes only. This seems to be somewhat comparable to the Upgrade from Protel 99 Service Pack 2 to Protel 99 SE, which if I understand it correctly, was actually also called Service Pack 3. Yes. But it was really an upgrade. Protel sometimes includes operational enhancements in service packs, and bug fixes in upgrades. The latter is more unusual, because by the time service packs are no longer issued for a product, *most* of the bugs have been fixed, the true bugs. The problem here is that while I understand that the step from Protel 99 to Protel 99 SE actually was in fact a really big step, what we appear to have here is simply some additional functionality, which you must
Re: [PEDA] 2004 DXP Looks Great,
- Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 2:45 AM Subject: Re: [PEDA] 2004 DXP Looks Great, On 08:17 PM 10/03/2004, JaMi Smith said: ..snip.. BS! Absolute BS! Nick, Altium - You are not giving me anything! Ladies and Gentlemen, This is the only person that I know that has been tossed off an Altium forum. Some may say this is due to a conspiracy. I suspect it is due to simple rudeness. Make your point by all means but I suspect you will be better served with a degree of civility. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2004 DXP Looks Great,
- Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 2:45 AM Subject: Re: [PEDA] 2004 DXP Looks Great, On 08:17 PM 10/03/2004, JaMi Smith said: ..snip.. BS! Absolute BS! Nick, Altium - You are not giving me anything! Ladies and Gentlemen, This is the only person that I know that has been tossed off an Altium forum. Some may say this is due to a conspiracy. I suspect it is due to simple rudeness. Make your point by all means but I suspect you will be better served with a degree of civility. Actually Ian, you know better than that, because I have personally told you the whole story directly offline from any of the Forums, and you have personally directly verified it with your friends at Altium. I will ignore the fact that you appear to be baiting me here, in view of these two facts. The real charge against me, if you will, was that I instigated and lead the Revolt against ATS, and embarrassed Altium by asking questions both here in the PEDA Forum and in the original Yahoo! DXP Forum that they couldn't answer, with the result being that they kicked me out of that Forum at the same time that they issued their humble public apology to their Protel and ATS Customers and supposedly canceled ATS back in September of 2002. You also forgot to mention that they have since reinstated me, which you are also well aware of. But that's really a topic for the Protel OT Forum, and not this one, so I won't continue that conversation here. If anyone wants to continue with this specific issue, let's please do it there (I am a member of that Forum too), or contact me directly. Back on topic of the new DXP THICK manual. I am, and have been, simply trying to make the case that all of Altium's loyal DXP Customers should qualify to receive a new printed THICK manual, as Mike stated that he had received in the initial Post to this subject. Since there are many here in this Forum that have not additionally been monitoring the DXP Technical Forum, and therefore may not know the whole story, I am additionally trying to clarify the fact that Altium themselves originally stated that Protel 2004 is NOT a New Product, and that DXP is still DXP. Yes I understand that Altium has additionally released a new product, Nexar, and that it is compatible with the Protel 2004 Design Explorer, but Nexar is not DXP. Altium has clearly stated it the DXP Forum that the name change was simply to clarify the relationship of the different parts of the DXP Product, since they had inadvertently originally applied the name DXP to both the Design Explorer Platform, and the Schematic / PCB portions of the DXP Product, which had been a departure from their previous practice, and that this had caused much confusion, and that they were just changing the name to clear up the confusion and go back to the previous practice of applying the product name of Protel 2004 to the overall product and retain the name of DXP as it relates only to the Schematic and PCB portions of the product. Additionally, they have stated that they want to be able to place additional products, such as Nexar, under the umbrella of the Protel 2004 name. This is what Altium has said as recently as a few months ago, and since Protel 2004 was NOT going to be a New Product, I repeat, NOT going to be a New Product, and since DXP was still going to be DXP, there should be no Upgrade involved, but rather simply a formal release of the initial 2 pre-releases of Service Pack 3, with some additional corrections, and possibly a few more of the issues that have been brought up in the DXP Forums (both Technical and Pre-Release) resolved and implemented. In other words, aside from the fact that the Design Explorer Platform has been modified to support things such as Nexar, Altium themselves have made it clear that DXP is still DXP, and that all DXP Customers would be receiving the finalized release of Service Pack 3, in spite of the fact of the name change. This is why I have referred to Protel 2004 as DXP with the finalized release of Service Pack 3, and this is in strict accord with what Altium themselves have stated in the DXP Technical Forum. The problem, and the confusion, arises only out of the fact that Altium seems to have now at the last minute decided to change their mind regarding the DXP Product still being the DXP Product, here within the last month or so. Altium now appears to want to present Protel 2004 as an entirely New Product, as opposed to just a long overdue finalization of a regular Service Pack for DXP that was intentionally withheld for over 6 months. If in fact Protel 2004 is truly a New Product, then receiving it truly would be an Upgrade. But in fact, it has only been in the last month or two that Altium seems to have come up with this New Product and Upgrade idea. It is a nice Marketing idea, and more obviously possibly even an attempt to distance themselves from
Re: [PEDA] 2004 DXP Looks Great,
- Original Message - From: Brooks,Bill [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 11:08 AM Subject: Re: [PEDA] 2004 DXP Looks Great, Just an additional clarification Mike, The book from the DXP class is nice. It's about 300 pages of what should have shipped with the product. The class was 2 days and about 1400 bucks if I remember correctly. My instructor was Matt Berggren and he's a really great guy. The others in the class came from all walks... and each one came away with something because Matt tried to address their specific needs. I think it was worth the trip . . . Trip? what trip, aren't you located there in Vista there just about 20 minuites away from Altium North Amarica over there in South Escondido? Respecting Top Gun, mentioned by Mike in a parallel post, I didn't know that you participated. Was that at PCB West? What did you use, Protel 99 SE, DXP, Protel 2004, or Mentor Expedition (which I know you can also drive)? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2004 DXP Looks Great,
Tony, Actually no, that is what happens when you double click the Reply button in MS Outlook Express, instead of just a single click. My apologies. I have actually replied now. Sorry for the blank post. JaMi - Original Message - From: Tony Karavidas [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 11:21 AM Subject: Re: [PEDA] 2004 DXP Looks Great, What, you're speechless? ;) . . . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Quit Complaining!!! ( 2004 DXP Looks Great)
Melvin, I am not sure if you have been monitoring the various DXP Forums, or not, so I am not sure if you actually have the whole story. I actually bought DXP on ATS, which was really a promise by Altium to deliver a functional Protel 99 SE replacement. Altuim has consistently and continually promised all of its DXP Customers every step of the way that they would fix DXP, regardless of when and under what circumstances they bought DXP. This drama has unfolded in the various DXP Forums over the past 2 years, and only within the last 2 months has there been any indication that Altium is now apparently trying to step away from all of those promises. For example, if you have not been monitoring the DXP Forums, you may not be aware that the DXP Situs Autorouter has never been able to route even a moderate design to completion. Virtually everyone acknowledges this, and DXP Customers that needed to use an Autorouter had to export the Design back to Protel 99 SE to get it done. Altium has repeatedly promised to fix the Situs Autorouter, and up until just a few months ago was promising that it was undergoing an entire overhaul. This is why loyal Altium Customers who have purchased DXP have been hanging on for up to a year and a half (two years in my case) waiting for Altium to fulfil those promises, are now a little upset when it appears that Altium may now be trying to sneak out of the commitment and promises that they made to those customers Respecting your assertion that the DXP Product could have been returned for a full refund, I am afraid that it is not as simple as that, either ethically, morally, or legally. DXP is not a simple Word Processor or Accounting program that you can purchase for a couple of hundred bucks, learn within a week or two, and then return for a refund when you find that it doesn't do what it says it will. DXP is an expensive program with a list price of $8,000 US. But notwithstanding the initial price tag, virtually everyone that has bought it has spent at least that much in addition to the purchase price, in terms of time and energy invested in training, to learn how to use DXP, even to get up to the point that they could realistically make the decision that it was unusable at the point that it was initially delivered. Simply returning the product at that point in time would not have paid for the losses incurred in learning DXP, and would not in and of itself been a realistic option for too many of those DXP Customers (and I will not digress into what would have been realistic options along this line, but I am sure that many can guess (and I wouldn't be surprised to find out that it may actually have happened in some cases)). There is additionally the problem of being locked into DXP from a design perspective. By the time that many DXP Customers came to the conclusion that DXP could not perform as expected, many had created several, if not numerous designs in DXP, and could not replace DXP without having to re-create all of those designs with yet another product. This is compounded yet further for those who may have used DXP to create designs not only for themselves, but additionally for their own customers, which designs they still need to be able to support and update yet into the future. Simply returning the DXP Product for a refund does not even begin to scratch the surface of the expenses involved and the amount of direct revenues that would be lost by DXP Customers in this scenario. Once again this too does not appear to be a realistic option unless one is willing to try and additionally recover those additional losses (again, I will not digress into that option here). In other words, realistically it is impossible to return it and be able to get a FULL refund, as you call it, once you have actually begun really using DXP. As an interesting side note to this discussion of the above two issues, I am willing to bet that if someone were able to come up with a reliable low cost (or no cost) design translator, so as to be able to reliably directly translate a current design from DXP directly into say Mentor Expedition, or Mentor PADs, that you would see a whole lot of people with their box in their hands lining up to get their money back for DXP, losses on training notwithstanding. Respecting your final alternative, of going back to Protel 99 SE. This is just exactly what many, if not most DXP Customers have actually done. Notice how many have said that they put it back in the box to wait until DXP got fixed? But there are a couple of problems here, even with this option, and the primary one is the fact that Protel 99 SE still has many problems and even a few bugs of its own, and Altium has refused to solve any of those problems, which is why many of those people have turned to DXP in the first place. But did you notice that even those that put DXP back in the box to wait for it to get fixed, and who temporarily went back to Protel 99 SE, did not ask Altium for a
Re: [PEDA] 2004 DXP Looks Great,
- Original Message - From: Brooks,Bill [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 2:58 PM Subject: Re: [PEDA] 2004 DXP Looks Great, I was using P99SE. It was a challenge. Also knowing what I know now, I would have approached the design differently and might have placed higher in the rankings. But be that as it may, it was a good run for the money and I was in very good company at the time too. It was back in March of 2000 at PCB West in Santa Clara. Heheh.. you crack me up... ! I know you drive much farther than I do Bro... You live out in the toolies... That's why you drive that Jeep isn't it? No it wasn't a long trip for me... Maybe 40 min. They held the classes down in Mira Mesa in the old training center for one of those ITT Tech schools of some sort. I wish it had been at Altium HQ that would have been even closer for me. Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 Trip? what trip, aren't you located there in Vista there just about 20 minuites away from Altium North Amarica over there in South Escondido? Respecting Top Gun, mentioned by Mike in a parallel post, I didn't know that you participated. Was that at PCB West? What did you use, Protel 99 SE, DXP, Protel 2004, or Mentor Expedition (which I know you can also drive)? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2004 DXP Looks Great,
Arrrgh! Whats with me this double clicking the Reply button and shooting blanks today? Anyway, Bill, I didn't realize that your Top Gun participation was back in 2000. Based on Mikes comments I thought it was at the current 2004 PCB West (or is it not quite time for that yet). Toolies . . . What toolies? Pasadena (as in Rose Parade, Rose Bowl, and an occasional Super Bowl and World Cup) isn't out in the toolies, even if I do drive about 140 miles one way to attend your IPC Designers Council Meetins down there in San Diego. But on the other hand, I mean South Escondido is still South Escondido, isn't it? Just because they are a few feet across the San Diego County Line and want make it sound a little more upscale by calling it Rancho Bernardo . . . : ) Respecting my Jeep . . . alas, my poor Jeep . . . it died two and a half weeks ago on Friday when a brand spanking new never even been sold yet 2004 Ford F250 4 Door Crew Cab Diesel Truck with a $43,000.00 Sticker Price Sheet still in the window turned left right in front of me in the rain, right out in front of Galpin Ford in the San Fernando Valley, and I T-Boned it with my poor little Jeep Cherokee, on the way back from picking up some PC Boards, a few blocks away from the Board House. Fortunately my new Boards that I had just picked up were not damaged, but this last Friday the other guys insurance adjuster (another Ford Dealer (he was doing what they call a dealer exchange)) told me that I need a new Jeep, and I can kiss this one goodbye (although as of yet they haven't yet told me how much they are going to give me for my poor little baby). I was however able to pick up my four little letters, J, e, e, and p, from all of the rubble that was in the street after the accident, so at least I can keep those . . . maybe even glue them up here on the top of my Monitor . . . Anyway, back to issues at hand. You mention that you got a big manual with your Altium Training Class, and stated that It's about 300 pages of what should have shipped with the product. Was that specifically a Training Manual, just for the class, or is it possible that that is the same as the THICK manual that Mike is talking about in the initial post to this thread? JaMi - Original Message - From: Brooks,Bill [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 2:58 PM Subject: Re: [PEDA] 2004 DXP Looks Great, I was using P99SE. It was a challenge. Also knowing what I know now, I would have approached the design differently and might have placed higher in the rankings. But be that as it may, it was a good run for the money and I was in very good company at the time too. It was back in March of 2000 at PCB West in Santa Clara. Heheh.. you crack me up... ! I know you drive much farther than I do Bro... You live out in the toolies... That's why you drive that Jeep isn't it? No it wasn't a long trip for me... Maybe 40 min. They held the classes down in Mira Mesa in the old training center for one of those ITT Tech schools of some sort. I wish it had been at Altium HQ that would have been even closer for me. Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 Trip? what trip, aren't you located there in Vista there just about 20 minuites away from Altium North Amarica over there in South Escondido? Respecting Top Gun, mentioned by Mike in a parallel post, I didn't know that you participated. Was that at PCB West? What did you use, Protel 99 SE, DXP, Protel 2004, or Mentor Expedition (which I know you can also drive)? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2004 DXP Looks Great,
This is kind of what I was trying to address in the DXP Forum with a post there, before Nick stepped in and totally side-stepped the issue by telling me to go read a link. People keep calling Protel 2004 an Upgrade. With the exception of the Nano-Board stuff, it occurs to me that this is not a real Upgrade in anything but name only, and that in respect to DXP Schematic and DXP PCB that this is really nothing more than the long long overdue Realease of Service Pack 3. This seems to be somewhat comparable to the Upgrade from Protel 99 Service Pack 2 to Protel 99 SE, which if I understand it correctly, was actually also called Service Pack 3. The problem here is that while I understand that the step from Protel 99 to Protel 99 SE actually was in fact a really big step, what we appear to have here is simply some additional functionality, which you must pay for if you want, and which is clearly additional to the basic DXP Package, but that with respect to the basic Schematic and PCB Packaging part of DXP, we are only getting a Service Pack, and one that really doesen't look like it really may have addressed all of the problems in the DXP Only part of the package, based on what I am seeing here in the forums. Respecting the issue of too many trees for Manuals, When I got my initial Release of DXP, I got a manual that was just over 3/8 thick that was an absolute joke (I am once again restraining myself to keep it clean here in the forum), that was totally worthless, and very soon actually obsolete. I can accept the fact that Altium did not want to print any manuals while they were trying to get their collective DXP act together, but if they think that that time has come, and they have actually decided to go ahead and print a THICK manual as Mike called it, then I do believe that Altium owes one of these manuals to all of it's DXP customers, since it never delivered a useable manual in the first place, and have been begging off giving one to every DXP Licensee with various excuses over the last year and a half now. Altium - If you have actually have printed a manual, then distribute it to the people that you have been stalling for the last year and a half, irrespective of the number of trees that it takes. Respectively submitted, JaMi Smith - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, March 08, 2004 1:43 PM Subject: Re: [PEDA] 2004 DXP Looks Great, On 03:03 AM 9/03/2004, Tony Karavidas said: I'm guessing they it's either a new purchase or he is paying maintenance. Tony This was made quite clear by Nick on the DXP list, wasn't it Tony. Full licenses get manuals, the upgrade issued to DXP license holders don't. At least this is what Nick Martin wrote: The free upgrade packages won't include the Printed Books (too many trees!!) but all the doco is available on the CD. This seems clear enough to me. So Mike, was yours an free upgrade from DXP or a new P2004 license? Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Semiconducto rmfg Footprint creation
Tony, Ian, Dennis, Leo, and the Forum, Actually, I can not find the original post to this thread, so I will simply assume that what is said that Tony wrote below is what was originally posted. Actually, there is a brand spanking new Spec (Standard) that will be released at APEX in Anahiem California at the end of this month, that will deal exactly with the problem of Standard Libraries and the associated problems such as zero degrees of rotation for a Component Footprint (in the Libraries). The Spec is IPC 7351, and there is a related spec which covers a Neutral CAD Database Format for interchanging information contained in these Libraries between different EDA/CAD Vendors, and that is IPC 2581. A supposedly complete Library already exists for PAD's which can be downloaded for free from www.pcblibraries.com , which supposedly already conforms to the relevant specs. There are actually some current specs that already cover some of the issues related to zero degrees of rotation as it relates to a Pick and Place Machine. (yes, this again, just what I have been asking for here in the forums for the last few years). Some of these current industry standards can be found at JEDEC JEP95 for most IC Packages, although about half of the packages in the proposed IPC 7351 Standard Library by PCBLibraries.com have rotations that are inconsistant with the current JEDEC JEP95 Design Requirements and Standard Procedures and Practices (SPP's) portions of JEP95 (Section 4). In addition to the JEDEC JEP95 Standard (which is primarily concerned with Registered and Standard Device Outline Drawings), there is a specific Standard which defines how not only IC's, but additionally resistors, capacitors, and other devices, are to be packaged in Tape and Reel for Pick and Place machines. This spec is EIA-481, and it has been around since the early 90's, and is currently entitled ANSI/EIA-481-C 10/03. There are in fact some contradictions here also between EIA-481with what PCBLibraries.com has done so far, but effective this morning IPC is looking into these disgrepencies, and they will be resolved before any Standard Library is actually adopted by IPC. The whole point here is that there will actually be an international standard that is going to be released very shortly here that will in fact address this very issue, and other related issues including the database problem, and everyone, even including Altium, will be expected to conform to the standard within a few years. The ultimate Goal for the IPC Standards would be acceptance not only within the PCB Design community but also within the Component Manufacturing community, such that ultimately even Schematic Symbols would be standardized, and all components would directly map to a specific Industry Standard Schematic Symbol and a Specific Industry Standard Component Footprint, all freely available from the Component Manufacturer in a Neutral CAD Database Format, and that these Standard Libraries would drive all of the Manufacturing Processes, such as Assembly and Testing. Maybe Altium will be developing some new Library Component Wizards after all, once the details of the new IPC 7351 and IPC 2581 specs are actually finalized. JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, February 08, 2004 3:29 PM Subject: Re: [PEDA] Semiconducto rmfg Footprint creation On 11:15 AM 7/02/2004, Tony Karavidas said: What does the lack of an industry wide standard for component footprints have to do with Altium? They are but one EDA vendor and there are certainly orders of magnitude more component manufacturers than EDA vendors. The problems and unfriendliness are prevalent and unique to each EDA vendor's tool set. Having an interoperable library standard cannot be done in a vacuum, and I don't think Altium can take the lead. They would need to form a consortium of EDA vendors and I think they don't want to play ball together. (It would be nice if the top 4 or 5 could join to develop this XML or whatever based standard.) I also don't think a parts vendor could/would do it. What's in it for them? Why should they throw the resources at it? They will sell their parts regardless...if people need those parts for a certain functionality. If you're thinking yeah that may be true for single sourced parts, but what about multi sources parts? then I would say those are nearly commodity items anyway and there's no money in time spent making industry standard libraries for them. It probably needs to be some organization like the IEEE. Or users - there is nothing to say that a bunch of committed and competent users couldn't form the consortium and start the definition process. What would be required is users using all sorts of different CAE programs getting together to start the process. There would potentially be copyright issues with someone taking the Altium libs and converting them to a
[PEDA] Test - Is the PEDA Forum operational?
I have not received any posts for several days now, and I am wondering if Forum Traffic is just down, of if we have hit another operational snag . . . JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [dxp] Control Thermal Reliefs by Area
Abd and Hamid Ok, Protel 99 SE, I had a little trouble following all of that at first, but actually got in there and started playing around with the scope of the rule for Power Plane Connect Style, and while I too had never before investigateed the full list allowed by the slider, right there at the bottom is what I am looking for, which is Region, and while it takes a little bit of work to set it up, that is just what I was looking for. This also appears to possibly be the answer to the No Connect situation I inquired about in a parallel post, since I can set up special rule for no-connect, although the one thing that I was looking for there in the scope, was the ability to apply the rule directly to a single via, which appears to be the one thing that is not in the list, although I guess that I could make a seperate via-specification that had a very very slightly different sized pad, and place it where I wanted the my no-connect via. It would have been nice to be able to just select a single via, as it appears that you can do with pads. Back to the Area question, the Region seems to be the answer. Footprint won't work with a BGA, since most vias related to a BGA are actually free vias, which are part of the fanout, and not the Footprint. Now the only question is can I do this in DXP? Thanks, JaMi - Original Message - From: Abd ulRahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 8:25 PM Subject: Re: [PEDA] [dxp] Control Thermal Reliefs by Area At 10:26 PM 1/7/2004, Hamid A. Wasti wrote: Abd ul-Rahman Lomax wrote: In 99SE, this would be controlled by a Design Rule, and the choices for scope are Board, Footprint, Component/Class, Net/Class, Pad Class and Specification. I'm a little surprised not to see via there Look harder. It is there and always has been. It is located just below Pad Specification duh. as is the rest, i.e., Via Specification, Footprint-Pad, and Region. I overlooked the slider Now, in DXP, it seems to be a little more complicated. I looked and could not come up with a way to do it, so I gave up after wasting an hour. So much for the claim by the Protel sales person that if you are an experienced user of 99SE, there is absolutely no learning curve to be just as productive in DXP. I'd say that was puffery. A learning curve is involved only if you chose to take advantage of additional powerful features. Would you call that a blatant lie, an ignoramus telling the truth as he knew it, or in our politically correct world a poor victim of capitalist society merely taking liberties with the truth in order to earn enough commission to feed his family? I'd say somewhere between the second and the last, it can be hard to tell the difference (though I don't know if Protel salespeople get commissions). It is not entirely false, i.e., much of the basic functionality is the same, but enough functions have changed in some way to cause delay as one figures out how to do it in DXP. How much impact this has on productivity, I can't personally say, because I haven't pushed a job through DXP yet. But it will have an impact in the short term, I have no doubt. In real life, I'd ask the question on the DXP list, not here, if I wanted to get the fastest and best answers. What I was specifically trying to do in DXP was to have all vias connect to the planes without thermal reliefs. Well, I defined a via specification scope direct-connect rule in 99SE (unchecking all the specifications so that it applied to all vias), then I imported the board to DXP. I did get a rule with the same name, but the scope did not mention vias... just All. And I don't see via or pad scopes in DXP Power Plane Connection Style rules. What am I missing? (In 99SE, to reiterate, one may, for example, give free pads a PadName and then use Free-PadName in the scope, allowing one to control connection style and other characteristics like Solder Mask Expansion, pad-by-pad simply by editing the pad name. Or one could have one size of via that is, say, tented, and one size that is not.) The DXP way, as I understand it, would be to create a Query that selects the objects to be affected by the rule. I can create a Query that selects Vias with the Build Query command, but I don't see how to connect this with the Rule, the Query Builder button in the Rule window does pop up a query dialog, but the required options (Via, for example) are not there There has got to be a way. If I were trying to get a job out, having managed to get it designed in DXP and now I'm just trying to finish the details, I'd be fairly upset! (And, as I said, I'd ask on the DXP list. But my own motive here is to explore a bit what it is like to move to DXP as an old hand with 99SE, to find the rough edges.) And I'm not thrilled that the rule from the 99SE file did not survive import. (But maybe it did and I'm just
Re: [PEDA] [dxp] Controll Connection to Plane by Area
Rob, InRegionRelative and InRegionAbsolute, as well as inVia, appear to be on the road to what I need, but I could not find anyhting like that that deals with Region when I was playing around with the Query Helper last night. It appears that these are part of a much larger Query Language that I need to learn. Is this stuff specifically documented somewhere? Thanks, JaMi - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, January 08, 2004 6:29 AM Subject: Re: [PEDA] [dxp] Controll Connection to Plane by Area Sure, there are a few ways to do this. You have to make a rule for the plane connect style, then use the query helper to specify the via. Specifying the via is where the different ways to do this come in. I would specify the NET or NETCLASS and IsVia, and InRegionrelative, or inRegionAbsolute depending on where I had the origin for the board (look in the archives for the difference), but you could also make a room for that area and then use TouchesRoom. There is also a function to select if it is within the space of a component, but I can't remember the name of it and don't have time to look. You could also tell it to apply the rule if the via is not in a net class so that it only apply to nets that were not in the power class, but that is assuming you don't have it directly connected to a power net, and are using the NetTie component attribute to attach it to the power net. So yes it is very easy to do unlike P99SE where about the only easy way to do it was to convert the via to a free pad then make a rule to specify that pad. Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [dxp] Controll Connection to Plane by Area
- Original Message - From: Abd ulRahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, January 08, 2004 7:23 AM Subject: Re: [PEDA] [dxp] Controll Connection to Plane by Area . . . These are all more complex than simply setting a rule for all vias to be direct-connect. But it is exactly this which we can't seem to find. I can set up a query with Build Query, but I don't see how to point the Connection Style rule to the query. Nor do I find this in documentation anywhere, which doesn't prove it is absent! That one I can do. PCB Rules and Constraints Plane Power Plane Connect Style Plane Connect Panel, and then select All in the Where the First object Matches dialogue, and then a Connect Style of Direct Connect in the Constraints dialogue. But like you, I can not find any Documentation. I now am looking for some specific information on the keywords used in the Query Language, as well as an overview of the Query Language itself, and I can't seem to find them. I have posted to both Forums on these issues (here and DXP), and I am learning from both. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] [dxp] Controll Connection to Plane by Area
Is there a way to control the connection to Planes, or specifically forbid them, by defining a physical area on the Board? Is there any other method? I am thinking of a circumstance such as a BGA where I may have 1 or more connections which are control inputs to the BGA, and that as such they need to be tied either High (VCC) or Low (GND), but which I do not want to connect directly to the Plane in the middle of the Board, since I may want to cut them loose from that specific connection during testing or at some other time. Is there any other way to do this, short of routing the connection out to a jumper pattern outside of the BGA? Another common area where I might want to do this is with a component where I have to put the Decoupling Capacitor(s) on the back side of the board, and I do not want the specific via that goes thru the Board to the Power Pin to connect to the Plane in the middle of the Board (i.e.: I want to decouple the Pin and not the Plane.) JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel PCB fornat
I got a layout of the ASCII Format once from Abd Lomax, but I have it archived somewhere and cant find it at the moment. It may be one of the files on his Yahoo! site. Let me know if you need me to dig deeper and find my copy. JaMi - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 11:07 AM Subject: [PEDA] Protel PCB fornat Hello All Does anyone know a source or information for the format of Protel 99SE ASCII PCB files. I intend to modify ASCII files but would like to know the real format. Thanks in advance Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [dxp] Controll Connection to Plane by Area
John, Short on the backside of the board -This is something I have done in the past by placing full arcs on the specific Plane Layer, to prevent connection, and then by running a small trace to another point that is connected to the Plane in question. This works quite well, although it is very time consuming, and is next to impossible to see once it has been done, and no way to identify in the design to the next guy who works on the project. I was hoping there was another faster or simpler way. JaMi - Original Message - From: John M. Cardone [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, January 07, 2004 2:56 PM Subject: Re: [PEDA] [dxp] Controll Connection to Plane by Area A virtual short on the back side of the pwb (this would require breaking up pwr and gnd nets) or, Define a split plane inclosing the pins you dont want connected which would be associated to a phony net JaMi Smith wrote: Is there a way to control the connection to Planes, or specifically forbid them, by defining a physical area on the Board? Is there any other method? I am thinking of a circumstance such as a BGA where I may have 1 or more connections which are control inputs to the BGA, and that as such they need to be tied either High (VCC) or Low (GND), but which I do not want to connect directly to the Plane in the middle of the Board, since I may want to cut them loose from that specific connection during testing or at some other time. Is there any other way to do this, short of routing the connection out to a jumper pattern outside of the BGA? Another common area where I might want to do this is with a component where I have to put the Decoupling Capacitor(s) on the back side of the board, and I do not want the specific via that goes thru the Board to the Power Pin to connect to the Plane in the middle of the Board (i.e.: I want to decouple the Pin and not the Plane.) JaMi -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP
Ian, I just knew that you could not speak to the issue. You have only confirmed what was fairly obvious before, that you really are on the Protel / Altium side of the fence. You contribute greatly to the forum when there are small problems to be solved, but you are nowhere to be found when an issue with your buddies at Protel / Altium rears its ugly head, such as the current one where DXP licensees and users are being totally abandoned for at least the next several months, if not permanently. You have no real answer to the topic of discussion here, and the only thing that you can try and do is save face by personally attacking me. Ignoring me does not fix the problem, or address the issue. Many DXP licensees and users need real hard information on what is happening with DXP right now, so that they can plot their course of action for the next few months, and maybe even the next few years. These people have nothing to do with me, other than the fact that they are fellow licensees and fellow users. Ian, don't penalize them by withholding the inside information you have regarding DXP, and it's demise. Yes, we all know that they will be given a new product, Protel 2004, but you actually know now just how different that product is from the current DXP model, and you actually know not only how different, but you also have a real good idea of the transition that all of these licensees and users are facing, in order to stay in business and keep their jobs, whilw still following the Protel / Altium product line, and you choose not only keep your mouth shut on the issues, but you complain about my mannerisms and put up a smoke screen instead. Ian, this has nothing to do with me. I am not going to let you hide behind personal issues. For the third time now, I will directly ask you not to respond to me, but rather to respond to the issues. Don't play childish games, and say you are not going to read any emails posted by me, because that will not excuse you from being fair and honest with all of the other DXP licensees and users in this forum. And last but not least, just because you cannot handle the truth, please don't call it bile. Sure I'm upset with Protel / Altium, and what they are trying to pull off on the DXP licensees and users. You should be upset with them too - but no, your only upset with JaMi for speaking out on the issue. Don't answer me. You need to answer the DXP licensees and users in this forum. JaMi * * * * * * * * * * - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, November 23, 2003 2:09 AM Subject: Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP On 09:21 PM 21/11/2003, JaMi Smith said: Ian, Please see below. No - I've wasted too much time on your ranting over the years. Trying to be polite and give you the benefit of the doubt. Plink - that is the sound of the JaMi filter being engaged. I am not reading your bile now, better things to do. Maybe I will relax the filter in the months ahead or maybe not. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Happy Thanksgiving
Happy Thanksgiving to all that observe it. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP
of their existing designs to another EDA product (yes, that is legally possible under California law which covers the DXP(nV) License, but again please not let us digress or argue this issue (at least at this point) as it takes us away from what is really going on here). So what's the Bottom Line here? I think that current DXP(nV) Licensees need to really stop and ask what Protel / Altium is really saying here, and what it means to their own productivity, and whether or not it is wise to continue down the Protel / Altium yellow brick road to the land of Oz, the land of promised future productivity. I think that it is time once again for us to request, no, demand, some real answers from Protel / Altium as to what is really happening and going on here. I would say at this juncture that what we all need to do on an individual basis is to evaluate just what the real hidden meaning of this announcement is, and decide whether or not we should proceede for yet another day to put more time and money, in the form of designs and training, into this bottomless money pit called DXP(nV), which which it appears is being dropped by Protel / Altium themselves.. The bottom line is that I think that at this point in time Protel / Altium needs to give us some real reasons not to simply pack it in and dump them as a provider of EDA Software. Please see below for further comments: JaMi * * * * * * * * * * - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Thursday, November 20, 2003 9:02 AM Subject: Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP At 02:56 AM 11/20/2003, JaMi Smith wrote: Maybe I just need to get a good nights sleep before I try and read this thing again. Maybe you should follow that practice every time you think that Altium is a collection of idiots and you are tempted to fly off the handle as you did. For the record, I do not think that Altium is a collection of idiots (well maybe for an occasional moment two), but rather I think that Protel / Altium sometimes appears to think that its licensees and users are the idiots, based on some of the things that they have done in the past, and some of the things that they have tried to pull off (there is a difference between being stupid and acting stupidly, since the one can't be helped). I will however admit to the fact that sometimes I do in fact believe that Altium is a collection of people who occasionally exhibit gross incompetence in certain areas. Whether or not I am flying off the handle will be born out by future history, but please let us not digress into my manner of stating the problem (which I know can sometimes be rather direct, if not offensive), but can we please just stick to dealing with the problem of discussing the announcement and its meanings, both stated and implied, and how this is going to affect the licensees and users. [...] Seriously, I am not just writing this to provoke an answer from Ian or Abd or Tony, and in fact I beg you guys not to take this off topic and run it all downhill into the gutter as has been done in the past. It's already there. Please, again, can we not digress into this, but rather really deal with the issue of the announcement itself. We who are DXP Licensees have spent a very very long time waiting for Protel / Altium to fix the major problems in DXP [...] only now to find out that they have apparently not been busy trying to fix the problems with DXP, but coming up with something new for which they will ask us for more money. For those who did not get a copy, please read the original announcement below. I'll quote the relevant parts below. No ! ! ! Please do not just quote the relevant parts, but rather please go back and read the whole announcement, and please be sure to look between the lines at what it is really saying, and what it really means. The one that really really really has me fuming is the statement Updates and enhancements that were under development as part of Service Pack 3 for nVisage and Protel will not be released for the DXP versions, but have now been integrated into the nVisage 2004 and Protel 2004 releases. Protel / Altium - I don't think that you really know what you are getting yourself in for, and you might want to rethink your whole approach about selling your customer base a non functional system, and then turning around and saying that you are not going to fix it. They did not say that. However, I'll admit that on the *second* reading, I became confused and thought that they *had* said that Protel 2004 was not going to be free to ordinary DXP users. That was a misreading. See: Because of our belief that every engineer should have access to the opportunities that this new technology offers, all current DXP version users will receive the 2004 software update automatically, free of charge when
Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP
Ian, Please see below. JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, November 20, 2003 1:49 AM Subject: Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP On 06:56 PM 20/11/2003, JaMi Smith said: What the #$%@ is going on now ? ? ? When has anyone been as rude to you as you are to others? Is it a special skill you have or something you practice hard at. Actually Ian, I am not always rude to others, and you know that, and neither are you, but even you have been extremely rude on occasion. I do not always flame on others, and you know that, and neither do you, but you have especially done so on occasion. I do not always dump on others, and you know that, and neither do you, but even you have done so on occasion. As even you have personally demonstrated here in this forum and others in the past, there are occasions when it is both proper and necessary to be rude, or to flame, or to dump, on someone or something, and I believe that this is one of them. In this case, I dumped on Protel / Altium, specifically because of what I perceive to be going on here with regards to them abandoning DXP Licensees and Users. Plain and simple. I am not being personally rude or slandering your good buddy (or would that be good mate down under) for what he wrote, nor am I holding him personally accountable for the actions that Protel / Altium as a Corporation seem to be taking, since those actions are not personally attributable to him, but I nonetheless do believe that the Corporation is in fact screwing over the DXP Licensees and Users. Again, plain and simple. I am on one hand rather surprised that you have been very very quiet respecting what is going on here, but on the other hand, you have obviously had full knowledge of what was going on here for a long time thru your good buddy and other contacts at Protel / Altium, which has put you in a rather unique position, and I can respect that you have to keep your mouth shut as far as criticism is concerned so that you don't jeopardize those friendships and relationships. But just because you have to keep your mouth shut, it doesn't mean that I or others have to keep our mouths shut, respecting Protel / Altium raking us over the coals. I find it very very interesting and very very telling that you cannot say anything else about this whole situation other than complain about my manner of responding to this situation. Your good buddies at Protel / Altium are screwing us, and you have absolutely nothing to say except that you consider me to be rude. Well, I tell you something, since this is a open discussion group that consists of men and women of all different sensitivities, I have tried to keep it fairly clean, but I think you can read thru the lines what I really think of some turncoat smuck like you who is a member of this forum, but yet keeps his mouth shut about what is happening to your fellow users. Seems to me that we have been here in the past, haven't we, where you have kept your mouth shut about certain things simply to let them play out to the detrament of others in the forum? But I guess that you no longer really consider yourself a user any more, since you have graduated to an insider. You have been very very quiet in all of the forums lately, and I guess we now all know why. Why don't you make your point without the slander and bigotry? Ian Wilson I don't believe that I have used slander or bigotry, and I actually think you got the whole point very precisely, but that you couldn't respond to it in any other way, other than make an issue out of my manner of presenting the problem. Didn't I specifically ask you not to respond to me but rather respond to the issue. But you cannot respond to the issue, can you. The politest thing that I can think to call you in this circumstance is a smuck, and I don't mean it in a bigotrous sense either, I am just trying to keep it clean and respect the sensitivities of others in this forum, while at the same time let everyone else know just exactly where your allegiances really lye . Ian, please don't attack me or my mannerisms, simply because you cannot speak to the issue. I've got a great idea Ian, why don't you really come to the aid of the DXP Licensees and Users and all of the other people in this forum, and come clean with what you really know about everything that is going on with Protel / Altium in this current issue? JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Exciting news for all users of Protel DXP and nVisage DXP
What the #$%@ is going on now ? ? ? Can anyone out there understand any of this, or is this just more Protel / Altium Jabberwake. On one hand it looks like they are trying to make a case for making a new product out of something that they were supposed to give us as part of DXP and nVisage to begin with, and on the other hand it seems that they are going to end up trying to charge us money to even fix (oops, they will never fix it - so I guess that the more correct word would be finish) DXP SP3.5 (build 18550372). Maybe I just need to get a good nights sleep before I try and read this thing again. On the other hand, maybe we just need to nuke Australia - well maybe not the whole Country, but at least Protel / Altium. I think it may once again be time to wake the sleeping giant of customer / user opinion, but this time, unlike before when Altium supposedly abandoned ATS (only to re-clothe it as so clearly shown below), maybe we need to do it in a much more coordinated manner, that guarentees the outcome in writing. And what the #$%@ is Protel 2004. Could this possibly be Service Pack 7 ? ? ? What is with these guys. Is there something about all of the blood pooling in their brains as they stand upside down on the bottom of the world, or what ? ? ? Protel 99 SE is still incomplete, and needs some patches ! ! ! DXP / nVisage has been lost in la la land for months and months and months, and still can't route a board to completion ! ! ! Does anyone else out there besides me think that it is about time that Protel / Altium needs to come up with some real good answers. Maybe it is just about time to call a lawyer or two, and get a good class action lawsuit going here for SP7, SP8, SP9 and the Source Code for 99SE, and not only a full refund for DXP, but also some very very large punitive damages to cover the purchase of and retraining on some other EDA Software as a real solution to our EDA problems and woes. Needless to say, this is posted here, and not in the DXP Technical Forum, so I don't get banned once again for speaking the truth and seeking honest answers to honest questions. Seriously, I am not just writing this to provoke an answer from Ian or Abd or Tony, and in fact I beg you guys not to take this off topic and run it all downhill into the gutter as has been done in the past. We who are DXP Licensees have spent a very very long time waiting for Protel / Altium to fix the major problems in DXP, and have had no response to many many questions regarding the status of DXP, only now to find out that they have apparently not been busy trying to fix the problems with DXP, but coming up with something new for which they will ask us for more money. For those who did not get a copy, please read the original announcement below. The one that really really really has me fuming is the statement Updates and enhancements that were under development as part of Service Pack 3 for nVisage and Protel will not be released for the DXP versions, but have now been integrated into the nVisage 2004 and Protel 2004 releases. Protel / Altium - I don't think that you really know what you are getting yourself in for, and you might want to rethink your whole approach about selling your customer base a non functional system, and then turning around and saying that you are not going to fix it. JaMi Smith @ @ @ @ @ @ @ @ @ @ - Original Message - From: Phil Loughhead [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, November 19, 2003 9:36 PM Subject: Exciting news for all users of Protel DXP and nVisage DXP Dear JaMi We would like to notify you about a recent Altium announcement and take some time to explain the impact of this on the current DXP product range, in particular Protel and nVisage. This week, Altium announced the release of a new Altium product called Nexar (see http://www.altium.com/corp/media/mr_nexar.htm/). Nexar will deliver a new approach to digital design, allowing you to implement a processor-based digital system in an FPGA using board design methodologies. It will include a mixed schematic/HDL design capture environment, IP cores, embedded development tools, and a reconfigurable hardware development platform called a NanoBoard. These features combine to create a highly interactive design and debug environment, allowing the engineer to interact directly with a design implemented in the FPGA. For more information on Nexar, please go to http://www.altium.com/nexar/. More importantly for you, Nexar will pioneer a new approach to electronics development - something that we are calling LiveDesign. LiveDesign capabilities, which are incorporated into the DXP platform, support real-time communication between the engineer and the design. This will have broad implications for all Altium products - how they work, and more importantly, how they work together to provide a complete, integrated electronics design system. Significantly, the entire Altium product line will move
Re: [PEDA] Open source SP7
- Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, October 15, 2003 12:12 PM Subject: Re: [PEDA] Open source SP7 ~ ~ ~ . . . Too bad the U.S. Dept of Justice didn't impose an effective remedy on Microsoft, that is, to publish all of their APIs and formats. But that is another topic... Ivan, I thought all of that stuff (or at least most of it) was available from the Microsoft Developers Network. and to be more specific, from their Visual Studio, and particularly from the individual SDK's for the different products. I know it took me years to track down, since I never had the extra bucks laying around to pop for the subscription to MDN, or for the Visual Studio (as I think it is now called), but I have run across some pretty arcane stuff from Microsoft, among which was a copy of the Win32 API, which I actually believe that I still have somewhere, but just exactly where, is unknown and a mystery at this current time. ~ ~ ~ . . . I still have my printed manuals from Quattro Pro 3.0, Borland C/C++ 3.0, MS-DOS 5.0, WordPerfect 5.1, etc. Did Microsoft ever give me any manuals for Word? Nope. I actually have some manuals for Microsoft Word (Actually Office, but they include one one or two for Word) kicking around here somewhere, but I dont know what version, but they are of the same vintage as the other goodies that you mention. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Open source SP7
Abd, Sorry I haven't had the time yet to respond to your last dump, although I am still planning on it (and much of it will have to be offline since it is unfit for any of the forums), and responding to this post is not the place to do it, so please stick to the issue at hand here. Please see below. JaMi - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Thursday, October 16, 2003 3:39 PM Subject: Re: [PEDA] Open source SP7 Mr. Smith's proposal is of sufficiently questionable legality that it would be a fairly hazardous undertaking. It might indeed be legal -- too many details are unknown to me to have a clear opinion -- but if Altium felt threatened by it, who is going to pay the legal expenses to defend against a suit? What the hell are you talking about? Aren't you the guy that has said that it is legitimate for an employee to take his employers Protel 99 SE CD ROM home and install it on his own personal machine (or make a copy for himself), and then do whatever he wants to with Protel 99 SE at home? That is of known illegality, and absolutely unquestionably unethical. Yet there is absolutely nothing at all even questionable about writing your own servers utilizing the Protel 99 SE SDK, and either selling them or giving them away free of charge to other legitimate owners of Protel 99 SE. That is a 100% completely legitimate and ethical course of action. Where are all of the real problems with Protel 99 SE? Some of them, like KLUNK, are obviously in Design Explorer itself. However I would maintain that many of the others are actually in the servers and processes used by those servers, all of which could easily be replaced with new servers and processes. I am not that up to speed on the Protel 99 SE SDK, but I do believe that all of this is not only doable, but doable ' in a totally legitimate manner. Perhaps some of those in the list that are more familiar with the Protel 99 SE SDK and the intimate workings of Design Explorer, its servers, and their processes, can comment on this. The only thing in my entire previous post that would be of any questionable legitimacy, would be the unspoken but possibly preceived implication that any Trial Version of Protel 99 SE that was given away for free, could be patched or cracked to work longer that 30 days. Respecting the giving away of the Trial Version of Protel 99 SE: Since it was originally freely given away to absolutely anyone in the world who wanted it, particularly in the freely downloadable version, I am not so sure that there would be anything that anyone could do to prevent any further additional free distribution of it, even if they wanted to. Is it my fault that there are actually other legitimate ways that you can still use the Trial Version for more than 30 days? Besides, most of the people in this forum already legitimately have their own copy of the full up Protel 99 SE (unless of course they have already taken your previous advice, and are using a copy of their employers Protel 99 SE). The Association, which has never raised a dime, might nevertheless be able to manage to support something in the user's interests, but my own opinion is that the Association, if it is going to do something serious, is better advised to work *with* Altium than to advance in what might be or might be perceived to be a hostile fashion. The Association is YOU ! ! ! Are you trying to say that you would be willing to be the repository of the fruits of everybody else's efforts and labors? Aren't you already making enough money on your resales of Protel 99 SE? Always after that something for nothing . . . If we want an SP7, we could organize and show sufficient interest -- and cash commitment -- that a real SP7 could be produced, not just a cramped version dependent upon the limitations of what can be done with the SDK. What's with this we? You got a mouse in your pocket? Fixing the remaining bugs in 99SE could involve some serious programming. Who is going to do it for free? If there is someone, great. Balderdash! Absolute Balderdash! (I am trying to keep it clean). It would take some simple programming by a good programmer who was familiar with the source code. The remaining bugs have already been so well defined, I doubt that they would take very much time at all to find and fix. In fact, I wouldn't be a bit surprised if thay haven't already been resolved, and just not implemented and released for either political or strategic (sales) reasons. I would be willing to bet that at least some of the remaining bugs could be fixed by nothing more than a fresh compile with an updated compiler. It's important to keep in mind the Protel support model. Protel's policy was (1) free service packs and (2) upgrades for a price. It goes with this policy that service packs are only issued for a limited time. After that, the Protel model
[PEDA] [PrU] Wierd Sience
I have not received any posts from PEDA for the last couple of days, so I begin to wonder what is going on with the listserver . . . I go and look at the Techservinc Archive, and it appears to have also stopped a few days ago too . . . Ok, me thinks, is it broken, or is it me . . . So I go to the Yahoo! Groups list, and the parallel archive that is (was?) kept there . . . Last post there, October 19th . . . Today's date . . . Ok, so I haven't received anything newer than October 17th from PEDA, and the date says the last post was today's date October 19th . . . Ok, so let's look at the Subject line and try to make sense out of what is going on here, and what has been missed . . . Wait a minute, none of this looks very familiar . . . Lets look at the overall number of posts here, and see if any of this makes sense . . . No, none of this makes sense . . . Ok, lets go back to the latest post, and go over it with a fine toothed comb . . . Wait a minute, that's not right . . . Today's date October 19th is correct . . . But it is not Saturday, it is Sunday, at least in my neck of the woods . . . Ok, not just the day of the week is wrong, but so is the year . . . The year says 2002 . . . Not 2003, but 2002, one year ago today . . . Now that's wierd . . . Not just wierd, but truly bizarre . . . JaMi Yahoo! Groups Sponsor To Post a message, send it to: [EMAIL PROTECTED] To Unsubscribe, send a blank message to: [EMAIL PROTECTED] Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] TEST
TEST * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Test
Are we back yet? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Non-Concurrent Licence Use (WAS Open source SP7)
Frank, The position you describe below is exactly (almost verbatum) the position that I was taking in a previous post (Subject Thread = License Legalities, beginning 9/4/03), where Mr. Lomax was trying to take yet a different position, and I was here chiding him for what I preceived to be a difference in his position, and where he now actually appears to be trying to say that my position is less than legal or less than ethical. I invite you to go back in the archive and read the other posts, where he seems to think that licensing has nothing to do with it, but that it all boils down to a matter of copyright law, which he believes is bogus anyway, and which to him means that it is alright in his eyes for an employee to make a copy of his employers Protel CD ROM that may be stored in the desk that he is assigned to sit at, whether he asks his employer or not. This was not a question of what the employer as the owner of the license has a right to do (which includes allowing the employee install it on his home computer if the employer so choses (I also originally pointed out the one person operating it at a time limitation of the license in the previous posts)), but a question of what the employee had the right to do without even asking his employer. I have not actually had the time ro respond to the last round in the previous thread, and that is why I was asking him to stay on topic here. JaMi - Original Message - From: Frank Gilley [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, October 21, 2003 7:39 AM Subject: Re: [PEDA] Non-Concurrent Licence Use (WAS Open source SP7) At 03:18 PM 10/17/2003 -0700, JaMi Smith wrote: (Referring to Mr Lomax) What the hell are you talking about? Aren't you the guy that has said that it is legitimate for an employee to take his employers Protel 99 SE CD ROM home and install it on his own personal machine (or make a copy for himself), and then do whatever he wants to with Protel 99 SE at home? That is of known illegality, and absolutely unquestionably unethical. I just want to point out Jami, that Protel has told me more than once that it is FINE with them to install Protel on more than one machine as long as only one copy is in use at a time. This includes taking a company copy home to install on your home computer and use at night, as long as the licence is only in use at one place at a time. I don't believe that their policy on this has changed. I can't imagine how this could be unethical. Another company, AWR's Microwave Office also supports this. In fact, since their software is locked to the MAC address of your NIC, they will actually issue you a free second home licence as they call it for your non-concurrent use on your home computer at night and weekends. -Frank Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Open source SP7
Ok, Mike, I'll stick my foot in my mouth . . . As if I haven't already done enough of that . . . Actually, I think that it is a lot easier than anyone may think. Most people on this list own a functioning copy of Protel 99 SE. Protel 99 SE runs faster on a slow computer than Protel DXP runs on even a fast machine. Enter the SDK. Lots of people have a copy of the SDK, and I happen to know for a fact that not all legitimately obtained SDK'e were obtained at the point of a non-disclosure agreement, or even at the point of an EULA. : ) So we use the Design Explorer shell from Protel 99 SE, and maybe even the core of Protel 99 SE SP6 PCB, and plug in a couple dozen servers that fix or replace all of the known problems (we can start with a pack of say seven (7) servers). : ) Worst we might have to do is make a few patches and/or intercepts in some of the the original executables. We might even be able to find a few legitimate Trial Versions of Protel 99 SE out there that we can legitimately redistribute in their original form for free, etc., etc., etc.. Yeah, I know some of you are worrying about slowing everything down by hanging all these new servers and patches on it, but once you put this thing on a really fast new machine, like the kind that you need to even make Protel DXP even limp along, then the thing should still fly. It could even possibly out-perform Protel DXP. If they won't give us our Service Pack 7, then maybe it is time that we develop our own Server Pack 7. : ) They don't actually even hold all of the cards that they may think they hold. There is more than one way to respond to a non responsive EDA vendor. : ) Altium, your last chance to give us Service Pack 7 for Protel 99 SE is fast approaching. : ) Whats it gonna be: SP7 or SP7? : ) - Original Message - From: Mike Reagan [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, October 15, 2003 2:33 PM Subject: Re: [PEDA] Open source SP7 I thinks Jon is right we need the source code to start -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] Sent: Wednesday, October 15, 2003 3:26 PM To: Protel EDA Forum Subject: Re: [PEDA] Open source SP7 hell, i'd buy a closed source one! ds Mike Reagan wrote: Hello All, I was contemplating what my next move with Protel will be and came up with an idea of creating an open sourced SP7 software for 99SE. Before I put my foot in my mouth, is there a future for open sourced Service Packs? is it legal? Mike Reagan EDSI -- Dennis Saputelli = send only plain text please! - no HTML == * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How to change drawing order?
Ian, I think I understand it now. Thanks. JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, October 14, 2003 2:53 PM Subject: Re: [PEDA] How to change drawing order? On 06:21 AM 15/10/2003, JaMi Smith said: I know that at some time on my OC system, I appeared to have lost the ability to alter the color of the Connections (if I ever had that ability), and I even seem to have lost that ability on my home installation too, although I do not remember having ever hit the Default Button on this system. Ian, You are probably the best one to explain this all, and also clarify why I would need to do something with the data you have provided below, and how I can tell whether or not I need to do anything at all. Whew - all a bit long I had to scan quickly to the question; I did as I thought there may be some confusion over this. When you click on the Default button on the Drawing Order screen the system writes the new order into the ini file (see the stuff I wrote before). The problem is that it does not write correct information for the new mech layers (newly introduced in P99 or was it P99SE). Pressing the Default button causes loss of the new mech layers until you manually twiddle the ini file. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How to change drawing order?
Ian and the group, Ok, I have waited for the dust to settle on this one before asking what may appear to some to be a simple question, but before I do, I need to explain a few things. First, I am color blind. Not totally, as some might think, since I can see and distinguish most, if not all colors, but the type of color blindness that I have has to do more with shade distinction, and distinguishing certain colors from one another. The standard question that I get is how do you know what color the traffic light is?, and that is not the problem, since I can tell that red is red, and green is green, and yellow is yellow, etc., quite nicely. The problem that I have is telling certain shades of green from certain shades of brown, which sometimes I cannot distinguish very well at all, especially in low light conditions. I also have a problem with some other combinations of colors when there is not too much contrast in the colors, such a yellow lines or letters on a white background. Anyway, with that as a background, I have always preferred the Protel 98 Classic color scheme, as opposed to the Delivered (I am avoiding the use of the word Default here (even though that is what Protel calls it)) Protel 99 SE color scheme. I remember back in July of 01 when I first started at Optical Crossing and they bought me a brand new seat of P99SE which I installed on a brand new Dell 4100, after I installed the new copy of Protel, I changed the colors to suit my tastes (Tools Preferences Colors Classic Colors, plus a few other changes). Some time after this (and after the mouse wars with Protel NA), but before joining this forum, I began playing around with the layer drawing order, under Tools Preferences Display, and at some point in time I did in fact Hit the Default Button under that Dialogue, and yes, strange things did happen. Ok, now we are up to date with 2 exceptions. 1. The Super Wazoo 19 inch Dell Monitor I had at work there at OC used to have a brilliant white background that hurt my eyes, especially at high resolution where it had limited scan rates available which were not too compatible with the bright fluorescent lights in the large room that I had to share with many other people before we moved and I got my own large office with appropriate filters and grilles on the lights. As a result, I had to avoid white, and select several contrasting colors so that I could see and distinguish with my color visual limitations. 2. When I bought my own copy of Protel 99 SE / DXP, and installed it here at home where adjustable incandescent lighting and an IBM 19 inch Monitor, I never seemed to have the problems that I had with the Monitor at work, and low and behold, I just checked and found that after a year and a half, I still have the basic Delivered color scheme on my system here (not the Classic Colors). Ok, so that brings us up to the present. With all of that said, I have read all of the posts to this thread very carefully, and I am still lost as to the meaning of the following: Do NOT press this button in 99 SE !!! I believe that here we are speaking about the Default Button under the Layer Drawing Order Button on the Display Tab, and not the Default Color Button on the Colors Tab (at least that was what I was originally talking about). Pressing this button rewrites the configurations files back to Protel 98 and will permanently set your layer capabilities back to the same era. You will have to either re-install or copy a section from a good file to get them back. Not sure what all effect this has, but I do know that it will get rid of alot of mech layers. I do not understand just what is meant by that first sentence above here, but I think that it may mean a lot more than just changing the colors to the Classic Colors scheme as I did on my machine at Optical Crossing. Can someone elaborate on just what exactly we are talking about here. I know that at some time on my OC system, I appeared to have lost the ability to alter the color of the Connections (if I ever had that ability), and I even seem to have lost that ability on my home installation too, although I do not remember having ever hit the Default Button on this system. Ian, You are probably the best one to explain this all, and also clarify why I would need to do something with the data you have provided below, and how I can tell whether or not I need to do anything at all. One final caveat: If I actually did alter something on my OC system other than just the colors of my ADVPCB99SE.ini file, would this account for some of the bizarre crashes that I and some others have been having all of these years that are still otherwise unexplained? Thanks, JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, October 09, 2003 2:05 AM Subject: Re: [PEDA] How to change drawing order? On 08:44 AM 9/10/2003, Ian Wilson said: On 08:05 AM 9/10/2003, Frank Gilley
Re: [PEDA] How to change drawing order?
I forgot one additional thing: Did anyone else get a post to this thread with an attachment from [EMAIL PROTECTED] ? Me thinks it might just be afoul of good intentions . . . Possibly a virus? I have not opened it . . . JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CTL key during routing placement electrical grid.
I too have an Official Protel 99 SE Mouse Pad . . . I Stopped by Protel NA in Rancho Bernardo (Baja Escondido) one day, and among other things, I asked them for a Protel Coffee Cup. Much to my surprise, they apologized and said that they did not have such a thing as a Proel Coffee Cup, but instead produced a Protel 99 SE Mouse Pad, and an Altium Frizbee (for Tasking if I remember correctly). I am trying to remember if they had Mouse Pads at PCB West . . . Anyway, I keep it in a compartment in my laptop case, just in case I run into something that will not work too well with my Logitech Optical Mouse, but I never noticed wheather or not it had a problem with that mouse, since I don't remember if I have actually ever tried to use it other than just momentarily, since the Logictech seems to work on pretty much anything I have tried it on, including my Levis and the console and seatcovers in my Jeep. Oh well . . . Never really looked at it closely . . . Hey, maybe it is useful after all . . . Just dug it out, and tried it with my Logitech, and it seems to work OK unless the Mouse Pad is not flat (notwithstanding that it is new, the Mouse Pad does appear to have a bit of a built in curl to it). I have noticed this before, that whenever the Logitec is not in direct contact with a flat surface, it misses some things. My Computer Work Bench is made from a large Kitchen Counter Top (imitation woodgrain) that I got from Home Depot (one of those super hardware stores), which has a radiused front edge (easy on the arms and wrists when working on the computer all day), but the radiusd edge is also raised just a bit from the remaining top surface (nice to prevent pencils from rolling off, etc.), and I notice that whenever the rear of the Logitech Optical Mouse goes up on the raised edge a bit the Mouse stops working. It appears to be because the Mouse works on reflected light, and changing the contact distance (even slightly it seems), appears to screw up the reflected light. Just noticed that it also screws up a normal mouse with a ball when the surface is not flat and I get too close to the edge with its radiused bump . . . JaMi - Original Message - From: Duane Foster [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, October 10, 2003 9:58 AM Subject: Re: [PEDA] CTL key during routing placement electrical grid. I have a Protel mousepad... it doesn't play well with optical mouse.. i thought my mouse was screwed up.. then i thought my mouse driver was hosed... then one of my cohorts suggested my mousepad was suspect... changed out the Protel pad and mouse stability has returned... i suppose i could tack it to the wall for reference... duane -Original Message- From: Steve Smith [mailto:[EMAIL PROTECTED] Sent: Friday, October 10, 2003 9:26 AM To: Protel EDA Forum Subject: Re: [PEDA] CTL key during routing placement electrical grid. Thanks, I wish I had gotten one of those. (Mousepad.jpg) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How to change drawing order?
Zhang, In the PCB Editor, select Preferences under Tools in the Main Menu. Under the second tab, Display, you will see a button labeled Layer Drawing Order, which will bring up a dialog box that will allow you to change the order in which the layers are displayed. Just select the layer that you want to move, and use the Promote button to move it up in the display drawing order, or use the Demote button to move it down in the display drawing order, and then press Ok when you are finished This should allow you to change the order in which things are displayed, which I believe is what you are looking for. Once you are finished doing whatever it is that you want to do, and you want to set the display drawing order back to normal, just return to the same dialog box and use the Default button, and everything will be set back to normal. Hopefully this will answer your question. JaMi * * * * * * - Original Message - From: Mr. Zhang Yangtian [EMAIL PROTECTED] To: Protel [EMAIL PROTECTED] Sent: Wednesday, October 08, 2003 7:48 AM Subject: [PEDA] How to change drawing order? When I doing PCB design, the drawing order is fixed, eg. The track of TopOverlay layer will cover the objects on the Bottom layer. Now, for some reason, I want to change this order and want the track of bottom layer can cover objects of all other layers. How can I change the screen drawing order under PCB mode? Thank you very much! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE has Altzheimers' ?
KLUNK ! ! !
I thought at one time that we could possibly embarrass Altium into some
kind of action on Service Pack 7, and I think that since it appears that
all else has failed, that maybe its time we should start making a some
more noise again.
It worked for ATS (at least superficially) . . .
The nicer, kinder, gentler, meeker, submissive, and more passive user
approach has gotten us nowhere in terms of fixing the remaining problems
with Protel 99 SE, and absolutely nothing except more refrains from the
upgrade to Protel DXP song and dance routine of some of the more
prominent users in this forum, almost as if they were either getting a
commission on DXP sales, or maybe even hoping that if they could get
enough new converts to DXP that Altium would fix it faster and even
possibly someday make DXP as productive as 99 SE (even with all of its
warts) . . . .
[insert primal scream here]
AGH ! ! ! ! ! ! !
Upgrading to DXP, even at this point in time, is not upgrading, but
still actually downgrading, in almost every sense. Yes, DXP may
someday actually become the super wazoo program it has the potential to
be, and even become a really functional alternative to 99 SE, and be
worth the price of admission, and even be worth the price of training
(or is that retraining), but it appears that at this point there are
still a number of DXP users that are still singing the blues and have
not yet seen the vision of the starry eyed and Altruistic Altium
faithful . .
Alt[ruistic]ium . . .
JaMi
PS. While members of this forum see an occasional DXP sob story, or even
the occasional story of success, to really see what's happening with DXP
you need to join the DXP Forum, from the Altium website, where you can
see the daily problems and solutions. Even as just Protel 99 SE users
you should still be able to join the DXP forum (since you are a
potential DXP customer), just to monitor its progress as it were.
Interestingly, or possibly the word is unfortunately, it is still even v
ery difficult to log into the official DXP Forum website and review
all of the previous posts that are archived there, since a good number
of the posts are totally scrambled and unreadable, since it is still,
even at this time, unable to correctly display the all of the various
different email formats.
* * * * *
- Original Message -
From: Robert M. Wolfe [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, September 18, 2003 5:20 AM
Subject: Re: [PEDA] P99SE has Altzheimers' ?
As far as I know it was never fixed and it still hangs
many many times on close so end process
needs to be done to shut down a machine.
Bob Wolfe
- Original Message -
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Wednesday, September 17, 2003 9:17 PM
Subject: Re: [PEDA] P99SE has Altzheimers' ?
i believe there is both a in memory cache and an in schematic file
cache
closing and reopening the file does not clear the memory cache as i
recall
you have to close the whole protel session
i think this was cleaned up somewhere along the way so that i have
not
found it to be much of a problem
please correct me if i am wrong about this behavoir
Dennis Saputelli
[EMAIL PROTECTED] wrote:
This probably strays from your query, but from memory, there was a
buglett
(I'm not sure if it's been fixed) in that where you define the
default
primitives in the schematic editor for schematic parts, one of the
PartFields was incorrectly mapped to another. Therefore, there
was one
part field you could not define, and another that appeared twice.
What
I
do now at the end of a design is to do a global change to all
schematic
parts and replace all part fields matched by: * with attributes:
{*=}.
...The weirdest thing however is that when I place the part,
delete it
and
then place it again all behaves as expected: non-hidden, blank
fields.
Every subsequently placed instance of that part (wether left-click
or
with
a new place command) is then OK, even when rotated...
this mysterious behaviour may have to do with how Protel
caches
placed library parts. Once you place a part in the schematic
editor, it
is cached in memory somewhere (escapes me as to where exactly at
the
mo).
Even when you place a part supposedly from the library, it adopts
the
cached part. This is overridden with the update cached parts
function.
I've also experienced Michael's situation once where an entire
databse
file etc vanished. This occured when Protel crashed and gave the
option
to ignore and continue or close. This one time I chose to
close and
it then kindly offered to save my work that had changed. The
mistake in
this case is to select save (and destroy).
HTH
Brendon.
[EMAIL PROTECTED]
09/18/03 02:00 AM
Please respond to
Protel EDA Forum [EMAIL PROTECTED]
To
Re: [PEDA] P99SE has Altzheimers' ?
P99SE has Altzheimers' ? Duh? You guys just now figuring that out? Unfortunately, it appears to be hereditary . . . I want my Service Pack 7 . . . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integration
Serak, Forgive me for jumping to conclusions, but it appears that you may be attempting to calculate the impedance of a differential pair, or what is commonly sometimes referred to as differential impedance, or more correctly, an impedance controlled differential pair. One common type of signal that falls into this category would be LVDS, which has a differential impedance of 100 ohms, but which could have each signal independently routed where they were not in close proximity to each other (no coupling) and each signal would then be routed as a 50 ohm line. When the differential pair is routed side by side in close proximity to one another such that there is intentional coupling between the two lines, it will usually be in one of two structural forms. The first would be a structure that consisted of two parallel traces over a ground plane, which is called differential microstrip, and the other would be a structure that consisted of two parallel traces between ground planes which is called differential stripline. There is yet a third structure which consists of two parallel traces where the traces are stacked one on top of the other, both of which are between ground planes, and I have heard this referred to as broadside differential stripline, although I cannot vouch for the accuracy of that terminology, nor do I know of any formula that can be used to deal with this last type of structure. The first two structures, differential microstrip, and differential stripline, are actually quite common today, especially in routing LVDS signals. Unfortunately, I do not believe that Protel knows how to really deal with either of these structures. However I can recommend you to a calculator called Zcalc, which is designed to handle just such calculations. One of the nice things that I like about Zcalc, is that it will simultaneously calculate both normal (single line) impedance and also differential impedance from the dimensions that you provide, so that you can not only check the single line impedance calculations against some industry standard such as AppCAD from HP (Agilent), but you can also see and understand the relationships between the different parts of the structures as you vary the different dimensions within the structure. Zcalc also has numerous links to other valuable information built right into it which you can access just by clicking the link in the lower right corner of the calculator, which will take you to its webpage, which happens to be identical to the link below: === http://www.logiccell.com/~jean/LVDS/ The link that you want to download your own copy of Zcalc is the very first link at the top of the page, with the date of 11/05/2001, and the version number of 1.30b9. A quick word of warning. There are many different calculators out there that call themselves differential impedance calculators, including some even referenced to by Zcalc itself, that have an error built directly into them, and therefore give incorrect answers. What happened here is that National Semiconductor wrote the definitive paper on LVDS, the LVDS Owners Manual, and some other important related papers (some versions of which the links in the Zcalc webpage will point you to), most of which are in PDF Format. Well, the problem here is that there is an error in one of the primary formulas given in the some of the PDF Literature, which appears to be limited to the Second Edition of the one PDF Literature file mentioned above (The LVDS Owners Manual), and it is not apparent from the PDF Literature itself, and is only commented on and the error explained by the National Semiconductor webpage that itself links to that PDF Literature. Thus if you access the National Semiconductor PDF Literature from any place besides the National Semiconductor webpage, you will never see the notice about the error, and any calculator you build from just that version of the PDF Literature itself will produce an error in the results. Well guess what? Almost everybody gets to the PDF Literature by using some direct link somewhere, and as a consequence goes directly to the PDF Literature, which has the error. Oddly enough, even though Zcalc it self does not appear to have the error internally, it still points you to the First Edition of the PDF Literature (only 66 pages), and not the Second Edition of the PFF Literature (101 pages). Possibly this means that the First Edition did not have the error that the Second Edition does, and Zcalc was coded from the First Edition without the error, and anything coded from the Second Edition will have the error, unless one gets to the correct webpage with the errata. Anyway, the following link will not only get you to the webpage that has the errata regarding the errors in the PDF Literatue at the at the bottom of the webpage, but it will get you to the current LVDS Owners Manual which is the Second Edition. http://www.national.com/appinfo/lvds/0,1798,100,00.html Fortunately, since Zcalc.exe
Re: [PEDA] Footprints with traces
When I initially sent this reply, I believe that I for some reason I hit some keys that somehow set a flag that required a varification of reception, and who knows what else, which appears from at least at my end here to have somehow disrupted normal distribition of the email to the list, resulting in my not getting either my cc back or the normal distribution copy (although I did get the verification (maby I sent a blank)). I am therefore sending this reply a second time, and I apologize if this results in yet a second distribution of the same email to the list. - JaMi == Mark, One way that I usually accomplish the task of placing all of the short traces and vias to the respective planes for all of my decoupling caps, or even for those resistors or capacitors that are in circuit but have one end tied either to a voltage plane or ground plane, is to define one trace, and one via, and then select them and then copy them with the location point of the copy being that of the center of the pad that is going to be grounded or tied hi. I can then use a keystroke combination of E P (edit place) using my little finger of my left hand on the E key and my thumb or index finger on the P key, and just do an E P followed by the placing of the copied trace and via with the mouse , using the space bar as necessary to do any rotating that may be necessary, and then once everything is positioned, I do a left click on the mouse to place everything. Then I simply repeat the process for the next location that needs a connection. Usually I can place a trace and via pair where ever I need them in a very short time, and I have not found it necessary to go to the extreme of having a special component, which would take even longer to define on the schematic (which would require a special footprint) than I would spend even on a large number of such connections. Very occasionally (and I don't remember what the circumstances are) the copied trace and via will assume the net name of the pad which you are connecting to, but usually you will have do an Update Free Primitives . . . from the Drop Down List of the Menu Button in the lower Left Corner of the Netlist Manager (found in the Drop Down Menu under Design, once I have placed all of the trace and via pairs. This copy technique works especially well if you follow the IPC-2221 guidelines that suggest doubling up the number of vias on decoupling caps, such that you need 2 vias, properly spaced, and a whole bunch of little trace segments to connect them to the center of the appropriate pad. This method usually gets the job done for me, although there are certainly other approaches to the problem, as have been described in other responses to your question. The nice thing about using a small narrow trace and a via that is placed a few mils away from the edge of the pad, as opposed to using an oblong pad as you mentioned, is that a small trace, although short, will provide enough thermal isolation from the connection to the power or ground plane, that it is not necessary to have any thermal relief on such a via where it connects to the plane. JaMi - Original Message - From: Leopold, Mark [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, September 10, 2003 5:53 AM Subject: [PEDA] Footprints with traces Hi, I am running DXP and I want/need to create a footprint that has surface mount pads connected to vias by a short trace that won't cause a whole lot of DRC errors on my PCB. The footprint is for bypass caps placed on the component side of a multi-layer board. The vias take the cap terminals to the appropriate power or ground plane. My company's boards are not that complex and I generally hand route them, so this would save me from having to run traces and placing vias for all the bypass caps. I could also see this being useful for creating footprints that will accommodate both SMT and THT resistors and caps -- which I could have used more than once in the past when prototyping. The problem that I run into is that in the process of generating the PCB from the schematic, the pad is correctly associated with its intended net, but neither the trace nor the via are associated with any net. This leads to DRC clearance errors as I have effectively connected a No Net trace to a pad with a net. Is there any way to setup the footprint or the schematic to PCB process so that the pad-trace-via combination are all added to the appropriate net? Another possible solution that I toyed with was to have an elongated pad with the hole offset, but I can't find any way to have the hole placed anywhere but in the middle of the pad. Is there a way to place the hole offset from the middle of the pad? Thanks, Mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list
Re: [PEDA] Footprints with traces
Mark, One way that I usually accomplish the task of placing all of the short traces and vias to the respective planes for all of my decoupling caps, or even for those resistors or capacitors that are in circuit but have one end tied either to a voltage plane or ground plane, is to define one trace, and one via, and then select them and then copy them with the location point of the copy being that of the center of the pad that is going to be grounded or tied hi. I can then use a keystroke combination of E P (edit place) using my little finger of my left hand on the E key and my thumb or index finger on the P key, and just do an E P followed by the placing of the copied trace and via with the mouse , using the space bar as necessary to do any rotating that may be necessary, and then once everything is positioned, I do a left click on the mouse to place everything. Then I simply repeat the process for the next location that needs a connection. Usually I can place a trace and via pair where ever I need them in a very short time, and I have not found it necessary to go to the extreme of having a special component, which would take even longer to define on the schematic (which would require a special footprint) than I would spend even on a large number of such connections. Very occasionally (and I don't remember what the circumstances are) the copied trace and via will assume the net name of the pad which you are connecting to, but usually you will have do an Update Free Primitives . . . from the Drop Down List of the Menu Button in the lower Left Corner of the Netlist Manager (found in the Drop Down Menu under Design, once I have placed all of the trace and via pairs. This copy technique works especially well if you follow the IPC-2221 guidelines that suggest doubling up the number of vias on decoupling caps, such that you need 2 vias, properly spaced, and a whole bunch of little trace segments to connect them to the center of the appropriate pad. This method usually gets the job done for me, although there are certainly other approaches to the problem, as have been described in other responses to your question. The nice thing about using a small narrow trace and a via that is placed a few mils away from the edge of the pad, as opposed to using an oblong pad as you mentioned, is that a small trace, although short, will provide enough thermal isolation from the connection to the power or ground plane, that it is not necessary to have any thermal relief on such a via where it connects to the plane. JaMi - Original Message - From: Leopold, Mark [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Wednesday, September 10, 2003 5:53 AM Subject: [PEDA] Footprints with traces Hi, I am running DXP and I want/need to create a footprint that has surface mount pads connected to vias by a short trace that won't cause a whole lot of DRC errors on my PCB. The footprint is for bypass caps placed on the component side of a multi-layer board. The vias take the cap terminals to the appropriate power or ground plane. My company's boards are not that complex and I generally hand route them, so this would save me from having to run traces and placing vias for all the bypass caps. I could also see this being useful for creating footprints that will accommodate both SMT and THT resistors and caps -- which I could have used more than once in the past when prototyping. The problem that I run into is that in the process of generating the PCB from the schematic, the pad is correctly associated with its intended net, but neither the trace nor the via are associated with any net. This leads to DRC clearance errors as I have effectively connected a No Net trace to a pad with a net. Is there any way to setup the footprint or the schematic to PCB process so that the pad-trace-via combination are all added to the appropriate net? Another possible solution that I toyed with was to have an elongated pad with the hole offset, but I can't find any way to have the hole placed anywhere but in the middle of the pad. Is there a way to place the hole offset from the middle of the pad? Thanks, Mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mentor Board Station Netlister
John, I have no direct experience with the netlister that you speak of. I have not used Mentor Graphics Board Station Version 6 (or are you referring to something else being V6) since the last time I was on lab at JPL in 1989, and while I did write a couple of interesting little Utilities that did a couple of different things to the wires file (or possibly it was called the routes file instead (?)), such as rotate the routes (routed traces) for the board (so the entire board could be rotated 90, 180, or 270 degrees), since in Board Station 6, (or at least 6.2) only an unrouted board could be rotated (it would not allow you to rotate the board along with placed traces). My solution to this limitation was to copy the wires file, and then delete it, and then rotate the unrouted board by the amount that you wanted to rotate it, and then rotate the traces in the wires file using my little Utility, and then copy back the rotated traces in the rotated wires file into the design directory, and walla! - instant rotated board with traces intact. Another thing I wrote a Utility to do, was to move selected layers in an already routed board down in the stackup a specified number of layers, so that a certain number of additional layers could be added in the center of the board. This too was accomplished by manipulating the wires file. If I remember correctly, Board Station 6 ran on an Apollo platform (at least the ones that we used at JPL did), and I had to copy the wires file over to a PC via the network, and then copy the wires file off onto a diskette, and then take it home and work my magic on it on my own PC at home, and then copy it back to a diskette and then go back across the network. Unfortunately, I never did any playing around with the netlist. And I can't remember if there ever actually was an intermediate (seperate) netlist file involved in the processing of a schematic. If there is an intermediate (separate) netlist file, it will show you the required format, and you might be able to do a quickie examination for compatability to the output from the Protel formatter(?) to the format required for Board Station 6. However, if such an intermediate (separate) file is not used, one thing that I do remember about Board Station 6, was that every single operation or keyboard entry, generated a corresponding entry in a script file that was about 37 and a half miles long, that accounted for each and every minute operation that would ever be performed, and the one thing that was unique about this script file, was that if you ever lost or corrupted your design files for any reason, you could completely recreate them from scratch simply by executing the script file (or relevant portion thereof) from scratch. Ok, so what this means practically, is that minimally you should be able to determine the format of a netlist by simply looking at either a netlist file, or if that is not directly available, by looking at the script file that results by compiling a schematic (or associating it, or whatever it was that we did to it (it has only been a short eon and a half ago since I did any of this, and the cells in that corner of the brain are a little oxidized)), and seeing how that compares with what is generated by the Protel formatter(?). Anyway, I believe that in the worst case, you would only have to make a netlist look like a script file to be able to execute it and enter it into Board Station 6. You might want to run this by your guy with Board Station 6 and see what he has to say about all of this. But now if you wanted to take your gerbers and generate a wiresfile of traces . . . Just kidding . . . JaMi - Original Message - From: John A. Ross [Design] [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, September 13, 2003 6:44 AM Subject: [PEDA] Mentor Board Station Netlister Due to time constraints I need to issue one of our partner companies with a netlist rather than a completed board. They use MG Board station as their layout tool. Has anyone used the Board station V6 netlister in 99SE successfully? Or can offer any advice on re-formatting or combining the files generated by 99SE? I have already searched on MG Support Net for information on the netlist format for EN2002 but cannot find it (unless it is hidden in some other manual) Thanks Best Regards John A. Ross RSD Communications Ltd 8 BorrowMeadow Road Springkerse Industrial Estate Stirling, Scotland FK7 7UW Tel +44 [0]1786 450572 Ext 225 (Office) Tel +44 [0]1786 450572 Ext 248 (Lab) Fax +44 [0]1786 474653 GSM +44 [0]7831 373727 Email [EMAIL PROTECTED] WWW http://www.rsd.tv == * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: *
Re: [PEDA] Mentor Board Station Netlister
John, Forgive me, but I am lost as to the meaning of EN2002. Is it somehow related to their (Mentor Graphics) current Expedition Series? If so, it may be that you are better off looking for a Cadnetix netlist generator, or even a VeriBest netlist generator, since the current Expedition has decended from Cadnetix thru VeriBest, and is actually unrelated to the former Board Station. JaMi - Original Message - From: John A. Ross [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Saturday, September 13, 2003 9:48 PM Subject: Re: [PEDA] Mentor Board Station Netlister Thanks Jami The end application is EN2002 version but 99SE seems only to have a MGBS V6 netlister. Like most of the netlisters in 99SE and DXP they are well out of sync with the latest versions of other vendors tools :-( There is currently no PCB file, only the SCH project from another design which will be reused as it is a proven block. I do not mind writing a utility to create any macros or otherwise to merge the 99SE outputs to some kind of readable format if it is not too involved. (and from what I read below there might not be a separate netlist file anyway). My Spanish colleagues will be back on Monday so I will ask if an intermediate file exists and get a copy of one. An alternative route I have not tried yet is CAM350, but I cannot access that until Tuesday. I believe I can create a protel PCB with just a netlist imported (delete parts after load), export as PCAD ASCII, save in CAM350 and then export as Mentor format file. Hopefully my friend has licensed these options! Long way for a short path, but I did not expect it to be easy. Best Regards John A. Ross ~ ~ ~ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License Legalities OT
Please see below . . . - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Monday, September 08, 2003 8:49 PM Subject: Re: [PEDA] License Legalities At 12:31 AM 9/8/2003, JaMi Smith wrote: A perfect example of . . . Since Mr. Smith wrote . . . Abd, Ian, and the group, At the risk of being flamed on, I actually believe that I can bring this topic to a very short conclusion. If Abd or anyone else that is interested will simply go to the following link and then put a check next to Penal Code and then do a search on the word software, and then find his way to California Penal Code Section 502. === http://www.leginfo.ca.gov/calaw.html In an effort to keep this short, this deals directly with the issue of software, and computer crime, which is the issue at hand, and forgoes any discussion of Cable TV signal theft which was brought up by me as an example (and which Abd actually admits is an exact parallel of his argument), and which I am also willing to discuss further offline. Please note that this is the Penal Code, which deals with public offenses (i.e.: crimes - criminal law), and does not even address the issue of civil law (which is another whole large case of cans of worms). Please read the entire section carefully, especially the intent portion of subdivision (a), and specifically note: 502 . . . (b) For the purposes of this section, the following terms have the following meanings: . . . (6) Data means a representation of information, knowledge, facts, concepts, computer software, computer programs or instructions. Data may be in any form, in storage media, or as stored in the memory of the computer or in transit or presented on a display device. . . . (c) Except as provided in subdivision (h), any person who commits any of the following acts is guilty of a public offense: . . . (2) Knowingly accesses and without permission takes, copies, or makes use of any data from a computer, computer system, or computer network, or takes or copies any supporting documentation, whether existing or residing internal or external to a computer, computer system, or computer network. . . . (d) (1) Any person who violates any of the provisions of paragraph (1), (2), (4), or (5) of subdivision (c) is punishable by a fine not exceeding ten thousand dollars ($10,000), or by imprisonment in the state prison for 16 months, or two or three years, or by both that fine and imprisonment, or by a fine not exceeding five thousand dollars ($5,000), or by imprisonment in a county jail not exceeding one year, or by both that fine and imprisonment. . . . And please don't be so ridiculous as to try and say that making a copy to take home without permission for your own personal use or your own commercial use in performing work for yet again someone else is within the normal scope of your employment. Please note that if your employer caught you trying to take a copy of his $8K Protel software without his permission, and he was ticked off enough at you and wanted to make an example out of you and call the police, the charge upon which you would be arrested, handcuffed, and hauled off to jail, would be Section 502(c)(2) of the Penal Code (I am sorry that I do not have an Annotated Copy in front of me so that I can give you further details from the actual case law). Needless to say, there would be many other things that he could additionally do to you in terms of civil law. Please also bear in mind that if Altium were in fact to attempt to make an example out of your employer and go after your employer in a big bucks civil lawsuit for violating the license agreement, your employer would have a very very large incentive to offload the whole problem onto you by simply pressing criminal charges against you based on the above section of the Penal Code (or whatever local equivalent there may be in your neck of the woods). While I can't actually find a copy of my EULA right this very minute for my Protel 99 SE, which I purchased from Altium North America here in California, I do know that my EULA for my Protel DXP specifically states that it is governed by the Laws of the State of California. Abd (or anyone else), If you wish to carry this discussion any further, please contact me offline, and I will be glad to discuss it further with you. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License Legalities OT
Response moved to the Protel Open Topic Forum at Techservinc.Com I apologize for not moving it over there sooner. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT employer topics WAS: License Legalities
Ivan, My question of Are you this liberal when you are the employer? was aimed at the Is he justified? Darn right he is, and whether one of your own employees would be justified in a similar circumstance if you were on the employer end. As far as everything else that you say here is concerned, I would say that you have made a pretty good case for the standard Employment Agreement, and I would say that on the average, the standard Employment Agreement is pretty fair to both parties. I also think that you have made a pretty good case for the use of Company resources issue that is to be found at the heart of most Assignment Agreements. It all boils down to what is done where and with what, and whether or not permission is given by the owner of the resources being used. JaMi - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, September 08, 2003 8:51 AM Subject: Re: [PEDA] OT employer topics WAS: License Legalities I am somewhat surprised at your stance above when it comes to what an Employer seems to owe an Employee, or what an Employee has the right to be able to do at the expense of his Employers time and resources. But then again, quite possibly you only consider this where other Employers are concerned. Are you this liberal when you are the employer? See below. I don't consider it being liberal, I consider it being fair. I once had an employee who was an amateur musician. He was even a pro for a while back in the early 90's - unfortunately the music scene shifted and his (heavy metal) band became an anachronism just as it was getting noticed. You know the lyrics in AC/DC's song Rock and Roll Ain't Noise Pollution, where the singer says Rock and roll will never die... Well, I got news for you pal, it's dead! It died in the early 90's. I haven't been able to listen to top 40 radio for over 10 years now. But I digress. And no, he was not a band member in AC/DC. Anyway, I hired this guy because he was an electronics buff. He had 2 years of vocational tech schooling, in addition to building circuits at home and repairing guitar amps and electronic instruments. He told me of his quest to build the perfect noise gate, compressor/limiter, tube amp, etc. He would ask me my opinions about circuitry. And we would enjoy these discussions during lunch and breaks. Now if he came up with some music gizmo he invented at home on his own time, I don't feel like I would own the rights to it. I even let him borrow one of the scopes for a while until he bought his own. But if any of what he did required design time from me (other than tips and advice during lunch and breaks), then I would feel like I had some ownership of it. I have enough ideas and creativity to make my own fortune. I don't need to rip off someone else's hard work to get there. And if my former employee makes it big someday with an electronic music instrument gizmo, I'm happy for him. As for me, I'll stick to embedded computers and control systems for now. As far as ex-employees going into competition, that is on a case-by-base basis. If the former employee started producing DOS Stamp clones, then I would take action against him. But if he starts making his own design based on an 8051, SH3, or some other CPU we've never used before, that's nothing to get riled about, because he didn't steal my IP to make it. By the way, what would you yourself do if your own little Company needed to get a certain job done for a Customer, and you walked up behind one of your employees who was supposed to be working on this job, and you found him working on his own little project, on your time, and you realized just by looking at what he was doing, that he had to have spent the last three days working on his own little project? What would you really do? I'd fire his ass. That is not the same thing as working on one's own project on one's own time. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Sunday, September 07, 2003 7:37 PM Subject: Re: [PEDA] OT employer topics WAS: License Legalities * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License Legalities
Tim, Firstly, you state If I have a valid license, and then turn right around and state registered to the company I work for. I take that to mean that the company that you work for is the purchaser and licensee of the Protel software in question. In other words, your employer, and not you yourself, is the owner of the Protel license. That means that from an ethical and legal standpoint, your employer, and not you, is the one that must decide what the Protel license must be used for. Assuming that your employer has a single seat license, it is up to him as to who uses that single seat, and additionally, where that single seat is used. I am assuming that this goes a little further, and that you are really asking is whether or not you can use a copy of your employers single seat license of Protel which might be installed on your own computer at home, to do work on that single seat for a third party. This needs to be handled as two different issues: 1.) Your employer has the ethical and legal right to install and use his copy of Protel on any computer system or network that he so chooses, and in any location that he so chooses, providing that it is only operated by one person at a time, which is the limit of his single seat license. Notwithstanding what the end user license agreement may state, this would extend to your employer asking you to install it on your own computer system at your own home, so that you could do work for him in the evenings or on the weekends, or even work at home, all providing that amongst all of the computers that it may be installed on, it was only operated by one person overall at any given time, again which is the limit of his single seat license. Your employer, as the licensee, can do this, but you, as an employee, have absolutely no right whatsoever, to install a copy of the software on your own computer at home, unless your employer asks you to do so. Please note that from a legal perspective your employer must be in control of the license, and of the computers that it is installed on, and the software must be removed once you cease to be in the employ of your employer, or at any other time that your employer may demand. In reality here, so long as your employer is in control of the license, and so long as no more copies of the licensed software are operated at the same time than allowed by the license, a court of law would find that there was virtually no difference in whether the software was used in the next room, or the next city 37 miles away. 2.) Now to what I believe might be the real issue. Can you use your employers Protel software license, to perform work for someone else. This is entirely up to your employer, who is the licensee of the software. Both legally and ethically, you cannot use it for any reason whatsoever without the full knowledge and consent of your employer. Would your employer allow you to use his licensed copy of Protel on his own computer system where you work every day, either during lunch of after hours, to do work for some other company? Your employer is the person who owns the license, and as such, he has the right to use it in any fashion that he so chooses, which includes allowing you as his employee to use it in any fashion that he (your employer) so chooses, as long as the usage remains within the scope of the license. Can your employer allow you to use it on your own computer at home to do whatever work for whatever reason that he approves of? Again the answer would be the same as above, so long as your employer is in control of the license, and so long as no more copies of the licensed software are operated at the same time than allowed by the license, It would be acceptable. Now to the bottom line. Is it legal or ethical for you to install a copy of your employers licensed Protel software on your own computer at home without your employers express knowledge and consent? ABSOLUTELY NOT ! ! ! Is it legal or ethical for you to do any work of any kind either for yourself or someone else or some other company on your employers licensed Protel software either on his computer at your place of employment or on your own computer at home without your employers express knowledge and consent? ABSOLUTELY NOT ! ! ! It's really very simple, the short answer is no. At the risk of possibly being a little bit too presumptious, I will now say that you should do what is legally and ethically the right thing to do and take Protel off of your computer at home. JaMi Smith - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, September 04, 2003 12:26 PM Subject: [PEDA] License Legalities If I have a valid license of Protel registered to the company I work for am I legally allowed to use it for work that I'm doing for another company? Both companies are in a different field of electronics and would not be competing in any way. Tim Fifield
Re: [PEDA] License Legalities OT
Jon, Interesting story, I know of yet another similar story, but which has a much different outcome. Back in the 70's, a very good friend of mine, John Scott Campbell, who is a joint inventor on my Patent, and who also had been a Professor of Mechanical Engineering at the California Institute of Technology here in Pasadena, introduced me to a very good friend of his, Ed Simmons, who has also been a Professor at Cal Tech. Ed Simmons is and was a legend, and a real eccentric character, and known by many, especially around Cal Tech. He could be spotted walking all over Pasadena wearing nothing but a sweater or sweatshirt, a pair of colorful tights, sandals, and a beret. John told me the story behind Professor Ed Simmons and Cal Tech. I am not quite sure what Ed's discipline was while he was teaching at Cal Tech, and I am not exactly sure when this happened, whether it was in the 40's or 50's or even later (John retired in 1953), but Ed had signed the customary Assignment Agreement which said that anything that he invented and Patented during his employment would be assigned to the California Institute of Technology. Well, Ed invented this little gizmo thingie, and he dutifully took it to the Patent Board (I think that's what John called it) at Cal Tech, and they immediately decided in their infinite wisdom that the little gizmo thingie was totally worthless and proclaimed that they did not want to waste any time or money on it or to Patent it or have it assigned to them since it was totally worthless anyway. Ed said OK, fine, since you consider my little gizmo thingie totally worthless, and since you don't want it, then will you please release it to me, so that I can try and pursue it on my own. Cal Tech said sure, OK, and released it to Ed. Ed applied for a Patent on his little gizmo thingie, and was awarded the Patent in his own name, without having to assign it to Cal Tech. Cal Tech had a change of heart, and decided that Ed's little gizmo thingie may not have been so worthless after all, and they took him to court to try and force him to assign it to them per his original Assignment Agreement. Fortunately for Ed, the court ruled in his favor and said that Cal Tech had had there chance, and that they had considered it worthless, and that they didn't want to do anything with the little gizmo thingie, and that they had released it to Ed, and that the Patent therefore belonged totally and completely to Ed, and that Cal Tech had no right in it whatsoever. Well, the worthless little gizmo thingie that Professor Ed Simmons had invented and Patented while he was teaching at Cal Tech was nothing less than the Resistance Strain Gauge. That Patent on the original Resistance Strain Gauge allowed Ed Simmons to retire and live very comfortably for the rest of his life. I am not quite sure how old Ed is now, or if he is still with us, or still walking around Pasadena as I write this, but I did see him walking down Colorado Blvd near one of his favorite haunts, C H Surplus, as recently as just about a year ago. If I remember correctly, Abd ul-Rahman Lomax of our little group here, went to Cal Tech, and possibly he has seen or met Ed and knows some more about him and his Resistance Strain Gauge. I also have some very personal experience along this line, having spent over two years before Judge Julius Title, in Law and Motion, in the Los Angeles Superior Court, in litigation with Faxon Communications Corporation, who was attempting to force me to assign my rights to my Patent (mentioned above) to them. Ultimately, the case was never scheduled for trial, and was finally dismissed after being unresolved and unsettled for over five years. Yes, I managed to keep my ownership of my rights as a joint inventor of the Patent, but in the end, the useful life of the technology yielded to the digital age of the microprocessor (this was back in about 1976 thru about 1982). But this is a story for another time. One other point that is germane to the issue, especially here in California, is that the State of California has actually enacted a provision in the State Labor Code that specifically deals with the question of Assignment Agreements between Employers and Employees, and is very liberal in favor of the Employee, since it specifically deals with and covers such things as whether or not something is within the scope of employment or business, and whose facilities and time were or were not used in development, etc., etc.. I am really surprised with the outcome of your example story in the paper below, especially since it appears that he actually got a release. There may have been some other mitigating factors to the story. Many agreements today cover not just inventions, but also cover many other things, such as specifically limiting activities in the same field for a specified time after employment, or require maintaining confidentiality indefinitely on certain things, or non competition clauses, or similar
Re: [PEDA] OT employer topics WAS: License Legalities
Ivan, Please see below. JaMi - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, September 06, 2003 12:14 PM Subject: Re: [PEDA] OT employer topics WAS: License Legalities Sure, you should work for your employer when he's paying your salary. But, I have heard of so many cases where a guy who designed aerospace parts, for instance, thinks up an idea for a better fishing reel, on his own time, and ends up having to give all profit to the employer. (There are, I'm sure, lots of cases that can be found where the employee used some facilities or company time to develop the product, that changes the picture very much.) It never ceases to amaze me how in so many instances, mandatory overtime without pay is never considered as a fair trade for usage of company resources. For example, my father is the Engineering Manager for a well-known air compressor company. For the entire time he has worked there (10+ years now), he has had to put in more than 40 hours per week. But since he is salaried, he only gets paid a fixed amount. The extent of his usage of company resources for personal benefit is: photocopies, paper, pens, scotch tape, occasional shipping of small packages via UPS. Big Whoop. He doesn't even surf the internet on company time, in fact he avoids use of e-mail because it is only a tool others use to cover their asses with (Oh, didn't you get my e-mail about that?). And yet, memos circulate, saying that employees are not to take office supplies for personal use. No one has ever confronted him about it, maybe because they realize how indefensible their position would be. So my overworked father uses some office supplies for personal use. Is he justified? Darn right he is. Is there a difference in walking out the door with a pen in your pocket that you have been using all day and which will probably come back to work and be used all day tomorrow, or on the other hand, going into the supply cabinet and taking a handful of pens to take home? I think that there is, and I think that most people would agree. Regarding the . . . occasional shipping of small packages via UPS, no comment. And regarding the But since he is salaried, he only gets paid a fixed amount syndrome, most of those that do work as salaried employees do expect to have to put in an occasional bit of overtime, and understand that it is all part of the job, and I would say that most people do in fact consider that when negotiating the salary to begin with. I know that I myself have specifically told my bosses that if they want x number of hours OT as the rule of thumb, then they are going to have to calculate that into my salary and pay me more accordingly. On the other hand, most bosses are also willing to compensate the OT required for the occasional unscheduled emergency with liberal amounts of comp time, which would be your fair trade. In places I worked before I started my own business, I refused to sign employment agreements that had language to the effect that any personal inventions belong to the company. As a result, I didn't get too far in the employee world. I did have jobs, but never achieved much rank, always low man on the totem pole, and the first to get axed when times got tough (motto: when the times get tough, the tough get axed). So I started my own business. And life is good... I think it is fair that an employment agreement could have language stipulating that the company is entitled to a small portion of the profits or shares of any invention the employee creates using company resources. In the example above, if the fishing reel was made using the company's machine shop, and drawings were drawn on the company's CAD system, maybe 5-10 percent of the profits or shares would be assigned to the company. But not the whole thing, that's just pure greed! Most, if not all, invention Assignment Agreements allow you to make exemptions for any ideas or inventions that you already have, and even those that you state that you plan to continue to work on, own your own time. As a legal practicality, most Assignment Agreements are usually only enforceable where the scope of the invention is within the scope of the Company's business. As mentioned in a parallel post to this original topic, the State of California has provisions in its Labor Code that specifically address the issues of whether an invention is within the scope of the Company's business, and additionally, whether the Company's resources were used to develop the invention. Unfortunately, in the above example, you specifically state that the Company's facilities as well as resources were used to build the prototype fishing reel, and any Court in the land would say that that makes the fishing reel the property of the Company, and would rule in favor of the Company every time. In the absence of some mitigating
Re: [PEDA] License Legalities
A perfect example of the New World Philosophy which states that there is no right or wrong, and I can do anything that I want to, and you have no right to tell me what is right or wrong, moral or immoral, ethical or unethical. I mean gee whiz, sure I stole a fifty thousand dollars from Bill Gates or some other billionaire, but he won't miss it, and he certainly won't ever use it, so it must be OK then because I need it. But gee whiz officer, I didn't hit anybody, and I am in a hurry, so why should I have to stop at every one of those stop signs or only go 25 miles per hour down this residential street, when I wasn't causing any problems by going 50. I don't care how much you attempt to justify the situation, what's right is right. and what's wrong is wrong. Truth is truth, and it does not change or waiver to suit the needs of the moment, or to justify ones actions, or excuse ones behavior, I don't care how much you want to philosophize or wax eloquent. Licensed Software that costs $8K a copy is a tangible asset as well as a proprietary asset of the company that paid for it, and theft of a copy of that asset is still theft, or actually it would be considered grand theft, which in and of itself is an unlawful act in most jurisdictions, notwithstanding any tort which would or would not be a civil action totally separate from the criminal charges involved. If you don't believe this, then steal a copy of Protel from a Government Contractor's facility and see how fast the FBI locks you up and throws away the key and then charges you with a Felony. Ethically, you're justification simply does not map to reality. That's like trying to say that you wouldn't have paid for a Cable TV Subscription anyway, so the Cable Company didn't loose anything by your using a Cable TV Descrambler to get free Cable TV. That is exactly the same argument that you are stating below. Identical. Well I've got news for you. In this State, it's not only theft (unlawful - illegal), it's a Felony, punishable by imprisonment (not just a few days in the local Jail, but a few years in State Prison). Ethical? There is absolutely no question that it is unethical, and I would bet that it would certainly be grounds for termination at just about every company that ever bought a Protel license, if you were caught taking the CD ROM and Access Codes home without permission. Remember, we are not talking about a Protel licensee that allows his employee to take a copy home and install it with his permission, or at his request. We are talking about an employee taking a copy home and installing it without asking. It would be totally futile to attempt to argue any specific points with you below, since you have already redefined both ethical and lawful behavior to conform to your own standards of right or wrong, and to justify your own world view, and if you can't even see or admit to that, there is nothing that I can say or do that would make you see that or change your mind. JaMi - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, September 07, 2003 8:29 PM Subject: Re: [PEDA] License Legalities I'm reminded of an old story. A poor and hungry man walked by a street-vendor's stand, with cooking meat, it smelled delicious. He stood there inhaling the odor. The vendor demanded that he pay for the privilege of smelling the food. When no payment was forthcoming, the vendor called the police and insisted that he and the alleged odor-thief be taken before a judge. Before the judge, the vendor insisted that the poor man had deliberately enjoyed the odor of his food and had refused to pay for it. The judge thought about this for a bit, then he asked the poor man if he had any money. The reply was, Just this coin. Hand it to me, said the judge. Then the judge asked the vendor to approach the bench. He held out the coin, but when the vendor reached to take it, the judge said, No, I'm only allowing you the smell of his money. Copyright is a statutory invention. There has been a major effort on the part of businesses which depend on copyrights to equate copyright violation with theft. It may be a tort, in some cases, but theft it is not. In theft a tangible is removed from the possession of its legitimate owner, the owner suffers a clear loss. With copyright violation, of the kind where someone uses software without permission or downloads a piece of music without payment or permission to the copyright owner, the owner has not lost anything; that is, the position of the owner is the same as if the violation had not occurred. However, Microsoft, the RIAA, et al, will claim that they have lost so many billions of dollars, basing this on the supposed lost revenue, generally calculated as if all those illegal users had paid for the software or music. But it is not at all clear that *anything* has been lost; in some cases it is quite possible that the
Re: [PEDA] License Legalities
Almost forgot. There are a whole new class of statutes which have been appearing recently (or at least getting a lot of attention in recent years), and that is in the arena dealing with the areas of illgotten gain and unlawful enrichment. I am not quite sure that these areas deal only with the civil arena, but rather I believe that they also get into criminal law as well. - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Sunday, September 07, 2003 9:31 PM Subject: Re: [PEDA] License Legalities A perfect example of the New World Philosophy which states that there is no right or wrong, and I can do anything that I want to, and you have no right to tell me what is right or wrong, moral or immoral, ethical or unethical. ~ ~ ~ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
Joe, Who says it has to be a 3mm thickness (I think you may actually mean that the trace has to be 3 mm wide)? Is this requirement imposed on you by an Engineer, or is it some requirement found in a datasheet for some specific circuit or device? A current sense resistor has to be in series (in line like a fuse would be) with the load (the circuit or voltage that is being sensed) so that it can determine how much current is being used. In most cases a current sense resistor is used so that there can be some feedback to the circuit that is controlling the voltage output of some type of voltage regulator (or voltage distribution), however, in few cases, it may be used so that the current can be measured for some other reason such as to take a measurement for a remote monitor of some kind. In most, if not all cases, there needs to be a direct and unobstructed path back to the feedback input of the controlling circuit (which in your case is the amplifier input) which has no additional loss (such as a resistive drop in the trace) which could otherwise affect the measurement. Typically, this requirement may be met by specifying a wide trace (such as your 3 mm requirement) for the feedback signal, but more often, a very short and direct trace can be used, which can usually be accomplished by having a good component placement so that the current sense resistor is not too far away from the circuit involved (however, you must still watch out for any direct feedback to the amplifier input from the other end of the current sense resistor, which is usually the output of the controlling circuit (in other words, the location of the sense resistor can be very critical)). As stated above, the current sense resistor is in series with the load, and this means that it is only there so that you can measure the current going thru it (by forcing a very small and controlled amount of current limiting), as opposed to being in the circuit for some other kind of current limiting, which is the normal function of a resistor. This means that the load side of the sense resistor (where you are also taking the trace back to the amplifier input (for a feed back measurement)) is also in most cases the supply voltage for whatever circuit is connected to this load side of the current sense resistor. This would mean that it should be a wider than normal trace so that it can handle the power distribution to that circuit, just as if it were the normal VCC (or other power supply) trace in your circuit if you were not using any internal planes for power or ground distribution. With that said, the real question that needs to be addressed here is just how much current is going thru the sense resistor to the load. It may just be that the 3 mm requirement in your case is for the load itself, as opposed to the feedback line from the load. On the other hand, if there is a very large load (on the output side of the current sense resistor) that is being measured by the feedback trace, then 3 mm might be a very appropriate width for the trace. What is critical here, is that you do not want any loss or any other variables in this feedback trace (which would affect the feedback measurement) that may vary from board to board due to such things as manufacturing processes (etching or plating differences or minute differences it the copper (trace) thickness), or which may vary in the same board from such things as the resistivity of the trace varying due to changes in ambient temperature during operation. All of this boils down to having a very good and direct path back to the current sensing input of the amplifier in your application which will not have any resistive loss or drop. Thus the 3 mm width requirement. In this case, I would additionally say that you do not want to have any feedthrus or vias in this feedback trace, nor do you want to have anything else in the trace that might in someway affect the resistivity of the trace. A parallel response to this post, which deals with your wanting to use two 2 different nets (the subject of this thread), suggests that you might be able to use two different nets as you request in your original post, and then using the Lomax Virtual Short method to join your two 2 different nets together. This would be a very good solution to your problem in just about any other application but this one, since the Virtual Short plays some tricks on Protel by having a very very small gap between the traces to overcome DRC errors and objections, but which itself is reliant on the two traces actually bridging or shorting the small gap (or more accurately, not etching it thru completely, or bridging it with solder) during the manufacturing of the board, which unquestionably will have a major impact on the actual resistivity of the feedback trace involved. For this reason, I would strongly advise you to not use the Lomax Virtual Short scheme, or in any other way attempt to isolate the feedback trace from the load side of
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
Joe, Oops !!! I actually forgot to the most important statement in my whole response, although it is implied (I actually started to write it in one place, but changed it and wrote something else, and then forgot to put it back in another location). The net name of the feedback trace, which in your case you said is Iret, must (as in ABSOLUTELY MUST) have the identical (as in ABSOLUTELY IDENTICAL) net name as anything and everything else connectet to the load side of the current sense resistor. It IS all the same net !!! It ABSOLUTELY MUST be all the same net !!! Your real problem is that you are trying to use 2 different net names !!! If you, or your Engineer, or your datasheet, have a problem with this, than do not put any name on that portion of the net on the schematic with a net label at all, but put Iret in parenthesis (such as ( Iret )) in a text string near the line on the schematic, or a text string that says NOTE: Current Sense Return near the line. Do anything but try to make it a different net !!! JaMi - Original Message - From: Joe McCauley [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 4:09 AM Subject: [PEDA] Joining 2 different nets keeping seperate identifiers? I need to have a current return line with 3mm thickness. This line has a net identifier of 'Iret'. This line connects to a current sense resistor. I need to take a line from this resistor to an amplifier input. There is no need for this amplifier input line to be 3mm thick, in fact from the point of view of routing it would be better if it were not! Is there a way of joining 2 different nets in the schematic while keeping seperate identifiers? If there were then I could setup the design rules in PCB to always have the 'Iret' net 3mm thick, while the other one which connects to it could be (say) 0.35mm. Am I over complicating things by trying to do it this way? Thanks for any pointers, Joe * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
Ian, Please see below, JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 3:49 PM Subject: Re: [PEDA] Joining 2 different nets keeping seperate identifiers? On 07:40 AM 4/09/2003, JaMi Smith said: Joe, Who says it has to be a 3mm thickness (I think you may actually mean that the trace has to be 3 mm wide)? Is this requirement imposed on you by an Engineer, or is it some requirement found in a datasheet for some specific circuit or device? I would expect that the spec is wide uncalibrated current carrying traces with narrow current *sense* traces running off to the sense amplifier. This is a pretty standard sort of interface in high or precision voltage or current applications. You take a pair of sense traces to the load or sense resistor rather than using the uncalibrated high current traces for both current carrying and sensing. The 3mm width requirement would come from the expected current, while the thinner traces are used for the actual sensing. Very standard stuff. (Many bench-top power supplies will have sense terminals that allow you to control the voltage at the load rather than at the supply terminals, there is usually weak feedback in the supply to ensure that the supply is controlled if the sense terminals are unconnected.) The requirement is perfectly reasonable to me and I would either solve it by setting up from-tos and appropriate rules or by the Lomax Virtual short. In DXP it could be solved by a net tie component. Ian The initial question is not because I want or need to know why there is a requirement for a 3 mm trace width, but so that Joe can understand what the problem is, and just what the requirement may apply to. While I wouldn't necessarily state what you did in your first paragraph the way that you stated it, it does get the point across, and is not different than mine (although stated somewhat backwards as compared to what I stated). If you will carefully re-read my post, and also read the follow-up post with what I forgot to put in the original, you will see that I am trying to explain just where the high current is and where it goes, and just exactly what the current sense resistor does, and what the requirements may be for a feedback trace from the load side of that current sense resistor, and what the 3 mm requirement may apply to. If you will also carefully re-read the original post from Joe, you will see that this requirement has nothing to do with remote sensing, such as in your example in your second paragraph of the power supply, but that he is directly taking a trace from the load side of the current sense resistor, and feeding it directly back into the [current sense] amplifier input. I am sorry for my omission in my original post, but hopefully with the supplement from my follow-up post, it will all become clear. Yes, my original post is a bit confusing, but I think that you will see that we are saying the pretty much same thing, with respect to your first paragraph above, and that your second paragraph really does not apply to this instance. Respecting your last paragraph, I am fairly sure that when you get my follow-up post and think the whole thing thru together with the first post, that you would concurr with me in what I stated in my follow-up post, that the present case that Joe is describing, that the feedback trace is in fact the same net as the net connected to the load side of the current sense resistor (which in fact is just exactly what you yourself describe in your first paragraph above), and that it really should not have a different net name, and that the different net name is the real problem here (but which would not be the case in the example of your second paragraph). That said, I think that you would additionally concurr with my stating that anything that would introduce any loss or drop in the feedback trace should be avoided (such as the loss that would almost certainly be introduced by unnecessarily using 2 differnt net names and trying to join it all together with a Lomax Virtual Short (with its intentional gap which can allow for some small and uncontrolled amount of etching of the trace at the point of the gap), or by using too narrow a trace which could cause too much restivity in the trace). I would also think that whatever DXP may or may not do here does nothing but confuse the issue (especially if there is no reason to have 2 different nets in the first place). Sorry for any confusion, but I think you may be trying to say the same thing as I did with respect to the present situation, and that the case for the isolated remote sense (as you described in your second paragraph) does not in fact apply to this situation. Sorry again for any confusion. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http
Re: [PEDA] WANTED: Protel 99se license
Jeremy, You might also check on Ebay, as copies also show up there for sale from time to time, although the usual cautions should be observed to make sure you are buying a valid license. Another thing that you might be able to do in the intrim until you can find a valid license for sale, would be to try and track down a Trial Version of Protel 99 SE, along with Service Pack 6. This would hold you over for 30 days. While it appears that these are no longer directly available on the Protel Website, it may be available directly from a Protel Distributer if you ask very politely, or there may be a few people out there on this list which could give you a copy of the Trial Download if anyone has one, or the Trial CD, or maybe loan you their Trial CD. It might also be that the Trial Version of Protell 99 SE could still be available for downloading from the Protel Website, if one happened to have the right link, which is obviously no longer there. To that end, does anyone happen to have some of the old links to the old trial download pages on the Protel Website for the Trial Version of 99 SE and for SP6, which might just possibly still work? JaMi - Original Message - From: Thomas [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 5:01 PM Subject: Re: [PEDA] WANTED: Protel 99se license Try: http://groups.yahoo.com/group/protel-users-resale/ -Original Message- From: Jeremy Thompson [mailto:[EMAIL PROTECTED] Sent: Thursday, 4 September 2003 09:02 To: [EMAIL PROTECTED] Subject: [PEDA] WANTED: Protel 99se license Hello. I am after a Protel 99se license. If you have a license lying around collecting dust that you would like to sell, please let me know. Jeremy [EMAIL PROTECTED] - Do you Yahoo!? Yahoo! SiteBuilder - Free, easy-to-use web site design software * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
- Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 4:50 PM Subject: Re: [PEDA] Joining 2 different nets keeping seperate identifiers? At 07:09 AM 9/3/2003, Joe McCauley wrote: I need to have a current return line with 3mm thickness. This line has a net identifier of 'Iret'. This line connects to a current sense resistor. I need to take a line from this resistor to an amplifier input. Here is what I understand from this: this circuit is measuring current by measuring the voltage drop across the sense resistor. The current being measured is sufficient that a 3 mm trace is required. Presumably the temperature rise calculations have been done Or the trace is that fat so that error due to voltage drop in the trace is minimized. There is no need for this amplifier input line to be 3mm thick, in fact from the point of view of routing it would be better if it were not! Mr. McCauley writes about one line. Really, there are two, since one is measuring the voltage drop across a resistor. Of course, if there is a solid enough ground at the ground side of the sense resistor, one might assume that the drop in that part of the circuit can be neglected. Or perhaps the circuit will be calibrated to account for that additional drop. Otherwise one needs *two* sense lines, which will feed a differential amplifier of some kind. Presumably there will be negligible current in the sense line (the amplifier input line.) At least whatever measures that voltage should be designed to minimize the current. So the line can be narrow, really it only needs to be wide enough to be reliably fabricated. Is there a way of joining 2 different nets in the schematic while keeping seperate identifiers? If there were then I could setup the design rules in PCB to always have the 'Iret' net 3mm thick, while the other one which connects to it could be (say) 0.35mm. Am I over complicating things by trying to do it this way? I don't think so. I'm from the school that thinks that good DRC is very important. You can certainly accomplish what you want by setting the minimum thickness for Iret at 0.35 mm and the maximum at 3 mm. But this won't guarantee that you get 3 mm where it is needed. There might be some way to do this with from-tos, as mentioned by another designer, but I don't know that. I do notice that From-To Class is one of the possible attributes controlling width rules, but I've never investigated that rule. Maybe I should read the manual Naah, that's something I recommend to others, I don't do it myself :-) As mentioned by Mr. Ross, the so-called virtual short will accomplish this. Once you have built this footprint, have placed a symbol for it on the schematic and have wired it, and have set a design rule for the footprint (or component class, if by some chance you had different kinds of these creatures), it is pretty much set and forget. You would have your IRet net, being the return net for your large current. Then you would place, on your schematic, the virtual short, which is, for schematic purposes, a jumper. One side of the jumper is connected to IRet, typically right at the sense resistor pad. The other side of the jumper is connected to your sense net that goes to the amplifier. You could actually make the jumper structure part of the sense resistor pad, which would guarantee that the short is placed in the proper location. In other words, you'd build a symbol and footprint for the sense resistor that had two extra pads for the sense connections. These pads have a gap between them which is below fabrication possibility. Properly designed, there will actually be *no* gap on the films, because the gap will be well below the gerber resolution. It might be, say 4 microinches. (Protel can get a tad flaky in the microinch region since that's the database resolution, as I recall, otherwise it could be 1 microinch!) Then a design rule allows pads in that particular footprint to be very close to each other, say 2 microinches, without creating a DRC violation. By the way, you'll use rectangular pads How do you make the virtual short? I described above the principle for using fabrication limits to create a physical short that Protel considers as being unconnected. There is at least one other way, which became practical and reasonably safe when the CAM Manager was created, allowing custom CAM setups for your design. One of the mech layers is dedicated to a short, that is, a shorting trace is on that mech layer. It is merged with the normal layer as part of the CAM definition for the normal layer. With the fabrication limit method, you need to create a design rule. It's a good thing that if you forget to do this, you will get a DRC error, so this is quite safe. The down side of this method is that if you aren't careful about how your CAM pad
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
Oops, sorry for the empty response . . . that's what happens when you double click the reply button . . . operator error . . . I think that there should be a little more clarification of a few things before the misunderstanding in this thread becomes too rampant. There are basically two different ways that a current sense resistor is normally used. The first is between a voltage source and a load, and the second is between the load and ground. In both cases, the voltage drop is measured across the current sense resistor between the supply leg and the load. Typically, in this type of scenario, the voltage source is the output of a regulator, with the feedback from the load side of the current sense resistor being used to control the output of that regulator. My original response and follow-up, as well as my response to Ian's post, are based on a current sense resistor being used between the voltage source and the load. I believe that Ian's response to my post also assumed that we were talking about the current sense resistor being placed between the voltage source and the load also, but it may not have, although it does not really make a difference in his post or in my response to it. It appears that Abd, in his response below, is invisioning the current sense resistor in the second location mentioned above, which is between the load and ground, or possibly that could be better understood if it is stated as the between the return from the load and the ground. While this is different than I envisioned, the problem is really the same, and that is that the current sense resistor is usually put in one leg of a supply or regulator curcuit (either positive or negative) so that the current can be determined by measuring the voltage drop across the resistor between that leg of the supply and the load, or if you prefer, between the load and the supply. In either case, the feedback to the amplifier must be connected to the load side of the current sense resistor, with the other side of the current sense resistor connected to the appropriate positive or negative source, as dictated by the design requirements of the circuit, such that the current sense resistor is in series with the load This load side of the current sense resistor is both the place that any high currents going to or comming from the load must travel in order to get from or to the supply (or regulator circuit), and it is also the place from which a feedback trace must be connected back to the input of the amplifier that moniters the voltage drop across the current sense resistor. I am pointing this out so that anyone reading this compilation of responses can understand the differences in the possible location of the current sense resistor in the different discussions, and understand that while there are these differences, the requirements for handling the feedback from the load side of the current sense resistor is virtually the same in all of the discussions, notwithstanding possible confusion brought about by where the supply end of the current sense resistor is located. With that said, I have a few additional comments below. JaMi - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 4:50 PM Subject: Re: [PEDA] Joining 2 different nets keeping seperate identifiers? At 07:09 AM 9/3/2003, Joe McCauley wrote: I need to have a current return line with 3mm thickness. This line has a net identifier of 'Iret'. This line connects to a current sense resistor. I need to take a line from this resistor to an amplifier input. Here is what I understand from this: this circuit is measuring current by measuring the voltage drop across the sense resistor. The current being measured is sufficient that a 3 mm trace is required. Presumably the temperature rise calculations have been done Or the trace is that fat so that error due to voltage drop in the trace is minimized. There is no need for this amplifier input line to be 3mm thick, in fact from the point of view of routing it would be better if it were not! Mr. McCauley writes about one line. Really, there are two, since one is measuring the voltage drop across a resistor. Of course, if there is a solid enough ground at the ground side of the sense resistor, one might assume that the drop in that part of the circuit can be neglected. Or perhaps the circuit will be calibrated to account for that additional drop. Otherwise one needs *two* sense lines, which will feed a differential amplifier of some kind. Presumably there will be negligible current in the sense line (the amplifier input line.) At least whatever measures that voltage should be designed to minimize the current. So the line can be narrow, really it only needs to be wide enough to be reliably fabricated. I would disagree here, in that I believe that the trace should be large enough to not contribute any losses of its
Re: [PEDA] Joining 2 different nets keeping seperate identifiers?
- Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 03, 2003 8:10 PM Subject: Re: [PEDA] Joining 2 different nets keeping seperate identifiers? On 12:43 PM 4/09/2003, JaMi Smith said: There are basically two different ways that a current sense resistor is normally used. The first is between a voltage source and a load, and the second is between the load and ground. In both cases, the voltage drop is measured across the current sense resistor between the supply leg and the load. I think, Jami, that you are missing a critical aspect or it is getting buried in too much verbage. Sorry if I have just missed it, I am afraid I am doing you something of a disservice by not reading your post(s) in full. You are right in that sometimes I can get too longwinded in trying to explain someting, and I really need to try and just keep it short and simple. It is common to have four connections to a current sense resistor, two on each side. One on each side will be big and fat to carry the current, and the other with be a signal trace (carrying no current) that ensures the voltage drop across just the resistor is sensed - the voltage drop across power tracks, ground planes etc are ignored. The only tricky stuff with this is that it requires common-mode input ranges beyond, or at least close to, the supplies in many situations - but this is no longer rocket science. I agree with most here except the carrying no current, where I would say that that there is quite probably at least a small amount current (unless the amplifier has CMOS or FET inputs) but which is nontheless large enough to be affected by the restivity of the trace, where too narrow a trace, or differences in thickness and or width in manufacturing could cause differences in operation of the sensing circuit from board to board. If this is a very high current application, there could even be some fairly decent currents in the feedback loop, depending on just what was going on in the regulator portion of the circuit. In many regulator IC's this feedback input can even be the base of a bipolar transistor, whose operation is actually current controlled, notwithstanding that it may appear an amplifier in the datasheet. Even in the case of CMOS or FET inputs to an amplifier, which I think would be avoided in this type of application, but which really would have no current flow involved, I would still maintain that crosstalk and any losses due to restivity should still be avoided. I concurr respecting the 4 connections, but I am simply assuming that the 2 connections on the side of the voltage source (or ground in the sceneario discribed by Abd) are considersd internal to the regulation circuit, and have therefore not discussed them. I am also assumming that there is a regulator circuit involved in the original application which lead to the initial questions in this post, but possibly I am going to far in that assumption, which I have based most of my comments on, and even some here above. Oh well. Thanks for the feedback. JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2 SESSIONS
Dennis, How about a mouse with a 15 pound spring in the left button? Its kind of like having an Are You Sure? dialogue built right in, and since it takes both hands to operate, it really makes you think twice (if not three or four times) before you do any double clicking. ; ) JaMi - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, August 28, 2003 4:49 PM Subject: Re: [PEDA] 2 SESSIONS god i hate when i double click a DDB by mistake (instead of dragging it) Protel starts another session (which i have proven to be a 'bad' thing - library troubles commence) seems like it might be feasible for a utility to watch for a program starting, check if a session is already running and then advise or prevent any Windows gurus out there? is this feasible? this could be useful for other programs too Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2 SESSIONS
Dennis, Actually, many programs do in fact check to see if there is already another instance of itself running, and just open the file in the instance that is running. For example, Adobe Acrobat does check and open pdf files in an existing instance. Unfortunately, Protel does not check for much of anything, and the double instance issue has been brought up before. I thought it might be possibly responsible for some of the hidden processes that don't show up until you go to shut down the computer. Unfortunately, this particular problem is one of these loose nut behind the wheel problems. It was just doing what you told it to do. JaMi - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Friday, August 29, 2003 3:57 PM Subject: Re: [PEDA] 2 SESSIONS Dennis, How about a mouse with a 15 pound spring in the left button? Its kind of like having an Are You Sure? dialogue built right in, and since it takes both hands to operate, it really makes you think twice (if not three or four times) before you do any double clicking. ; ) JaMi - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, August 28, 2003 4:49 PM Subject: Re: [PEDA] 2 SESSIONS god i hate when i double click a DDB by mistake (instead of dragging it) Protel starts another session (which i have proven to be a 'bad' thing - library troubles commence) seems like it might be feasible for a utility to watch for a program starting, check if a session is already running and then advise or prevent any Windows gurus out there? is this feasible? this could be useful for other programs too Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Copper thickness VS mounted rails.
- Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, August 14, 2003 4:57 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. The problem with calling out 4 oz. Cu, or even 2 oz. for that matter, is that the board house will probably pattern plate the Cu, and it may not be uniform. There is additionally the problem of etching small traces in the same layer, due to the thickness. My PCB house says that their process is a positive growth of copper, not an etch process. Is this your described pattern plate? When you say not uniform, how much error can I expect? Will it matter with traces from 50 mil to 500 mil. My PCB does not have any fine traces. It's a pure CMOS class A audio amp and power supply. 3-4 traces are 25 mil wide (audio in), everything else is at least 50 mil wide, mostly 250 mil wide. Most boards today have at least one additive process, where the outer layers and all of the drilled holes that are to be plated thru, get a layer of electrically plated copper. This usually follows a non electrical plating process where there is a small amount of electroless copper (copper that is plated / deposited chemically) plates the entire board, including the inside of the drilled holes, so that the entire board (including the inside of the holes) can be electrically charged so that electrical plating process will extend into the holes. Typically, this electrical plating process may plate an equivalent plating thickness of from 1/2 ounce to 1 ounce of copper, or more. Thus if you specify 1 ounce of copper for the outer layers of the board, your board house may start with 1/2 ounce (or less) copper foil on top of several layers of prepreg, or use a laminate with 1/2 copper (depending on the stackup), and then plate up an additional 1/2 ounce of copper (after the electroless process), so that the final thickness of copper on the outer layers is a full 1 ounce, and the copper wall thickness inside the holes is approximately 1/2 ounce. This process can vary greatly, depending on just how much copper you specify on the outer layers and what you want in the wall thickness of the plated thru holes. Once the copper is plated up to the final thickness, the board is then usually masked with the trace pattern and then etched. There are a few variants to this process. First, there is the process whereby all of the copper that is to be placed on the board is added thru selectively plating copper only in the areas where there is to be copper in the final board. This is an additive process only, and involves no etching away of any unwanted copper. This process / method of making boards has been around almost as long (if not longer) as the etching process, and has been very popular offshore where very large quanties of boards are made and where this process can save lots of money by not only needing as much (or little) copper as you are actually going to use, but additionally in the saving of the cost of etchant and echant disposal. Another process, which combines the best of both worlds, is used quite often by many vendors today. This is the pattern plating process (although you could easily apply this name to the previous process, and this process may go by different names in some locals). In this process, you begin with a thin layer of copper on the outer layers (or any other layers for that matter), of say 1/4 or 1/2 ounce, and then you electrically plate up the remaining thickness of copper (with or without electroless plating as may be required for plated thru holes). The difference here, is that you first mask the thin starting layer of copper with an inverse image of the final copper traces and features, so that you will only plate copper in the areas that are to have copper in the final design. The next step in this process would then be to clean off the original mask and then remask only the areas that you have plated up (which masking can even be done by plating the conductor pattern with solder, if you use the proper etchant), and then you etch away the small amount of unwanted copper which remains from the starting layer of 1/4 or 1/2 ounce copper. Aside from the normal benefits of using less copper and extending the life of your etchant, there is another major benefit with this process in that it can yield much better control of very fine copper features (traces / lines / etc,) since there is much less copper to be etched (thickness wise), and much less undercut in the etching process. Thus the primary advantage of this process, is the control of finely etched features. However, there is also a major drawback in using this process, in that when the entire thin starting layer is masked, and then when the board is electrically connected to the plating supply (which makes the whole board become an electrode in the plating process) and immersed in the plating bath, the amount and
Re: [PEDA] Using DXP with a networked library.
It could also be possible that you actually had two wires going to the same connection location, in which one was right on top of the other for part of the distance. JaMi - Original Message - From: Kiba Dempsey [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, July 31, 2003 6:13 AM Subject: Re: [PEDA] Using DXP with a networked library. Thanks for your email; this system seems to work well, although it will still take some time to get used to the differences between Protel libraries and DXP. Cheers Kiba -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED] Sent: 21 July 2003 09:47 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] Using DXP with a networked library. Kiba This problem has been around for as long as there have been people using CAD Systems to design things. The first part of the answer to the problem is to make sure that everyone references the same Master Library, as opposed to a copy of it which may be residing on a local disk (this eliminates people using obsoleted symbols / parts). The second part of the answer to the problem is not to allow anyone to access the Master Library in anything other than read only mode, excepting the one person who is in charge of keeping the Master Library updated. I would propose that you consider something along the following lines: No one should be able to go into your Master Library at his leisure and add things, or even more worse, edit things. Make the Master Library read only, and set up an Interim Library which can be accessed by anyone, but which contains only new or edited symbols / parts, which need to be checked and approved before being added to the Master Library. New symbols / parts, or editing of existing symbols / parts (which should be accompanied with an appropriate renaming of the part (minimally with a modifier of some type added to the original name, or a totally new name)), should be done in a Local Library (local, as within the database of the design where it is needed), and then submitted to (copied into) the Interim Library for everyone's review, and then when approved they can be placed / replaced in the Master Library by the one person who has control of the it. In this scenario, all work is done in Local Libraries, and the Interim Library is only accessed for as long as people need to copy finished symbols /parts into it from their Local Lobraries (or review symbols / parts copied there by others), and the Master Library only gets accessed by the one person in charge of it, and then only long enough to add what ever needs to be added (or overwrite the old file with an updated version). A Local Library can be easily created within a design database by using the Make Library function in the Design menu. If you delete all symbols / parts from this Local Library excepting that which will become the new ones, the Local Library will be very small and only contain those items which are pending approval. An easy way to make a new symbol / part (or edit an existing one), is to place a similar symbol / part into the design from either the Master Library or the original Altium / Protel Libraries, and then create a Local Library with the Design Make Library function, and then edit that symbol / part as required, including renaming it, and then deleting the original symbol / part from the design, and replacing it with the new symbol / part. Once the symbol / part is placed into the Interim Library, and then finally into the Master Library (after approval), it may be necessary to replace the symbol / part once again with the final version from the Master Library, at which time the Local Library within the database can be deleted. Additionally, you might find it helpful to make all of your standard Altium / Protel Libraries read only (especially where they may reside on users local disks), so that they can not be edited by anyone, and set up a Master Library for your company, and copy things out of the Altium / Protel Libraries and place them into your Master Library for the company on an as you need them basis. This allows you to keep the original Libraries as delivered, and make any appropriate changes you to a symbol / part as you deem necessary for your company's uses, which may include renaming the symbol / part to meet your company's specific needs. This will also allow your company Master Library grow very quickly on an as used basis, with very little extra work. When coupled with a 'look in the Master Library first' policy, this can help create a well organized Master Library which contains only the symbols / parts you have actually used in your designs, and which by default can become your Preferred symbols / parts Library While there are many variations to the above, hopefully the it will give you some food for thought. JaMi - Original Message - From: Kiba Dempsey [EMAIL
Re: [PEDA] PCB Copper thickness VS mounted rails.
Brian, Sorry for the late response, but here goes. The problem with calling out 4 oz. Cu, or even 2 oz. for that matter, is that the board house will probably pattern plate the Cu, and it may not be uniform. There is additionally the problem of etching small traces in the same layer, due to the thickness. Solder, or solder plate (with or without soldermask so that you can put more on), as brought out in an earlier post, is a very very poor design choice, simply because solder will only carry about 16 percent of the current that copper will. You should never rely on solder to carry any current whatsoever. This is why solder is always excluded in any current carrying capacity calculations, whether they be the old MIL STD 275 calculations or charts, or any of the numerous newer ones (the IPC charts are the same as the old 275 charts). Bus bars do offer a solution, as does plain old wire. I would opt for the wider traces, as brought out in one earlier post, and I would distribute the copper on both sides of the board, and stitch it together with a very liberal sprinkling of vias, which should allay your fears about the connections that you bring up below. Remember to account for the size of the vias in your trace width calculations (subtract out the hole size(s) from the width of the trace)). Is it possible that the caps are large enough to have screw type terminals? If so, you could possibly use a wire with a terminal, in addition to the copper traces. Someone also mentioned a 10 - 15 degree C rise in conductor temperature in an earlier post. That is one problem with most current capacity calculators today, is that they start at 10 degrees C, and the fact is that you really do not want to design in a 10 degree C rise in temperature to your product, not to mention 15 degrees C or anything higher. In reality, unless you have a lot of airflow and lots of extra cooling capacity, you really should be designing for something mush less than 10 degrees C for the normal operation of the product. If you get large surges in current that last for any considerable length of time, and you get them often, then maybe it is time to increase your nominal / normal current rating a bit. JaMi - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 08, 2003 10:26 AM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon I don't like making power supply PCBs with power traces on both sides. Especially with large snap-in caps. It is too difficult to ensure that the top of the PCB under the cap has a good solder to the huge fat traces just like the bottom. I've experienced such designs where power supply sections get a fine odd crackling type noise, which may be mistaken for a bad caps, but it really was fine cracks in the solder on the top layer just under the cap. With a 1 layer board, such a problem is easily caught. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Jon Elson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 04, 2003 1:59 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. Brian Guralnick wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15 amps. Check with your PCB vendor on how much the extra thickness of copper will cost you. Then, compare with the rails, including the cost of having the assemblers deal with it. If the 4 or 6 Oz foil will carry the current with acceptable electrical characteristics, it sounds like the best solution, unless the extra cost is prohibitive. My guess is the extra foil thickness will be cheaper than all the extra handling to assemble the whole thing. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum
Re: [PEDA] Analysing...
Not to beat a dead horse, but what are you using for mouse software? - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 02, 2003 5:49 AM Subject: Re: [PEDA] Analysing... You know , i have have my own confusion both self afflicted and for using Protel.,Since i join this company i has been told to use Protel but the fact is that it seem to me Protel's old and new version do not alleviate anything much other than cosmetic and workaround change as the main sunject matter.Imagine all the feature it got but some is quite unusable for what it intended to be,and i still didnt know why my Protel 99SE with service pack 6 still crash even thought i have 256 mb ram on a Asus board with Pentium 4 at 2.4Ghz.It happen on multiple machines both new and old and i dont think the problem is with the Nvidia's graphic engine. Choong Terry Creer [EMAIL PROTECTED] wrote: Ok, Thanks to all who answered. I think the long term fix is to rip up the 35 polys, and do it properly by laying keepouts in the right areas and using as few polys as possible. Pain in the bum, but nicer in the long run. however, I think with these suggestions, I can wing it until it can be re-done. Cheers, TC __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
Terry. Welcome to the world of Protel. If you are only waiting 6 seconds for each Analyzing GND session, consider yourself extremely lucky. I have done boards that would take several minutes each time it would go south for the winter on an Analyzing session. This is my all time favorite Protel tie the computer in a knot trick. This is where I have even gone into the Task Manager, only to have it tell me that Protel is not responding, and then have Protel reemerge fine and still operatring properly after I walked away and took a very long coffee break. According to the Protel people that I talked to a little over a year ago, there is absolutely nothing that you can do about this one, except get up, and take a walk around the building each time it happens. I have had people make the suggestion to rename all of the nets, and I think that I may have even tried to do that, all to no avail. I have also had people tell me to turn off all on line DRC checking, but if I remember correctly, that didn't work either (or possibly it did, but left me to make such mistakes that I gave up on it). This is the one real time consuming bummer that I could never get around, and the one place where my systems would be most prone to crashing. The only answer that I have ever found was to delete all of the Polygon Planes, and always make them the last thing I do (although I do not think that that would not be the answer in your case with your 35 plane segments). I often wondered whether or not transferring all of the plane segments to a mechanical layer (or possibly just any different or unused layer) while working would allow me to skirt the problem, although every time I got to the point in the project where this became a problem, I never had the time to experiment with it. I have also wondered whether or not changing the resolution of the internal segments of the plane would have any effect, since it seems to go thru all of the small line segments of the plane and check them all, which I think is why it may take so long. This would in itself take alot of time with 35 plane segments. A faster machine is the closest I ever came to solving the problem, but even on a 2 GHz P4 with a 400 MHz bus, the problem is still there, although not as bad. This is one of those things that has even been brought up several times not only here (PEDA), but if I remember correctly, also in the DXP forums, all to no avail (Again, if I remember correctly, this is one of those posts that never gets answered by the boys down south in Oz). I know that Protel / Altium is aware of the problem in both P99 and PDXP, and I am pretty sure that they are trying to find a work-around or some other kind of fix for this in PDXP. Respecting a fix for PDXP, I would suggest that they somehow tag or otherwise identify all of the internal fill type segments of a plane on the first pass thru DRC, and then only if the plane changes (is repoured) do they have to recheck or reanalyze the whole of the segments of the internal plane. This would mean that they only have to DRC the outline of the plane against any other traces, which should be much faster (they may be doing this already). Another possible fix for PDXP would be to have a DRC mode that would go in and somehow tag or otherwise identify everything in the board that has already passed DRC, so that it would not be rechecked. Possibly the inverse of this would be more practical, in which any new additions or changes since the last DRC check would be somehow tagged or identified, and then a DRC could be run on just those items alone, so as to not recheck the entire board, which appears to be what is happening now. Yes, I still want my Service Pack 7 for Protel 99 SE, but even if they gave it to me, I don't think that there would be any improvement in this area. Respecting PDXP, I think that there should be at least some minor fixes or improvements in this area in the real SP3, if it ever gets here. Protel / Altium have taken enough time with working on the Pre-Release of SP3 and Pre-Release SP3.5 to completely rewrite the whole program from the ground up, so it will be interesting to see whether or not this works any better. It seems that whenever I or someone else really bad mouths some issue in PDXP, that it gives the people in Oz a little extra incentive to fix the problem. Maybe this will have some effect on future releases. Anyway, by the time you have read this, you will probably have completed the board, so this won't be a problem anymore, at least until the next time. JaMi - Original Message - From: Terry Creer [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, July 29, 2003 4:09 PM Subject: [PEDA] Analysing... Hi all, I've just been handed a rather large board with quite a few individual GND polygons on it (35 to be exact). I've been asked to clean it up so we can have a prototype made. Every time I make a change to the board, (ie, move track,
Re: [PEDA] Using DXP with a networked library.
Kiba This problem has been around for as long as there have been people using CAD Systems to design things. The first part of the answer to the problem is to make sure that everyone references the same Master Library, as opposed to a copy of it which may be residing on a local disk (this eliminates people using obsoleted symbols / parts). The second part of the answer to the problem is not to allow anyone to access the Master Library in anything other than read only mode, excepting the one person who is in charge of keeping the Master Library updated. I would propose that you consider something along the following lines: No one should be able to go into your Master Library at his leisure and add things, or even more worse, edit things. Make the Master Library read only, and set up an Interim Library which can be accessed by anyone, but which contains only new or edited symbols / parts, which need to be checked and approved before being added to the Master Library. New symbols / parts, or editing of existing symbols / parts (which should be accompanied with an appropriate renaming of the part (minimally with a modifier of some type added to the original name, or a totally new name)), should be done in a Local Library (local, as within the database of the design where it is needed), and then submitted to (copied into) the Interim Library for everyone's review, and then when approved they can be placed / replaced in the Master Library by the one person who has control of the it. In this scenario, all work is done in Local Libraries, and the Interim Library is only accessed for as long as people need to copy finished symbols /parts into it from their Local Lobraries (or review symbols / parts copied there by others), and the Master Library only gets accessed by the one person in charge of it, and then only long enough to add what ever needs to be added (or overwrite the old file with an updated version). A Local Library can be easily created within a design database by using the Make Library function in the Design menu. If you delete all symbols / parts from this Local Library excepting that which will become the new ones, the Local Library will be very small and only contain those items which are pending approval. An easy way to make a new symbol / part (or edit an existing one), is to place a similar symbol / part into the design from either the Master Library or the original Altium / Protel Libraries, and then create a Local Library with the Design Make Library function, and then edit that symbol / part as required, including renaming it, and then deleting the original symbol / part from the design, and replacing it with the new symbol / part. Once the symbol / part is placed into the Interim Library, and then finally into the Master Library (after approval), it may be necessary to replace the symbol / part once again with the final version from the Master Library, at which time the Local Library within the database can be deleted. Additionally, you might find it helpful to make all of your standard Altium / Protel Libraries read only (especially where they may reside on users local disks), so that they can not be edited by anyone, and set up a Master Library for your company, and copy things out of the Altium / Protel Libraries and place them into your Master Library for the company on an as you need them basis. This allows you to keep the original Libraries as delivered, and make any appropriate changes you to a symbol / part as you deem necessary for your company's uses, which may include renaming the symbol / part to meet your company's specific needs. This will also allow your company Master Library grow very quickly on an as used basis, with very little extra work. When coupled with a 'look in the Master Library first' policy, this can help create a well organized Master Library which contains only the symbols / parts you have actually used in your designs, and which by default can become your Preferred symbols / parts Library While there are many variations to the above, hopefully the it will give you some food for thought. JaMi - Original Message - From: Kiba Dempsey [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Friday, July 18, 2003 4:22 AM Subject: [PEDA] Using DXP with a networked library. Could any one give me some advice on the following problem:- I am trying to set up a library which can be used by multiple engineers. The problem arises when two engineers are working on the same library. Both engineers can open the library and add new parts, but both will find that they can not save. Is there a system which would at least warn that the library can not be edited? Regards, Kiba. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: *
[PEDA] Repost from: [dxp] Bugs situation - why upgrade to DXP?
* * * This post is in answer to a post originally posted to the DXP Tech Forum, but answered here for obvious reasons * * * Andrew, Whoa there ! ! ! Wait Just a Darn Minute There ! ! ! (He said trying to keep it clean ! ! !) Don't go giving anyone any ideas here ! ! ! It has only been a year since DXP was Officially Announced (one year ago tomorrow, see below). While DXP is offically only at SP2, it is actually currently in its eighth acknowledged (known) incarnation: 1) DXP Original Beta Prior to Release (Limited Controlled Release) . 2) DXP Original Official Release. 3) DXP SP1 Pre-Release (Limited Controlled Release). 4) DXP SP1 Official Release. 5) DXP SP2 Pre-Release (Limited Controlled Release). 6) DXP SP2 Official Release - Current Official Release. 7) DXP SP3 Pre-Release (Limited Controlled Release). 8) DXP SP3 1/2 (SP3.5) Pre-Release (SP3 Build 104) - Current Pre-Release (Limited Controlled Release). (N O T E : Based on current calculations using the current Build Number of SP3.5 and compensating for the Phase of the Day and the Time of the Moon, there can be 17 more Builds of SP3 before it actually becomes necessary to either actually release the official version of SP3, or go directly into SP4 Pre-Release (this calculation additionally compensates for the fact that it is now the middle of Winter in the land of Oz)). While it is very apparent that they (Altium) have indeed employed a lot of Programming Talent [sic] in getting DXP to where it currently stands at this point in time (Officially only SP2), it is equally apparent by examining the posts in this [DXP] forum, that not even they themselves consider that DXP is out of the actual Beta stage and into a Final Functional Product Release Form Factor yet. Look, many of us that have actually already paid for DXP are still waiting to get the signal that it has actually really and truly been transformed into a stable working product that we can use, and here you come along and try and give them ideas like the price . . . increas[ing] dramatically. Careful now, or they may get the idea that they can start charging for Service Packs, or worse yet, changing the name of DXP to yet again something else once they finally get it really working, so that they can charge all of us massive upgrade fees for the new product. I think that the operative thing to do right now is to let it be known that we are all still expectantly waiting for the actual delivery of a functional DXP Product. While DXP is 1 year old tomorrow from the announcement perspective, we are all really still waiting for it to be delivered. With respect to answering the original post by Thomas (below), which you were answering: Yes we still need and want SP7 for Protel 99 SE. JaMi ** *** BELOW COPIED FROM MY OWN PEDA ARCHIVE *** ARCHIVE ORIGINALLY POSTED JULY 21, 2002 ** - Original Message - From: Darren [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Sunday, July 21, 2002 9:05 PM Subject: [PEDA] Well, here it comes. ** *** BEGIN INSERT ** Release to the Australian Stock Exchange earlier: SYDNEY, Australia -July 22, 2002 - Altium Limited (ASX: ALU), a leading developer of Windows-based electronic design and development software, is pleased to announce there release of Protel DXP - the latest version of its Protel board-level design system. After the completion of a productive external beta release, Protel DXP was sent to manufacture last Friday. The official product launch and marketing activity is scheduled to begin early next week. Protel DXP represents a major upgrade to the Protel product line and brings a host of generational improvements delivering innovative features and technologies. It marks the beginning of a number of significant product releases from Altium scheduled for 2002103. With this next generation of the highly-successful Protel product line, Altium continues to breakdown barriers to innovation and technological advancement by providing every engineer, designer and developer with easy access to the best possible design tools. ** *** END INSERT * ** - Original Message - From: Andrew Fraser [EMAIL PROTECTED] Newsgroups: dxp To: DXP Technical Forum [EMAIL PROTECTED] Sent: Tuesday, July 08, 2003 8:04 AM Subject: Re: [dxp] Bugs situation - why upgrade to DXP? Thomas, You have to expect the price of DXP to increase dramatically as Altium have clearly employed many programmers over many months putting bugs INTO the software ;-) Sorry, that does not help you with your
[PEDA] Engineering Calculators Website
Here is an interesting website that some might find useful to bookmark: === http://www.sciencegems.com/HSG/RefCalculators4.html JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CORRECTION: CAREER OPPORTUNITY FOR SENIOR PCB DESIGNER
Ron, I did not respond to your original post below, since I am a little too far away for the commute, living in Pasadena in the LA Area. The thought has occurred to me though that from time to time you my get snowed under and need a little overflow support, and as I have my own Protel 99 SE and Protel DXP Licenses, and am not too far away for an occasional meeting or conference, I thought I would let you know that I am available for such work. Additionally, I can perform independant design reviews on your Schematics and / or PCBs, if you ever want a fresh set of eyes to look things over, all of course under any non-disclosure agreement that you may deem necessary. Thanks for the consideration, JaMi Smith CID 626.449.4242 [EMAIL PROTECTED] - Original Message - From: Website Visitor [EMAIL PROTECTED] To: proteledaforum [EMAIL PROTECTED] Sent: Tuesday, May 27, 2003 10:32 AM Subject: [PEDA] CORRECTION: CAREER OPPORTUNITY FOR SENIOR PCB DESIGNER San Diego North County Must be well Experienced using Protel Design Packages Must have Strong Electronics Background Have Management and Team Leading Experience Be Familiar with Drafting and Design Standards Salary Commensurate with Experience and Ability --- Send inquiries to: [EMAIL PROTECTED] Posted from Association web site by: Ron Beales * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP
That's odd, I thought Techserv was in CA, not OZ . . . : - ) - Original Message - From: Steve Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 10:41 AM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP The Great and Powerful OZ has spoken. Regards, Steve Smith Product Engineer Staco Energy Products Co. Web Site: www.stacoenergy.com -Original Message- From: Forum Administrator [mailto:[EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 12:49 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP For the record, this forum is dedicated to discussion of ALL versions of Protel software as well as EDA design issues and EDA software from other vendors. ~ ~ ~ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel EDA Forum... was adjacent component placement D XP
I've got a question on Wrico Pens and Linen . . . : - ) - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 7:33 AM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placement D XP Personally, I don't mind seeing questions about DXP on this list. It's good to know what the issues are with DXP, because it gives insight as to how mature (or immature) DXP is, and if it's worth upgrading to. I can't answer any DXP questions because I don't have it, but I at least want to know of what others are suffering (or triumphing) through. That also goes for older versions: 98, 3.X, 2.X, Autotrax, etc. All Protel is fair game here, IMO. And conversion issues (Orcad, PADS, etc.) too. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Cc: [EMAIL PROTECTED]; [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 8:56 AM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placement D XP Mr Morgan, Since when is this the Protel 99SE list? For your future information, this is the Protel EDA Forum, as clearly and explicity stated in the footer appended to each and every list message, and kindly maintained by Techserv, Inc for the quasi-public dissemination of issues related to any and all versions of Protel EDA software, including, but not limited to P99SE...AND DXP. I think I speak for a portion of this list (though clearly not all) when I say that I would appreciate it if you would attempt to remember this before spouting off erroneous garbage like the bull sheisa you post below. In any case, I speak for myself. Finally, I want to be clear to Dr Roberts that this is not the exclusive territory of P99SE users, and Dr Roberts is welcome to post queries or otherwise participate in this forum as she likes. As Jason indicated, there is another forum, sponsored by Altium, which is dedicated to DXP, but I feel the need to attempt to un-obfuscate the distinction between these forums. Altium's is one which is a quarantined, corporate sponsored list, with all of the implications that go with that status. Techserv's is an open user's forum for ANY and ALL Protel EDA products, regardless of any ignornat comments made by it's novice or jaded participants. thank you, Andrew Jenkins -Original Message- From: Jason Morgan [mailto:[EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 4:46 AM To: 'Protel EDA Forum' Firstly you posted to the wrong list, this list is for Protel 99se, and not DXP, there is a separate list for DXP issues, see http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Orcad Library Importing
Rob, A quich look at the Parallel Systems site shows that the freebie Orchad Lite from them is only for UK distribution (and a few other places), but does not includ the US. Following their link to Cadence, yields nothing in terms of Orcad Lite. I have looked before for such a demo for Orcad, and not been able to find one. Can you offer any other suggestions on how to obtain the demo? Thanks, JaMi - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 1:32 AM Subject: Re: [PEDA] Orcad Library Importing If you ask Parallel Systems (www.parallel-systems.co.uk) very nicely they might send you a free Orcad Lite disc. The Orcad Capture on that is free licence and seems to do most things that the full version does. Rob Wojciech Oborski [EMAIL PROTECTED]To: Protel EDA Forum [EMAIL PROTECTED] ice.pl cc: Subject: Re: [PEDA] Orcad Library Importing 09-Jul-2003 08:18 AM Please respond to Protel EDA Forum Terry Creer wrote: Hi all, Just got a few schematics and a library in Orcad format from the Atmel website. The schematics load ok (minus the parts in the .lib file), but when I try to load the lib file, Protel (99SE) tells me DECOMP.EXE must be in the path when trying to imort Orcad libraries. Any ideas where I can aquire this DECOMP.EXE? Terry, There is an article at Premier EDA Solutions's site Migrating data from OrCAD SDT/386+ that explains all necessary deails: http://www.eda.co.uk/download/orcadrev2.pdf Decomp.exe is OrCad's utility - part of OrCad SDT III/IV package. I'm not sure whether it's available as a standalone software. It is used to convert OrCad libraries form binary format to ascii. I still have OrCad IV installed on my computer so I may convert the library for you - just send it offline. Some time ago we moved from OrCad IV to Protel and I converted several old projects. My experience is that going through OrCad Capture as a transfer tool produces much better results than importing directly from OrCad SDT. The only problem is that you need an access to OrCad Capture. I used to have such an access and it was great - it saved me a lot of post-import cleaning. Wojciech Oborski * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel EDA Forum... was adjacent component placement D XP
I have a couple of Toshiba T1000's (and Toshiba MS-DOS 3.30) that might work with it . . . - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 12:36 PM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placement D XP I've got a question on Wrico Pens and Linen . . . : - ) Well, as long as we're going off the deep end, I have an old Toshiba P351 (circa 1986) 24-pin dot matrix printer (wide carriage) that still works great. ~ ~ ~ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP
OH . . . OK - Original Message - From: Jeff Adolphs [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 12:42 PM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP Oh yea! There's a lot of OZ type people in CA. Jeff Adolphs Westerville, OH -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 3:13 PM To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP That's odd, I thought Techserv was in CA, not OZ . . . : - ) - Original Message - From: Steve Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 10:41 AM Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP The Great and Powerful OZ has spoken. Regards, Steve Smith Product Engineer Staco Energy Products Co. Web Site: www.stacoenergy.com -Original Message- From: Forum Administrator [mailto:[EMAIL PROTECTED] Sent: Wednesday, July 09, 2003 12:49 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel EDA Forum... was adjacent component placeme nt D XP For the record, this forum is dedicated to discussion of ALL versions of Protel software as well as EDA design issues and EDA software from other vendors. ~ ~ ~ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Win2K SP4 and P99SE - Clarified
Brian and the forum, I did a little more digginh in my own archives on my own system, and have tracked down the original posts that I was thinking about, and they were from the DXP Technical Forum, and concerning DXP and not Protel 99 SE. For the benefit of those that might not have access to the DXP Forum, I will incorporate those posts here below. I have asked for clarification of the issue from Altium in the DXP forum, and they may in fact clear up the issue as regards DXP. his does not therefore seem to be a problem with Protel 00 SE. JaMi * * * BEGIN MESSAGE INCORPORATION * * * - Original Message - From: [EMAIL PROTECTED] To: DXP Technical Forum [EMAIL PROTECTED] Sent: Wednesday, March 26, 2003 10:58 AM Subject: [dxp] Re: Problems with Win2k and DXP ?? Hi I had the same problem. The solution in my case was: I uninstall the protel dxp and then UNINSTALL THE SERVICE PACK 3 FROM WINDOWS 2000. Then I'd install the Service Pack 2 (two!!!) from Windows 2000 and then the Protel dxp. I've got asked the Protel support, and they means, that dxp only works properly with service pack 2 of windows 2000 (and of course with windows xp). But my system is running now.. greetings C. Veronesi --- C. Veronesi E-CAD Designer Feller AG CH-8810 Horgen --- Original message BlankI've tried running the DXP SP2 trial release (looking at upgrading from 98SE) on Win2K SP3 and seem to be seeing some strange behaviour. Can any tell me if they see the same thing. The problem is that when I open the one of the examples (eg LCD Controller) and try to look at the parts library tab I don't see any scollbar on the right edge of the dialog box for any on the list windows in the dialog box. Wondering if this is a Win2K problem (running XP controls in Win2k) or something else ?? Linas * * * END MESSAGE INCORPORATION * * * - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, July 05, 2003 12:56 AM Subject: Re: [PEDA] Win2K SP4 and P99SE I've been using SP3 with 99se without problem. However, it was these past mentioned potential problems which are making me tread carefully here. I successfully upgraded 2 of my workstations, I am now attempting my server, where my network license of 99se runs, after doing a full image backup just in case. I'll report how it goes. Brian Guralnick - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Friday, July 04, 2003 2:31 PM Subject: Re: [PEDA] Win2K SP4 and P99SE Brad, Brian, and the List, I seem to remember seeing some posts about some real bigtime problems with SP3 of Win2K, but cannot remember if it was with Protel 99 SE or with Protel DXP, although I think that it may have been DXP. Does anyone have any updates on this issue, and whether or not these problems are still there in SP4? I am still running SP2 on both my Laptop and Desktop, and do not want to upgrade untill this issue is resolved. Thanks, JaMi * * * * * * - Original Message - From: Brad Velander [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, July 04, 2003 8:43 AM Subject: Re: [PEDA] Win2K SP4 and P99SE Brian, I believe that I am running W2000 SP4 without any problems. Can't tell you for absolute sure but I see (SP4) when I check my installed programs and look at the most recent hotfixes. I sort of expected it to show me SP4 installed but the only sign I could see are a bunch of Pre-SP4 and Sp4 suffixes on a bunch of M$ Hot Fix entries. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Friday, July 04, 2003 6:40 AM To: Protel EDA Forum Subject: [PEDA] Win2K SP4 and P99SE Before I install Win2K SP4, has anyone here already done it? Any Protel headaches? Thx. Brian Guralnick [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Win2K SP4 and P99SE
Brad, Brian, and the List, I seem to remember seeing some posts about some real bigtime problems with SP3 of Win2K, but cannot remember if it was with Protel 99 SE or with Protel DXP, although I think that it may have been DXP. Does anyone have any updates on this issue, and whether or not these problems are still there in SP4? I am still running SP2 on both my Laptop and Desktop, and do not want to upgrade untill this issue is resolved. Thanks, JaMi * * * * * * - Original Message - From: Brad Velander [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, July 04, 2003 8:43 AM Subject: Re: [PEDA] Win2K SP4 and P99SE Brian, I believe that I am running W2000 SP4 without any problems. Can't tell you for absolute sure but I see (SP4) when I check my installed programs and look at the most recent hotfixes. I sort of expected it to show me SP4 installed but the only sign I could see are a bunch of Pre-SP4 and Sp4 suffixes on a bunch of M$ Hot Fix entries. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Friday, July 04, 2003 6:40 AM To: Protel EDA Forum Subject: [PEDA] Win2K SP4 and P99SE Before I install Win2K SP4, has anyone here already done it? Any Protel headaches? Thx. Brian Guralnick [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OrCad to Protel
It's documented right there in the vaporware manual, along with all of the other undocumented features. ;-) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99 SE SDK
Nathan, As pointed out in all of the parallel responses to your post, The Protel 99 SE SDK does in fact require Delphi 5 to compile. You can occasionally find a copy of Delphi 5 on Ebay, but just make sure you get what you pay for (i.e.: it may be a bootleg copy). While I understand that the SDK will work with the Standard Version, from what I understand you probably will want to go with at least the Professional Version for the extra database capability. In response to the question that you might ask next, I have already asked Altium if they could recompile the SDK modules to be able to work with D6 or D7, and the answer they gave me was no. As a short term fix, you might want to ask one of the people here on the forum who does have Delphi 5, whether they could compile the your code for you. In fact, since Protel 99 SE does not appear to be fully supported by Altium any longer, and in view of the difficulty of finding Delphi 5 (which is not even available from Borland) it might be nice to know who among us has the capability to compile SDK servers which could be of general use to the Protel 99 SE comunity. In the event that you (or anyone else for that matter) are in fact going to try and track down your own copy of Delphi 5, either from Ebay, or somewhere else, you might be interested in the following link to the Borland site which has their older versions of Delphi documentation, which is itself is still available at this time, but who knows for how long. I myself have downloaded all of the different versions available for the different editions of Delphi 5 just to have them available if I do ever need them, since they will probably not be maintained on the Borland site forever. There is a ton and a half of Delphi 5 documentation here for the different editions, but you (or others) might still find it worthwhile to download it all and back it all off to a CD ROM, just to have it in the event you need it. The link is: === http://info.borland.com/techpubs/delphi/ JaMi * * * * * * - Original Message - From: Nathan Horsfield [EMAIL PROTECTED] To: [EMAIL PROTECTED]; [EMAIL PROTECTED] Sent: Sunday, June 22, 2003 5:29 PM Subject: [PEDA] Protel 99 SE SDK Good Morning All, Currently trying to create some servers using the Server Development Kit unfortunately I cannot get it to compile correctly under Delphi 6 or 7. Comes back with bad file format for the protel include files crtsl50 and protelcomponents50. Any ideas on how to compile this correctly?? Thanks -- Nathan Horsfield Inspiration Technology P/L Ph: +61 8 8211 9668 Fax: +61 8 8211 9658 www.instech.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Dennis, Please see below. JaMi - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 4:30 PM Subject: Re: [PEDA] eight-layer stackup you just use a via and short track in the component footprint design and then run update free primitives (yes i know they are not 'free') it works no drc probs You are right, this does in fact work fine, and in fact is pretty close to what I do normally anyway. I normally use one separate component for the BGA pad pattern footprint, and then make a second component that contains all of the dogbone traces and vias and all of what I call the BGA escape routing, which is all of the inner routing on the different layers out to the edge of the BGA. I keep all of the escape routing intact in its own component, which is placed in the design directly on top of the BGA component footprint (with free primitives updated)until I have everything in the area of the BGA routed exactly the way I want it. This allows me to easily edit the routing internal to the perimeter of the BGA in the Component Editor, and use Update PCB and then as you point out, use the update free primitives. Once I get everything the way I like it, I then release all of the primitives of the second component into the design, and then all of the traces and vias become part of the design. Using your methodology, I would just keep the dogbone traces and the vias as part of my first component, rather then the second component which I release. For that matter, I could just keep everything from my normal first BGA component and my second routing component, all in one component, and never release any it, and just keep updating free primitives as I go along. I guess it is all a matter of personal preferences. I prefer to have a standard BGA pattern for a component, and have nothing attached to it in the end product, and have all of my vias and traces and routing as normal vias and traces in the end product of the board, where I can go in and change things such as width or layer or whatever one at a time just as a normal trace. This also allows me to do things like highlight a net all the way to the BGA pad, and get the full length of the net in the netlist report. Most importantly, this method allows me to end up with a PCB that does not have any non standard little hidden tricks in it that may not be seen by the next person down the line to work on the board, or even forgotten by me the next time I have to come back in a year or two and work on the design again. In this sense, I would prefer to have the DRC errors showing right out there in plain sight where they can be seen for what they are. My whole point in this post and the earlier post where I discussed this DRC error issue (see the thread on subject quick question on last Saturday (5/31/03)) is simply that sometimes Protel DRC errors really are not errors at all, and I would like a way to handle them. Certainly there are ways to do tricks to make the little iridescent glow go away, but in some cases I just learn to live with them. I personally would rather have a Protel DRC error glowing here and there (which I can simply reset so I do not have to look at them) in the design, than have to play tricks here and there and do some non standard thing to make the DRC happy. I would rather have the DRC error, which anyone could see was not a real error anyway, then have to jump thru the update free primitives hoop on the finished design that gets released to production and sent down the road to the next designer who may work on the design a few years from now after I am gone. There is just something that bugs me about having to play tricks in a design to make a screwed up piece of software happy, especially when the screwed up piece of software in wrong half the time when it comes to DRC errors anyway. am i on the same page as this discussion or maybe i have missed something? Yep. You are in fact on the exact same page. ds JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Julian, Please see below, JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 6:00 PM Subject: Re: [PEDA] eight-layer stackup Jami, you missed a few important points. Generating a netlist and loading it into your PCB is not hard to do. It is a few more mouse clicks (maybe 20 seconds more work) than just hitting update. Your time is surely not that valuable, is it?? I am sure that this may work, but I was not thinking along those lines primarily since the last big mother of a BGA board that I did was done from an OrCAD netlist, where I don't think those options were available to me. Also see below. like I said: generate a netlist - it gives you the option to generate single pin nets if you want - ie a net for every unconnected pin. load the netlist into the PCB. I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. I only would want a net on the unconnected BGA pins that I would want to connect to a via so that that connection would be accessible from the back of the PCB. Juggling the netlist to generate all the extra nets seems to me to be an extra step that is not going to be understood by the next guy who happens to have to work on the design a couple of years from now when I may not be here. Also see below. I could also solve the problem by turning off certain rule checking, but that is not the answer. By doing that, I may miss a real error. I would rather have a dogbone trace and via flagged as an error, than have to override the ability to catch another single node net that really was an error. Now, if this is not the first iteration of the PCB (ie you haven't just placed all the parts on the board, its possible some preroutes will have nets already assigned to them) And particularly if you have just changed nets around on pins, as happens with FPGAs at layout time. you need to go to the net manager in the PCB editor and unlock the primitives of the prerouted BGA, then select all the primitives. Do a global edit on selected tracks, and selected VIAS to set them all to NO NET Then lock them all again. Then, you do that update free primitives from component pads thing. Now you won't have to make up any funny rules in your PCB, and you won't have to sit there after a DRC working out what are valid shorted nets and what aren't. It's a pain, but the only way I know to update prerouted footprints properly. Using the update PCB menu item does not allow this, and so when you're working with pre-routed BGA footprints, it is a better idea to work with netlists, even if it isn't as immediately convenient. This kind of sounds like some of the things you mention here are some of the things we all may do anyway in our approach to BGA routing. In this respect see my parallel resopnse in this thread to Dennis. On the other hand, juggling things around netlist wise, such as your selecting vias above and then setting them to NO NET and then locking them, seems like much more than I want to get into. I don't ever want to have to manually edit any net in the netlist or in the design. To me the netlist is sacred, and I never want to have to diddle around with it. That is my on real baseline in the design that I personally feel should never be touched. Getting back to Michael's original question in this thread: DRC ... is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC?, I simply stated that I didn't think that there was an easy way to do it short of putting them on the schematic. What I should have said, and what I really meant, was that I didn't think that there was an easy way to do it short of putting them on the schematic, without playing tricks on Protel or having to do anything non standard. I have a very strong aversion to having to do anything non standard in Protel, just to get things done and acceptable to Protel DRC. As discussed in your other post on Saturday, Protel DRC is not always right. Yes, there have been times that I have had to explain to someone that something really was not an error, simply because Protel thought it was an error (the error discussed in your other thread on Saturday regarding a trace crossing a split in an unrelated plane is a perfect example). Yes, there is a matter of personal pride in doing a design in Protel that has no DRC errors. I would rather have the DRC error, which to anyone is obviously really not an error anyway, than to have to have something in the final design that could possibly be missed or not understood by the next guy to work on the project. This is why I brought up the issue in the other post as to the acceptability of certain DRC errors. - As for my board (not
Re: [PEDA] eight-layer stackup
Julian, Please see below. JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 1:28 AM Subject: Re: [PEDA] eight-layer stackup From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. You have kind of lost me here on this one. It appears that no matter what you do you have to go back and screw around with the schematic somehow so that you can actually get a real live net in the netlist that will represent the little dogbone trace and the via. It also sounds like I have to have make a rule to allow a single pin net, and then actually put that connection into the schematic that would become a single pin net. Kinda sounds just about like I said but without the testpoint. Why on earth would I not want to keep synchronization intact? All in all, it sounds like I am doing more work and asking for more problems then necessary, and then opening the door for some real errors to sneak in undetected. Once again, I would rather have the little DRC error starring me in the face. At least this way I would not miss any other errors due to the fact that I was tricking Protel. I would still like to see a Protel 99 SE server to handle DRC errors like I discussed in my post to you regarding your split plane problem earlier this week, and I would like to see Protel DXP incorporate the solution to the issue that I discussed. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) I'd first like to thank John Haddy and Tom Reineking for the very important points that they both brought up along this line in there related responses to your post. I have spent too many hours out on an FCC OATS (Open Area Test Site) or in an Screen Room or Anacoic Chamber trying to track down EMC / Signal Integrity problems in equipment that I was trying to get certified for FCC or CISPR (or even CTIC) compliance requirements to let this one slide by. It has been my experience that a majority of the emissions problems I have ever seen can be tracked down to a high speed signal or clock line that has crossed a split in a plane. In addition to the reflection issue that was brought up by Tom, there is an even worse problem that has not been discussed. Simply stated, any signal that is traveling along a conductor over a plane will generate currents in the plane that are a mirror of those in the conductor. When you cross a gap in between two different planes, you will generate seperate currents in both of those planes. Those two different currents in each of the two planes will then travel throughout those two planes until they get to a common point and where they can cancel each other out. This may mean that they will travel to a common point on the board to cancel, or it may mean that they will travel all the way back to the power supply to cancel. Whatever the case, these currents will have to travel throughout the planes, affecting everything that is connected to the planes, until they can cancel. While decoupling caps will help the problem somewhat, they will not eliminate it. This is referred to as infecting the planes and supplies with noise. Once you get this noise into a plane or power supply, it gets into everything, and there is no way to get rid of it. The only way to get this kind of noise out of a plane or supply is to keep it out of the plane or supply in the first place. Period. That is why rule number one in PCB Design is to never ever under any circumstance cross a split in a plane with a signal. Period. Rule number two is to never ever forget about or ignore or violate rule number one. I don't care what any of the so called experts have to say on this issue, you simply should not do it. This is such a fundamental rule in the industry that even Protel has this one down right, and will flag this as a DRC error. Respecting your comment that you are the person (who got his
Re: [PEDA] Mechanical symbol?
Natalie, While some prefer to do something like that in another package, such as AutoCad, there are those that like to do it here in Protel 99 SE I know a number of people wo use one of the mechanical Layers as a PWB Detail (Fab Dwg), by putting on a Border and Title Block and Standard Notes, and just using that as the startup template for any new board. When you use the PCB Wizard in Protel 99 SE to create a new job (after creating a new file, rightclick on the background in your main window of your new .ddb and select New . . . and then select the Wizards Tab and then doubleclick on Printed Circuit Board Wizard), the Wizard itself uses templates to generate a new PCB document for you. These templates are stored in a database called templates.ddb located in your Program Files\Design Explorer 99 SE\System directory. You can modify an existing template to suit your needs, or make a new one of your own. I can't remember all of the details involved in setting up your own template, but possibly others in the forum can help you there. The only thing you I would say that you have to watch out for here is the size of the negatives since your board shop might generate film the size of your complete drawing and charge you for it if you have that layer turned on when you generate your Gerbers. Hope that this is of some help. JaMi * * * * * * * * * - Original Message - From: Natalie DeGennaro [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Sent: Thursday, May 29, 2003 10:16 AM Subject: [PEDA] Mechanical symbol? Hi, I am a newbie to this group, having just started learning Protel DXP. But I am a senior designer having used other software. I would like to make my fabrication notes (and possibly my fab drawing title block) into a symbol I can call in on every board. Is this possible on this software? From what I read in the Help section, all components have to have a pin definition in them. I don't want pins, I just want dummy text and lines in the shape of a Titleblock and notes. Is this possible? I can make a DXF file to do this but I would rather have a symbol to call in. Thanks for all help, Natalie [EMAIL PROTECTED] 04/22/03 06:36 AM To: [EMAIL PROTECTED]@Internet cc: (bcc: Natalie DeGennaro/Americas/NSC) Subject:Re: [PEDA] Import PCB Leo- May be that the Gerbers are RS274 rather than RS274X. For RS274, Protel needs to have the Aperture file loaded before importing the Gerbers themselvesotherwise, you get a black screen after the Gerber load. Aperture list must be in the bundle if Camtastic is finding it, tho the file extension may not be .apt. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
MichaelB, While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. Myself, I have had the very same problem with the identical requirements (needing to take each BGA contact to the back of the board with a via), and I just live with the errors. I have accepted the fact that even if I were to do a perfect board in Protel 99 SE, that there would still be some little DRC error somewhere. Protel DRC just doesn't map to reality in all cases, as there is always some need for some special requirement that Protel just can't handle, so you look at the DRC error, and accept it as is, and live with the error in the report file and that little iridescent glow here and there on the on the screen. I find that the trick for me is to reset the errors once I have examined them, and that way they are not just sitting there staring me in the face as I continue working on the design. Respecting the layer stack up, I myself would prefer to go with 2 outer routing layers, 2 planes under that on each side, and then another 2 routing layers in the middle. But before you even get that far, I think that you need to ask whether any of the signals may have any special requirements, such as controlled impedance, or matched lengths, or isolation, or the necessity to be routed over a specific plane. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. It may well be that due to the type of signals you are dealing with (LVDS / high speed / controlled impedance / susceptible to crosstalk), you might have to go with isolating the internal signal routing layers as layers 3 and 6 with the two power layers as 4 and 5. What type and size of BGA are you dealing with? Any special routing requirements? JaMi * * * * * * * * * - Original Message - From: Michael Biggs [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:20 PM Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Earth to PEDA
Earth to PEDA . . . Earth to PEDA . . . What's the story on the lightning fast turnaround on the Forum distribution . . . JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mechanical symbol?
Natalie, Wasn't till I got a copy of my own post back that I realized you were talking about Protel DXP as opposed to Protel 99 SE. I am asleep at the switch today, and assumed that because you posted to the Protel List instead of the DXP List that you were talking about Protel 99 SE, and read the DXP in your post as DXF. Sorry about that. Notwithstanding my blunder, I believe that everything I said below is also applicable to Protel DXP, with the exception that the templates.ddb file will now be located in the \Program Files\Altium\System directory. If you are not aware of the DXP Technical Forum, you can find it at: == http://forums.altium.com . JaMi - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Monday, June 02, 2003 5:58 PM Subject: Re: [PEDA] Mechanical symbol? Natalie, While some prefer to do something like that in another package, such as AutoCad, there are those that like to do it here in Protel 99 SE I know a number of people wo use one of the mechanical Layers as a PWB Detail (Fab Dwg), by putting on a Border and Title Block and Standard Notes, and just using that as the startup template for any new board. When you use the PCB Wizard in Protel 99 SE to create a new job (after creating a new file, rightclick on the background in your main window of your new .ddb and select New . . . and then select the Wizards Tab and then doubleclick on Printed Circuit Board Wizard), the Wizard itself uses templates to generate a new PCB document for you. These templates are stored in a database called templates.ddb located in your Program Files\Design Explorer 99 SE\System directory. You can modify an existing template to suit your needs, or make a new one of your own. I can't remember all of the details involved in setting up your own template, but possibly others in the forum can help you there. The only thing you I would say that you have to watch out for here is the size of the negatives since your board shop might generate film the size of your complete drawing and charge you for it if you have that layer turned on when you generate your Gerbers. Hope that this is of some help. JaMi * * * * * * * * * - Original Message - From: Natalie DeGennaro [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Sent: Thursday, May 29, 2003 10:16 AM Subject: [PEDA] Mechanical symbol? Hi, I am a newbie to this group, having just started learning Protel DXP. But I am a senior designer having used other software. I would like to make my fabrication notes (and possibly my fab drawing title block) into a symbol I can call in on every board. Is this possible on this software? From what I read in the Help section, all components have to have a pin definition in them. I don't want pins, I just want dummy text and lines in the shape of a Titleblock and notes. Is this possible? I can make a DXF file to do this but I would rather have a symbol to call in. Thanks for all help, Natalie * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] quick question
Julian, Went thru both of your emails (spliced below) trying to figure out exactly what you were describing, and the best that I can come up with goes like this: 1.) You have two split planes adjacent to each other on the same layer; and 2.) You have one hole placed directly in the gap between the two planes (or minimally directly on the edge of one of the planes), and 3.) That hole is electrically connected to one of the planes, and 4.) That hole has a thermal relief defined for its connection to the plane. If I am understanding this correctly, this would have probably resulted in the spokes of the thermal relief shorting both planes. If this is the case, I am surprised that Protel did not flag it in your DRC. It has always been one of my pet peeves with Protel in that it does not handle vias or component holes correctly when it comes to gaps in planes, since it has always been my experience that Protel seems to treat the gap as a trace when it comes to doing DRC, and ignoring the fact that it is a negative image or representation. By that I mean that whenever I have placed a via or component hole near the edge of a plane, Protel would flag a clearance error between the edges of the pads of the via or hole, and the trace, which in reality is not a copper feature at all, but simply a void, and as such should not generate a clearance violation. The reason this bugs me so much is that I did a whole series of little boards which all had the same little microcontroller circuit on them, on an isolated little island all of its own, packed in just as tight as I could get it. Due to the analog and digital separation in one corner of the chip, I had a tight little spot where I had to put a few vias right near the edge of one of the planes (although not connected to any plane). Protel would always flag this as a DRC clearance error, highlighting the gap (as if it were a trace) when in fact it was not. In light of this behavior, I am really surprised that it did not flag it (your problem) as an DRC error. Is it possible that there is an error in your DRC report file that you may have overlooked? I would think that you might want to check to see if something is turned off or set wrong in your DRC setup. Respecting whether or not it is the vendors fault, I would say that that depends on just what your gerber files told him to build. I can't think of anything that he would have done wrong, unless you are paying him to examine the design as part of the setup, and then you might have a case to say that he should have caught it. What does CAMtastic have to say about the situation? Just what do the gerbers really look like. In view of the fact that it has been a common rule of thumb in the industry now for many many years that you should never put a via in a gap between planes, I would vote on the side of the vendor and recite the Toyota Slogan to you, where they say you asked for it, you got it. If I remember correctly, I think that I may have seen somewhere that Protel might have even told you not to do this somewhere in their Manual or Tutorials. If this were to be called a bug, I would say that it is only a small part of a bigger overall problem that Protel has in dealing with gaps in planes and DRC errors. I wonder if this been fixed or at least improved in DXP (I may be able to import one of my older designs and see how DXP responds to it, DRC wise, but that may not really tell anything since I have only installed SP2 so far. An example of another problem with the way Protel handles gaps in planes and DRC, is the following: 1.) Take a 6 layer board, with all of your signal traces on the outer layers 1 and 6; and 2.) A solid ground plane on layers 2 and 5; and 3.) multiple little split plane patterns for power on layers 4 and 5. This is exactly the way that I laid out my last Xilink Vertex II BGA board, in 6 layers (2 routing, 2 ground, and 2 power) with a total of 23 different little split plane segments. In the above example, if I run a long signal trace on layer 1 (or 6) from one end of the board to the other, it will always have a solid ground plane directly beneath it on layer 2 (or 5). But, and here's the problem, the trace may in fact cross several gaps in the inner planes on layers 3 and 4 (which are physically and electrically NOT related to the signals on layer 1 (or 6)). Nevertheless, Protel insists on flagging all of these signal traces as errors, since they cross an unrelated gap in an unrelated inner plane. In the above example, there are those that would argue both sides of the issue as to whether or not Protel was right in calling it a DRC error. While I would not argue one way or the other on this one, I bring it up because it is a perfect example to show how Protel really does not know how to really handle the issue of gaps in split planes. Here again, some might argue that it is not really Protel's responsibility to really understand the issue or say what is or is not an error, but
Re: [PEDA] Seperate Systems - was Roxio, Nero, Virii and crashes
Ivan, While there certainly are reasonable limitations and exceptions, burning a CD is certainly not something that can generally be done at the same time while you are multitasking and designing a board with Protel, or even writing code, and is in fact somehting you could very easily do on at least 2 of the other 4 machines you have available right there at your desk, while you continued to work on your work machine. Certainly there may be other cad tasks that are best shared on your work machine, but not very much of an arguement can be made to say that burning CD's, for whatever reason, is one of them, especially when it is with the software under discussion as being the problem in the original posts. The primary point of my original post was to raise awareness of peoples investment in their Protel Machine / Toolbox, so as to prevent problems by needlessly trying to multitask on that machine where certain tasks, such as burning a CD, can be done so easily elsewhere. There really is no reason to invite problems on your Protel Machine /Toolbox when you do not have to. Thanks, JaMi - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, March 18, 2003 7:15 AM Subject: Re: [PEDA] Seperate Systems - was Roxio, Nero, Virii and crashes JaMi: While using a separate PC for each application will certainly reduce conflicts, it should not be necessary. You see, there is this concept called multitasking - check it out! ;-) I burn CDs on my Protel workstation too. And I'm not talking about MP3 CDs. I burn CDs of our hardware drivers for our customers. So it's entirely work-related CD burning activity. That's just as important as running Protel. I already have 5 PCs (Linux server, linux client, W2K workstation, W95 miscellaneous, and a DOS/W95 hackbox) on/under/beside my desk anyway. No way I'm going to add yet another PC just to run one program which should get along with other programs anyway. I could afford to buy another PC. I just can't stand any more clutter. Behind my desk looks like an explosion in a cable factory. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
