Re: [PEDA] DXP and FPGAs
[EMAIL PROTECTED] wrote: We have DXP with all of the options except IP processors, including fpga support, but no Nanoboard. My need is to build simple logic block replacement fpgas, and insert them into pcb designs. The current fpga is an Altera EPM3128A. Made it through the schematic and pcb phases, including a schematic of the fpga functions. I was under the impression that at this point DXP would use the fpga schematic to generate a VHDL file that I could compile with the appropriate Altera software. When I go to ToolsConvertGenerate VHDL From Part, andclick on thefpga symbol in the schematic, it generates a VHDL file with only entries for the control signal pins. My call to phone support ended with the explanation that the user is supposed to fill in the details of the logic in this VHDL file and compile it manually. The examples in the manual (using the Nanoboard) certainly indicate that there is some sort of automatic file and compilation going on. Am I missing more than just the physical Nanoboard, like additional software? If DXP won't generate the VHDL file from the fpga schematic, what is the point of generating it in the first place? It seems that I could just start with the Altera software. Any help would be seriously appreciated. I can't help with DXP specific info, but I have done this with P99SE. You ouput a netlist from the schematic, and select VHDL as the net list format. (I had to massage the netlist a little bit to make it compatible with Xilinx's VHDL compiler, but I did get it to work. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Negative Film Output
Jeff Stout wrote: How do I create negative film output? And why can't Protel do this right out of the box? I want to use a home PCB kit to create a simple PCB and I need negative film. I once heard of a method of printing to pdf then hand editing the output to create that effect. But nothing clicked for me when I looked at the pdf output a few minutes ago. If you have a PostScript printer, you should be able to find, under advanced, then PostScript Options settings to mirror and print in negative. This is in the print options menu. But, I think you'll find the results pretty poor. Laser printers (and most others) have problems with the paper not tracking straight through, and the lasers have tricky optics to linearize the optical path, but it isn't perfect. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Mike Reagan wrote: Jon You are probably correct about SELECT ALL WIRES not working Try select all nets.This is was a carry over from using SPECTRA. Sorry about my memory lapse Thanks, that fixed that error message, but I still get the incomplete command with the UNSELECT CLASSS ( ) And, the board doesn't route real well with these settings, about 73% and what it has laid down binds up its ability to route the rest. This is a real simple board with 3 68-pin connectors and 65 nets. It has somewhat of a routing channel restriction, but the Protel default router was able to do 100% of it right off. (It made a hell of a mess of it, though.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Electra router
Mike Reagan wrote: Dennis wrote: here is the link to the article by Mike re Electra tip http://www.connecteda.com/doc/Autorouting%20Techniques.pdf Thanks, how come I could not find this document myself on the Electra web pages? I have tried this, and I do get different results, but still nothing good. I get two error messages from Electra about the commands in the DO file from Mike's white paper. For the line SELECT ALL WIRES Electra says unknown command. FOR THE LINE UNSELECT CLASSS ( ) I GET inclomplete command whether I use CLASSS (verbatim from white paper) or CLASS. (I'm still using Protel 99SE, if that makes any difference.) Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE memory errors
Jeff Adolphs wrote: Hi! I am getting memory error when I click on print preview from the pcb layout. I have uninstalled Protel 99SE and reinstalled with Sevice Pack 6. I have Windows 2000 and 1/2 gig of RAM. Protel 99SE has worked well for a long time on my current machine. Could the latest Window updates be causing Protel 99SE to no longer run? Additionally I have repaired the database and still get Protel crashing. You might do well to run a memory test program on the computer. This doesn't sound like a software problem. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] time to upgrade 99SE? / Electra router
I finally downloaded the Electra router and tried it on a board I had just routed with the P99SE default router. I thought Protel did badly, but the Electra board was a nightmare. It wasn't even able to complete all the nets, it left about 5 undone. Protel made a fair jumble of traces all over the place, but Electra literally filled the entire area within the keepout border with tracks! I can't say for sure whether I had all the settings right (actually, I haven't found anywhere in Electra to set options, etc.) so I'm not sure this is a good comparison, yet, but so far I'm not very impressed, to say the least. Since this was discussed a while ago, I thought I would give a report. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE layout question
Daniel Weiss wrote: Hi The 99SE PCB layout program seems to *not* DRC a power supply layer. I am asking on behalf of our layout man, is there a way to have it do a proper DRC on power layers as well? It happend to us that two power supplies got shorted because the gap width between them was inadvertently set to zero. It does do a check on power layers, but there is a deficiency in the algorithm when it comes to holes that are partially in the border between split plane regions. Normally, I think you DO get some kind of complaint if split plane regions OVERLAP, but maybe the same problem occurs when the regions are extremely close. I think it is pretty well known that the handling of through holes connecting to split planes is not 100% airtight, and so you have to watch out for design practices that allow you to fall into these traps. (Been there, done that a few times, myself.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] tests for Pb in solder
Bagotronix Tech Support wrote: Hello, all: I was wondering if there are any easy, quick tests to determine if solder has lead (Pb) in it, and what the approximate concentration might be. I don't need a quantitative lab analysis, just a yes/no. A vendor told me yesterday that their process has been lead-free for over a year now. Then when I said that I don't want a lead-free process, they had their process engineer call me back later and say that they don't use lead-free processes. So I am wondering if the first guy made an honest mistake (he's not technical), or if they are switching their story to cover up something. You can buy lead test swabs for checking paint in your house at the local hardware store. I think they turn red if Lead is present. I don't know if they only detect the lead compound used in paint, or any lead, including elemental lead alloyed with other metals. But, the kit is pretty cheap, and you should be able to try it with solder still on a reel with a label, so you can verify what it detects. Personally, I wish the lead-free hysteria would just go away. Lead usage in PCBs such a small percentage of total lead usage, it's not worth the Yeah, I agree! There's tons of this stuff in the environment from car batteries and Pb-containing batteries in electronic products, and they're going crazy over grams in the circuit boards, and the lead in TV tubes, that is essentially Waterford crystal, and so unlikely to leach out in significant amounts. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copy selection to layer
bob stephens wrote: Oh, no! Not false at all, I do this all the time in 99SE. Select the bunch, double click on one, global, and move it to the bottom layer. Jon Yeah, I really miss some of the features of 99SE. I find DXP/2004 a *LOT* less intuitive. Another feature I really miss is the ability to trim or shorten a PCB trace by some combination of shift/ctrl/click/drag which I forget. I can't fathom why they would get rid of this very useful feature... Well, I don't miss those features, and I don't miss the money, either! I'm still happily running 99SE, and have no intention to move up until I find a real problem that DXP (or 2004) solves. They got rid of it because the institutional memory of how it was coded is gone, I suppose. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Adobe Illustrator
RogerHead wrote: I am considering AI for designing instrument front panels. What do other people use? Our publications department people love it, but they're using it every day. I'll use it a few times a year. But I want to get away from the blocky, 'designed by an engineer' appearance - you know, front panel artwork laid out in Protel. One really cute trick is to use Protel's PCB for front panels that are going to have a PCB behind the panel, with switches, LEDs, LDCs, etc. Then, the alignment of the panel's holes and cutouts, and the labels all will line up with the PCB-mounted components. You could also export some of the PCB info in some file format to a mechanical CAD package or art program, so the PCB locations could be used as a guide for the panel labels. I have a homemade laser photoplotter that I built for PCB prototype artwork, but I also use it to make phototools to make panel labels. I use some really expensive stuff from VPC (US rep for Quick Mark) to make laminated. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Exporting to pdf or Orcad or PSpice
Trent Bates wrote: I am trying to export one of my schematics to a customer. I am using Protel 99SE SP6. The customer would like it in a pdf format or an Orcad format (.DSN file or something of the sort) or something they could read from PSpice. I tried saving one of my schematics as an Orcad .sch file but strange things happened and components went all over the place. What is the best way to export the schematic. Can Protel export to a pdf format? I think that would be the easiest. I can take screen shots but you end up loosing a lot of detail with screen shots. If I took a screen shot of the whole schematic it would look pretty fuzzy when you zoomed in once it was in pdf format. If I could export directly to pdf I could keep the detail. My system, although cumbersome, works. I output to a PostScript file, using a driver for one of the common color printers from HP, but causing it to be saved to a file. I then pull the file over to Linux and run it through ps2pdf, to convert to pdf format. I'm sure Adobe has a program that will do this all in Windows. (I run Win 2K as a guest OS under VMware, with Linux as the host OS.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Spice Simulation (V I) Probes on Schematic?
Darren wrote: Greetings. I feel that Altium Protel DXP is a wonderful program with an insane amount of configuration capabilities, and is well-thought out in terms of integrating Schematic and PCB design. However, there seems to be one important feature that either I can not figure out how to perform, or was completely overlooked by the DXP development team, and that is when doing simulations from the schematic. It seems that in the schematic editor, there is no provision for placing either voltage or current probes on the schematic as is done in many other popular schematic/simulation packages. For me, this is an extremely important feature, for fine tuning a design. Without this ability, a lot of time is spent selecting nodes from a list, especially when it is desired to display different signals each time a simulation is run. The closest it seems that Protel DXP comes to this capability, is to place net labels on the schematic, but this only allows for voltages. I can not figure how to do the same for currents, and even if it is possible, it is extremely inefficient to do it this way as opposed to just dragging a probe on to the point of interest. Spice automatically produces a current scalar for every voltage source. These are listed as something like I#brname of voltage source. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Viewing a mirrored bottom layer and other layers
bob stephens wrote: Well, I figured out a kind of crappy way to do it. In DXP you can selectively mirror Gerber layers. I turned off everything except the bottom layer and bottom overlay, both of which I mirrored and then I could look at them in Camtastic. Better than nothing. Yup, you can do this in P99SE, too. Write out the gerbers mirrored, batch import them back in, and display from the other side. But, you lose a lot of information that way. And, you might forget, and send the mirrored Gerber output to the PCB maker, who might have no way to know something was really wrong. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Viewing a mirroed bottom layer and other layers
Trent Bates wrote: I use Protel 99SE. Is it possible to view different layers and turn different layers on and off. I know that by pressing SHIFT +S, I will view only the current layer but its it possible to select which layers are being viewed. For example when looking at my top layer I would like to see the Top layer and the Top Layer overlay . Sure. There are two things that control the view. One is in options, one is in preferences. These are under the main PCB menu tabs design and then options, you can turn each layer on or off. The colors are set in tools then preferences. Also is it possible to flip the board around and view the bottom layer as if it were the top. The PCB print process allows you to do this. I use it to make back side of board assembly drawings. I don't think there's a way to view it reversed right in the PCB window. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Simulating a centre tapped inductor in 99SE.
Ian Middleton wrote: I am trying to simulate a simple passive filter circuit that has an inductor with a centre tap as one component in 99SE. Can I just simulate this as two coupled inductors, as per page 209 of 99SE handbook, with the coupling set to one (as the two inductors are wound on the same core) ? Yes, that should work. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Router comparison
Tom Robinson wrote: I remember years ago an engineer getting mad at me because I wire-wrapped his circuit trying to make it look nice and neat with all the wires bundled together in streets avenues. He said it was a big cross talk problem. He wanted point-to-point with just a little slack in the wire length. Yup, he is right. It makes rework and checking hell, but it is best electrically. Unfortunately, a wire wrap or multiwire board is N layers, with N tending toward infinity. That's a freedom you don't have on printed circuits. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Keepouts on Planes
Ray Mitchell wrote: Hello, I would like my various planes to be back 50mil from the edges of the PCB. I placed a line on the keepout layer and set my clearance constraint to 50mils. While this does keep the autorouter from placing anything closer than 50mils from the edge, when I look at the Gerbers for the various planes it appears that they go right up to the edge and ignore the keepout. What is the correct procedure? The power planes are not objects to Protel, they are a lack of object. You need to draw either a track or a fill to cut these planes back from the edges. I use a wide track that partially extends past the routed edge of the board, so the board will be cut through that track, where there won't be any copper on the power planes. The keepout just prevents the autorouter from placing components, pads or vias in that region, which is fine, as far as it goes. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] The Protel 99SE router (router?)
Tom Robinson wrote: I remember when Protel bought NeuroRoute from Gene Marsh (?) At the time, which was not that long ago, EVERYONE was saying it, NeuroRoute, was the best thing since sliced bread. What happened? They haven't figured out how to degrade it sufficiently to release it! :-) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE: 2 of every net name?
Ray Mitchell wrote: I've never seen this before. In 99SE (Win2K) I've created a schematic and am starting the PCB layout. When I double-click on a pad and look at the net attached to it, as well as all the available nets, I noticed that there are two of every net. For example, there are 2 A5 nets. Some of the A5 pads are connected to one of these nets while others are connected to the other, even though they all have the same A5 name. My manually going through all the pads and selecting, for example, the first A5 of the pair I can get all A5 pads to connect together, etc. Any ideas? Yup, this is the out-of-sync synchronizer bug. I think you want to clear the entire netlist in PCB, close all files and exit P99SE, and then re-open the DDB and files, and then try to sync again. The worst case is to clear the netlist, generate a Protel netlist in the SCH tools, and load the netlist. But clearing, closing and the re-syncing may put it all back to normal. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Complex Hierarchy to PCB layout ?
Dave C wrote: Well, I forgot to mention that I am using Protel 99SE w/SP6 version. I am sure DXP has tons of new nice features and improvements, but it is out of the question to get it for now. Although this is a one time project, I have more than a dozen identical sections, over 500 parts more or less. I get tired just thinking I have to manually rename all of these, not to mention how easy it will be to make a mistake doing that. Any other suggestions ?? There are ways to do this in 99SE. The flatten hierarchy function is part of it, but it does a rotten job of handling the component designators, which most people want to do something like R101, R201, R301 being the equivalent part in each section. You can give each part a designator that is unique enough that you can use it as a qualifier in a global replace on all sheets. I usually don't get this all set up right the first (or second, third...) time, but after a few tries I get it in such a shape that I can flatten and renumber the sections the way I want. You can also just duplicate the sheet that contains the section, and then use a global edit to change the part designators as desired. For instance, if you have the master sheet with RZ1,RZ2,QZ3, etc. and then do a global edit on section sheet 3, you replace Z with 30, and you get R301,R302,Q303, etc. I do LOTS of boards with 16 sections like this, where almost the entire board consists of these sections, and 800+ components. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE for sale?
Robert Ritchey wrote: Hi, I am looking for a 99SE license. Since I have not done this before, does anyone know what documentation Protel requires to prove to them I bought the license to qualify for future upgrades if we decide (its getting so expensive and so many features we really don't need I am not sure of this)? Thanks, I bought an Advanced PCB for Windows and adv sch for windows licenses from a guy in the Netherlands, and then contacted Protel (at the time) with a copy of the guy's original license list (it had the serial numbers and license keys on it, and a bill of sale with his and my addresses on it, and that was all they required. I was then able to use those licenses to upgrade to P99SE at a VERY substantial discount. I would think the same documents would be all they need for a straight license transfer. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] File Format Not Recognized
edsi wrote: I would be interested in how many of you this week who lost Protel file , or it quit working have AUTOMATIC UPDATES on with windows. I had the same problem this week also. The only software installed on my machine this weeek was Gates trash. Never. I have never lost a significant amount of work with Protel 99SE/SP6. Sometimes I have lost a couple of minutes of changes, tops. I have never had a whole DDB file go bad on me, and only had a couple of hangups in several years of use. But, I only use Protel 99SE, Xilinx ise, and a mechanical CAD package on the Windows system. Everything else I do is on Linux. I actually run the Windows 2000 Pro system under a virtual machine emulator under Linux, called VMware. Linux usually stays up between power failures (70+ days) and Win2K usually stays up for weeks at a time. If you have problems, it could be flaky hardware. Get a comprehensive memory test program. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic text back to front and upside down
Kathy Quinlan wrote: Hi all, When I print a schematic on my Brother HL 1440, the text is upside down and back to front. If I print a Text document it is fine. Any Ideas ?? Clearly, your printer driver is bad. See if Brother has a new driver you can download. If the printer is an emulator for some other brand (HP, Epson, etc.) try a few different drivers for the emulated brand to see if one of them corrects the problem. I once had to send a laser printer back and get a different make as the PostScript emulator in it had a defect that smashed text from a particular application. The maker admitted the problem was bad firmware in the printer, but they had no practical way to fix it. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] Synchroniser won't recognise components
Leo Potjewijd wrote: Hello. I am trying to update an existing PCB (196U passive backplane): it needs to be shorter, lose some connectors and gain two connectors of a different type. I changed the schematic (just a single sheet) to include all connectors and their interconnections (almost all of them got a new refdes); then I changed the PCB manually to add the new ones, delete the unwanted ones and renumbered them all according to the new schematic. When I run 'update PCB' the synchroniser does not recognise two (different) connectors: it claims that J7 is not on the PCB (which it is) and that J13 is not on the schematic (which it is). I checked all fields, names etc of the components in question but cannot find anything wrong. Ugh, you've de-synchronized the synchronizer. This occasionally happens when you manually change parts on the PCB and then try to synchronize. Once it happens, the synchronizer is very difficult to get working right again, although it sometimes clears itself. But, you can just go to manual means. Do a netlist generate in Protel schematic and then use the netlist load function to reset the netlist info. Then, do the netlist asssign nets to free primitives function to reset any changed net names to the tracks and vias. Then do a DRC, and everything should be up to date. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message is sent using PostCast Server Professional Trial: http://www.postcastserver.com/
Re: [PEDA] TO-220 4th pin?
Dom Bragge wrote: I just would like to ask a question about how you handle TO-220 footprints ( the like)... I have the three (electrical) pin device, that's fine. I'm placing the T)-220's flat on the board. What if I want to (selectively) put copper on the top layer under the TO-220 have a suitable soldermask antipad? This could aid in cooling without resorting to an actual heatsink. How should I best do that? Do I place on the board a free pad, rectangle, with a hole the same size as the hole for the TO-220 tab? Seems a bit ugly, two holes etc etc but it should probably give me the SMask opening. Do I make a 4pin lib part, have a 4th pin on the footprint being the large hole add a polygon connected to that net? I suppose I'll have to add an opening for the SMask on the TO-220 footprint as well. I think the special library part is the best way to do it. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autorouter
Dennis Saputelli wrote: what you say is true (good products ruined) but it is too late in other words this is the M.O. of biz today so wishing it were otherwise makes no difference Well, remember that only publicly-traded corporations can be bought out by force. A privately-held corporation that doesn't want to be bought, can't be bought. In the old days, these companies would end up having suspicious fires. But, in the current climate of high-quality forensic science, it is REALLY hard to get away with this sort of crime. Konekt.com has the feel of a privately-held outfit, but I don't know for sure. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autorouter
Bagotronix Tech Support wrote: Well, remember that only publicly-traded corporations can be bought out by force. A privately-held corporation that doesn't want to be bought, can't be bought. I wasn't commenting about whether or not they wanted to be bought. It's entirely conceivable that the owners of a legit company with a good product want to cash out. Maybe they are tired of putting in 70+ hours a week, and a good offer comes along. Oh, of course, this happens. I know a couple of people who got lucky, and were able to sell their business for fabulous sums of money. The culprits are the buyers, who in many cases, don't have the business sense that God gave to a rock. UMM, anyone we know? Like Altium? Yeah, there's a business model - create a publicly held company, managed by the business school's best graduates, and well financed by IPO. Problem is, buzzwords and marketing do not a good product/service make. These people buy the company, and then change everything that made that company a success. When you are traveling in the direction of success, you don't do a 180! Yup, the history of high-tech businesses are littered with that debris. Shugart Associates, for instance. After buying it, and throwing out the founder, they even prevented Alan Shugart from using his own name in a new venture. So, he came up with Seagate. Where's Shugart (the company) now? Kaput. Where's Seagate? One of the biggest disk drive makers in the world. But that's exactly what they do. It's like the Reverse Midas Touch, where every piece of gold they touch turns into dung. I say dung, because even base metals would have some value ;-) Yup, that's it, the reverse Midas touch, all right. There's hundreds of these stories. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using Protel 99SE with Xilinx 6.1i Project Navigator
Ray Mitchell wrote: Hello, In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome. I have done this, but it gets a bit messy. I'm not sure my method is actually any improvement. The only thing I found that worked was VHDL (architectural) netlists. An annoying bug is that P99SE Sp6 will only output one VHDL netlist, then you have to restart P99. If you don't restart P99 each time, it will hang on the netlist step. If you wait half an hour, it outputs 65536 lines of garbage before the valid netlist. But, you get a netlist almost ready for Xilinx isp. You have to manually add the library unisim and the line use unisim.vcomponents to get the use of those library components. You can edit away the _sch extension from all VHDL files made from schematic sheets. You have to manually remove duplicate component declarations for all of the user-created components. This only comes up on sheets where you have placed the same user-created library component multiple times. The rough edges are that P99 wants input and output pads on the top level page for sim and ERC, but Xilinx DOESN'T want pads, it assumes any ports on the top page are pads. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE drc
Graham Brown wrote: Hi all, merry Christmas, I have a board with an internal plane split between +5v and +30v. I inadvertently placed a via, belonging to the 30v net, right on the separating line, thereby bridging the two power nets. P99SE/SP6 did not find this during drc. Is this a limitation of Protel or of my menu-digging skills? It appears to be a bug. I've just been lucky and not had a board go out for fab with one of these, yet. If the via is totally in the wrong split plane region, it will usually cause a reliable DRC error. Sometimes, I think, it will still cause an error, depending on the exact placement of the via. Note that many board manufacturers add additional blowout around the plane regions and non-connecting through holes toimprove their yield. This is more likely to cause thin areas in planes to become isolated, or cause a single split plane to end up as two regions. But, in any case, Protel is not aware of that modification, and can't predict the results when the fabricator does that expansion. It is a pretty good idea to import the Gerbers and view them one at a time (you can gang import them and then use shift-S to see the layers individually). If you scan along the split plane boundaries, any thermal connection will be pretty obvious. Any via (or pad) that doesn't connect to either plane should have a blowout pad that just makes the gap between the plane regions bigger at that spot, so those shouldn't be a problem even if right on the boundary. But, you say your problem was a via. That normally would not have a thermal connection, just a hole drilled into the plane. If you make the border line of the planes larger than the hole diameter, then you should not get a short between planes. (You'd get a no-connect for a via centered in the gap between planes. That would at least be easier to fix.) But, this is also not easy to spot in the Gerbers, as the direct plane connects do not show at all in single layer view. I suppose you could select the power layer as the current layer, and enable only the power layer and the multilayer, display vias only, and check the borders manually. But, I think making the split plane boundary track width wider than any reasonable through hole is the best policy, and how I always do things. If both boundary tracks are .020 wide, and you don't overlap them much, you should be pretty safe. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel PCB fornat
Mike Reagan wrote: Hello All Does anyone know a source or information for the format of Protel 99SE ASCII PCB files. I intend to modify ASCII files but would like to know the real format. Gee, it is really pretty self explanatory. You can just read the files, and the word that defines what primitive is on that line tells you pretty much what it is. One of the Protel user manuals had the description of the file, field by field, in an appendix in the back. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fw: Exciting news for all users of Protel DXP and nVisage DXP
Bagotronix Tech Support wrote: Has anyone ever successfully used Protel's PLD/FPGA features with a vendor's (Xilinx, Altera, Lattice, etc.) toolsuite and gotten usable results? Was it worth the hassle? I ask because it is usually better to use the vendor's fitting, place, and route software than some 3rd party thing. I wonder if Nexar will be another Altium product that is announced to much hype, driving upgrade purchases, and then quietly dropped (remember PeakVHDL?). I'm still on P99SE/SP6, I can't imagine moving once again to a new (major) version. After three major tries, consuming several weeks each, I have actually done it! There's no reason to do HDL work in Protel at all. But, for schematic FPGA work, the Protel schematic entry is pretty good. I have to admit that the Xilinx schematic editor is better integrated with the schematic/FPGA libraries, however. But, the actual symbol and wire management of the Xilinx schematic package is so bad as to be laughable! When you get over 10 simple gates on a C size page, it starts doing wierd stuff of the you can't put a wire there, it is too close to something else sort. I like to put a lot of stuff on a few pages, rather than having 3 gates on each of 300 pages. Protel allows making some VERY dense pages. I tried making Xilinx XNF files years ago, and found that Xilinxc would not accept the XNF files, giving a fairly specific message with line numbers for the syntax error. I sent this to Protel (this predates Altium) with no response whatsoever. I tried exporting EDIF files from Protel, and this came close to working, but the EDIFs it output needed a LOT of hand editing to make them work. Way too much to make this practical, without a program to do the editing, and that program would not be real simple. Then, I discovered thet Protel99 would output a VHDL file! Is this in the manual or anywhere else? I discovered it totally by accident when scrolling through the list of supported schematic export formats. This almost works without any changes in the files at all. The only discrepancies are : 1. You need to manually add a definition and call-in the schematic symbol library, that takes 2 boiler-plate lines in every VHDL file. 2. If you have user-defined symbols that reference schematic pages, the VHDL file will have a port definition for each instance where the symbol is instantiated on your schematic page. It should only have the port definition once, just like is does correctly for symbols that come from a library. These are pretty easy to edit by hand in a few seconds. Xilinx likes the VHDL format, and generates good code from it. Errors in the schematic that produce illegal syntax or errors on translation are pretty easy to follow back to the offending schematic, although this is not seamless or automatic. The way Xilinx wants top-level pins to be defined is different from what Protel wants, so the Protel ERC is not very useful. This is a bit of extra work to go through, but the Xilinx schematic tool is **SO BAD** that it is worth it. With some fooling around, the PLD simulator is also usable, especially for checking small sections of a design. In some ways it is a lot easier to set up a very quick check graphically than Xilinx's MultiSim graft, which is a pretty ugly external grafting-on, something like the way Protel did the CCT Specctra auto-router. If anyone wants more details on this, I can provide a bit more detail. It is only about 2 months ago I got this to work at all. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Simulation woes
Rolf Molitor wrote: The 'M' in the designators MQ1 and MQ2 may let the simulator look for a MOSFET model. But you want the IRF840 to be handled like a subcircuit (as stated in library field #3). Try changing the designators to Q1 and Q2. You're on the right track, but Q is for bipolar junction transistors. X is the first letter for a subckt instance. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Open source SP7
Bagotronix Tech Support wrote: Ivan, I thought all of that stuff (or at least most of it) was available from the Microsoft Developers Network. and to be more specific, from their Visual Studio, and particularly from the individual SDK's for the different products. Most of it is available through the MSDN, but you gotta pay for the yearly subscription. And it's expensive. And what about the undocumented API calls? If the Win32 API were fully and correctly documented, Wine would be nearly perfect. Remember what Microsoft did with DOS? DOS isn't done until Lotus won't run. They did that with undocumented DOS calls. BTW: Wine is a Win32 emulator for Linux, which allows you to run Windows program on Linux. Theoretically :-( I've never been able to get anything to run well on Wine. And it's been under continuous development for years. If you really want to run Win32 programs under Linux, try VmWare! I have it on 2 machines, using Win2000 Pro as the guest OS, and use P99SE, Xilinx Ise and Bobcad (mechanical CAD/CAM) on it, and it is as flawless as Win2K will allow it to be. VmWare is not free, but it is quite reasonable for the desktop version. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Open source SP7
Bagotronix Tech Support wrote: IMO, the software world is in terrible shape. The main reason free software exists is because some users got tired of being endlessly gouged by commercial software developers' prices and their lack of concern about fixing bugs, and decided to write their own stuff. Yes, and it has to be REALLY bad, too! Notice that practically nobody builds their own car, although the reliability of US-label cars is APALLING! Practically nobody builds their own computer (with FPGAs, or hand soldering chips, etc.), although what you can buy seems pretty good, so maybe there's no incentive. But, people are maintaining an entire multi-user, multi-tasking OS, because the market leader is such a heap of rubbish! And, they've done a FANTASTIC job of it, too! That's great, but the problem with much of the free software is that it's poorly documented, very rough around the edges, and sometimes missing many needed features. Gee, are you sure that doesn't apply to Protel 99SE? I know what you mean, I've seen some of this, but there are also projects that are WELL documented, work exactly as advertised, and most of what you need IS there. I really have no serious complaints with P99SE schematic and PCB. A few small quibbles, but almost everything there works well. I could make it work even better for me if I took 2 weeks and built a completely new set of sch and pcb libraries that are totally consistant across the two, for footprints, pin designators, etc. Much of the stuff I find is really buggy is the PLD section and I've just found a really annoying bug in the VHDL export. EDIF export is totally unusable, there are so many mistakes in the EDIF output format that I'd have to write an entire compiler to fix them. The VHDL output is nearly perfect, it just locks up almost every time you use it the 2nd time in a session. I'll bet that would be a one-line fix! Just reset the state of some database, or something, before running the VHDL module itself. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Open source SP7
Mike Reagan wrote: Hello All, I was contemplating what my next move with Protel will be and came up with an idea of creating an open sourced SP7 software for 99SE. Before I put my foot in my mouth, is there a future for open sourced Service Packs? is it legal? I don't know how you can do a service pack of any kind without access to the source of all the code that went before. Of course, if you can get Altium to give you the source of P99SE, I'm sure there are a lot of people, including myself, that would be eager to dig in and fix the many known bugs hiding in there! Good luck, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Ugh! New bug in P99SE
I just ran into a new problem in P99SE (SP6) using the VHDL netlist feature that I didn't even know was there until recently. If you have a multi-sheet schematic, and try to get the VHDL for each sheet separately, the first sheet works, but then when you try to generate the netlist for the 2nd sheet, Protel goes off into never-never land, eats up all the virtual memory, and eventually generates a file with 64000 lines that say Line=000123, etc. numbering all the lines, and then the VHDL is at the end of that. If you completely close Protel and restart, it works fine, for one sheet only. I can't do all the sheets in the project at once, because of the horrible way Protel doesn't handle hierarchical shematics. And, I don't want to flatten sheets that have 16 references to sub-sheets. It is really a pain to have to shut down Protel every time you want to edit a sheet and generate a new netlist. Does anyone have any idea why this is happening, and anything to make it work right? It seems like I didn't have this problem a few days ago, and then it started happening intermittently at first. It seems Protel tries to read some other file, and combine the contents of that with the VHDL file it is creating. Thanks for any thoughts on this, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE hangups during compact
Dennis Saputelli wrote: we also religiously close before just as you do and still SAW it it would happen during the file closing just like when closing protel without first closing all the windows and files over a six or seven different computer boxes only one showed this problem and not consistently at that so yes it is some obscure thing and yes with the exception i have mentioned we 'never' see it either maybe this is why protel abandoned the DDB ? the bad box had an Intel MB so did the good boxes of earlier generations I had a computer some time ago that appeared to run fine, but I occasionally had CAD files go haywire. I just attributed it to Windows troubles. I later ran Linux on it for some experiments, and then tried to compile the Linux kernel. It blew up every time, with a signal 11. I found out that this is often caused by bad memory. As I had an identical machine, I tried the kernel compile on the other one, it ran fine (for ~ 18 hours on a 486). So, even though Windows and applications appeared to run fine, this machine was sick. I then got a bootable memory tester program, and it indicated bad memory or cache, I don't remember the details anymore. You might try one of the memory diagnostics on that machine that had the difficulty. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] P99SE PLD problem ?
Hello, all, Is anyone using the PLD compiler in P99SE (SP6)? I just ran into a problem having to do with the generation of equations for tri-state OBUFs. It seems to be the same problem with both the OBUFT and the OBUFE. Maybe the problem really is in dealing with IOPADS, however. Anyway, the CUPL statements clearly are not right. There is no pin defined for the IOPAD, and the equations for the logic following the IOPAD (with an IBUF) are completely wrong, and are actually repeated. By that I mean that there are several occurrences of an eauation for the same signal, all different. I suspect the correct code should look like : IF (tri-state control) THEN OUTDATA = X ELSE OUTDATA = 'Z'; (excuse my lapse into VHDL here, which I know a little better than CUPL.) But Protel creates : OUTDATA = NetU3_O; OUTDATA. oe = NetU4_O; OUTDATA = NetU5_O; OUTDATA; Has anyone else seen this and, even more importantly, have any solutions to make it work. I'm using this as a front-end to Xilinx tools. I've figured out how to get an EDIF out of Protel, and hack it up to the point it can be accepted by Xilinx ISE, which I thought was a pretty major accomplishment! But, Xilinx's simulator is almost as cumbersome as their schematic tool. Thanks much in advance! Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License Legalities
John A. Ross wrote: For one, all my employees are prohibited from taking on paid work in similar fields or making use of skills and/or training and/or company resources the company has invested in them and/or made available to them in the course of their employment,(for personal benefit, payment in kind, hire or financial reward I believe the terms are) or second job without the companies consent. There is of course provisions to protect the employees rights should the second job or work not be related to their day job or the investments made by the company in them. Boy, that's a pretty restrictive agreement. I'm glad I have never been asked to sign anything like that. It would literally prohibit a plumber from fixing a leaky faucet in his own home! (That's the personal benefit part.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License Legalities
John A. Ross wrote: I would not also say it was restrictive, if you worked on any confidential projects or used proprietary technology I am sure your employer would have you under personal NDA or contract even AFTER you left them. Yeah, there was a real nice story in the paper last year, I think. A guy who worked for Alcatel came up with an idea. He ran it by the corporate powers, and they had no interest in the idea, and I believe he got that in writing. He quit, and developed the product to the point that he started selling it, or at least showing it to potential customers. He is now a legal slave of Alcatel, developing the product and doing custom modifications for free. He expects to be required to support the product for free for the life of the product, unless his lawyers can find a way to break the terms of the agreement he apparently signed. If he fails to continue to work on this, they apparently can jail him on contempt of court charges. I think they also have a requirement that he take no other job for the duration of this. If I recall correctly, this is going on in Texas. The product WAS very related to his work, and the business of Alcatel, which certainly clouds the picture. I think Alcatel would be totally justified to enforce some of the terms of the usual non-compete agreements and trade secret protection, and could make him work (as an employee) of Alcatel, or make him take the product off the market. Even forcing him to turn over the entire product, and spend a certain amount of his own time documenting it and bringing Alcatel employees up to speed on it would be reasonable. But, this slavery business, with no end in sight, is just too much! The principle is easy, if the company invests in them, they should invest in the company with their best efforts and loyalty. In fact we even invested in them by paying the fees for vocational training or education they wish to take on their own time, for personal improvement as long as it increases their skills base used within the company. Because of this even some of our assembly operators have attained education to degree level. Sure, you should work for your employer when he's paying your salary. But, I have heard of so many cases where a guy who designed aerospace parts, for instance, thinks up an idea for a better fishing reel, on his own time, and ends up having to give all profit to the employer. (There are, I'm sure, lots of cases that can be found where the employee used some facilities or company time to develop the product, that changes the picture very much.) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Tom Reineking wrote: Hi Yuriy, We've had very good luck with quality and quick turn around with Advanced Circuits, www.4pcd.com. I haven't done much with price comparison, though. Good luck. I was going to give the same information, but I think he is looking for assembly (stuffing) of the boards. If that is true, I'm not sure you can find any outfit that will do affordable work on only 10 pieces. The setup effort is just too great for such a small job. It probably makes more sense to buy the parts yourself, and find a part time person who can assemble it directly under the guidance of the person who designed it. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Bagotronix Tech Support wrote: It probably makes more sense to buy the parts yourself, and find a part time person who can assemble it directly under the guidance of the person who designed it. That's true if all you are using is TH or 50mil SMT. For smaller stuff and BGAs, how do you do that by hand with part time help? If ** I ** can do it, with tired eyes and shaky hands, I'm pretty sure I could train anyone with reasonable vision and hand-eye skills to do it in a fairly short time, one-on-one. (Heh, I have trained my wife, who finds sewing to be almost beyond her, to do modest SMT work.) I'm currently working with a number of chips with .5 mm lead pitch, and 0402 passives, and I do it all by hand. Now, BGAs, I admit, are beyond the tools and techniques I have developed. I think I could do a BGA, but I'd have absolutely no way to check it, other than boundary scan and similar electrical testing. So, that is one place that simple manual techniques really hit the wall. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Bagotronix Tech Support wrote: I can solder 0.5mm (19.685 mil) SMT IC's by hand no problem. BGAs are a different story... I can do that too. And my hand can slip, causing a solder bridge to an adjacent pin. It's a PITA to clear away that solder bridge from those small pins. I have developed manual techniques to do these, and they work quite well. I'm still fine tuning it, but I'm doing pretty well with it. What I do is manually squeeze out a VERY fine line of solder paste with standard syringe and a fine needle with the point ground off. I lay this line around the outer perimiter of the component pads. I then place the chip with tweezers, and solder 2 diagonal corner pads. I then inspect the alignment on all 4 sides, and walk the chip, if needed, one pad at a time. When all 4 sides have their pads aligned, I just slide the soldering iron down the rows of leads, at a rate of about 2 pads a second. If the right amount of solder has been deposited, there are NO bridges. If too much solder paste was applied, you will get bridges. The best way to fix them is to remove some solder with fine desoldering braid that has been dipped in liquid rosin flux. Then, you heat both leads at the same time, and the rest of the solder will pull into the pad/lead area, breaking the bridge. (If the bridge is small, reheating the two leads simultaneously may clear it without the braid.) I then apply isopropyl alcohol to an old toothbrosh, and brush the leads vigorously, and wash in water from a sink sprayer nozzle. It looks professional, like mass- produced boards. Oh, how I long for DIP and 50mil SMT packages. I figured it out - it is possible to put an ethernet chip into a 28-pin package (with an 8-bit wide uP interface). So why doesn't anyone do it? They have 100+ pins. Phooey! Yup, but the old days had entire boards covered with DIPs to do what I can do now with ONE very pedestrian Xilinx Spartan chip. And, if there is an error (there is ALWAYS an error or two) I can fix it in the configuration of the FPGA, and don't have to even hack a trace on the board, most of the time! (Of course, there was that one time I used a Protel PCB library part without checking it, and found out that Xilinx used a different convention with regard to pin 1 being on a corner or center of the side. That one I couldn't fix with even a complete config. change!) Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Prototype Assembly House
Yuriy Khapochkin wrote: Jon, There could be problems with hand soldered components. Ceramic capacitors, for example has a tendency to break and become resistor with 10-100 Ohm resistance. Probable, due to thermal tension from manual soldering. I had such problems in the past. Worst of all, it usually happens weeks or even month later. That's why I don't want hand-soldered SMT board go to the field. Interesting, but I have never seen this. I have deployed several hundred hand-soldered boards to customers all over the world. I HAVE seen broken caps on rare occasions, and fixed them. But, I've never seen this sort of trouble, except in manual rework. I definitely do not reuse removed SMT components except on VERY prototype pieces. My feeling is that manual soldering subjects parts to MUCH less thermal stress than IR reflow systems. Since these ceramic parts have VASTLY lower TCE than the PC board, the idea that fully heating the entire PCB and components and letting them cool together doesn't seem to be of any benefit to me. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99 SP6 bug in part type global move?
Steve Wiseman wrote: P99's just wasted a few more minutes of my life... Having placed an array of decoupling capacitors, I (as usual) wanted to place all the part types on top of each other. Since it was a larger array of caps than usual (its a huge DSP), I thought I'd do it using global, and just set all their X,Y coordinates. It turns out that the global editor ignores the 'selection' box in this case, and moves _all_ the component types on that page to the designated place. (While typing this rantlet, I figured I could move the capacitors to a new sheet, select on Y position, and only alter the X coordinate. Worked a treat) Thanks for listening!) You should be able to do an undo for this type of unexpected change. When's SP7 coming, again? Never, according to Altium. Why should they? We've already paid for P99, and won't be paying again. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How to locate components?
Peter Moreton wrote: Can anyone tell me how to quickly search for a particular component in the Protel Libraries? ...for example, I need to find the library component for the LM317, at the moment I do this by adding a likely library to my design, then look inside it. There has to be a better way! This is a problem in P99. The updated libraries on the Altium web site have a text list of all parts supported, so you could capture that in some way and make a cross listing for those libraries. When you have a schematic library open in the library editor, there is a reports/library menu selection that will write out a file with all the library entries and the comment text for each. You could make up a file with all these merged, and the library name appended to each entry. This would be a fairly worthwhile project to do. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] EDIF output, specifically PLD ?
Hello, Has anyone used the EDIF output format from P99SE, especially with the PLD section of Protel 99SE? I'm trying to get around the incredibly hideous schematic package in Xilinx's ISE. The most significant difference is Protel seems to require the IPAD and OPAD components, and won't even create a netlist through the PLD compiler without those components to source the signals. But, Xilinx DOESN'T want the IPAD and OPAD components, it just wants ports on the top-level schematic page. Has anyone figured out how to PLD-compile a schematic without IPAD and OPAD parts for the device pins? Alternatively, has anyone figured out how to get an EDIF file from a multi-sheet schematic in Protel 99SE? Yes, I know, there is an EDIF format selection in the Create Netlist command, but it appears to produce a badly mangled netlist, and the Xilinx tools find many complaints. Digging through the EDIF file produced this way, I see reason for complaint, although I'm no EDIF expert. Primarily, if the sheets are going to be represented as Cells, the ports on the cell has to be defined first, before the cell is instantiated. But, using the Create Netlist command, the definition of the sub-sheets are NOT there! Only the master sheet is defined. Obviously, Xilinx's tools can't work without the definitions of the cell's ports. Another problem with the EDIFs produced either way is that in the definitions of the cells from the library, all ports are prefixed by the '' character, while in the netlist part, the ports are referred to by the PortRef symbol WITHOUT the . Obviously, that can't work. I just use a text editor to remove all 's from the file, as I can't see anywhere in the Protel libraries where these 's are coming from. The 's cause the symbol names not to match with the symbols in Xilinx's libraries, either. Finally, either form of output seems to duplicate definitions of the library components used in the design. Xilinx can't handle that. I don't know if that is actually a violation of the EDIF format or not. Does anyone have any comments on this? If I can figure out how to get a reasonably close rendition of the EDIF file, I should be able to write a simple converter to make the corrections. Thanks in advance, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT audio WAS PCB Copper thickness VS mounted rails.
Bagotronix Tech Support wrote: Anyone heard how the new class D amps sound? Several chip makers (TI, Zetex, etc.) have come out with class D amp chips recently. Personally, I'm skeptical until I get to audition an amp made from these. Might be good for el cheapo consumer audio, but hi-fi? I suppose a class D done right could sound good, but if you go cheap on the post-amp LC filters, it could sound really bad. And using high quality magnetics might end up making it cost as much as a class AB amp would. I have worked with the Harris HIP4080, pretty much the same class D amp, which only requires external mosfets and filter copmponents. They sound quite good. I was more interested in using them in a servo amp application, and did get it working. But, their 80-V rated chip kept blowing up at 59 V. I finally got through to the applications engineed for that product, and he told me Oh, you're doing really well, none of our other customers were ever able to get it to take more than 54 V! I went Ugh! Thanks a lot! and switched to a very complex implementation of the same chip using about 8 chips. But, it ran fine at 80 V, and could go to 180 with ease. I'm only running my amp at 100 KHz, as I don't need the full audio bandwidth to run servo motors. Harris runs their chip and FETs at 1 MHz! The TI and Zetex chips are meant for laptop PCs, and so they often run on 12 V or even 5 V power supplies. You can't get a lot of power out of them. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
Ian Wilson wrote: If I understand John E. correctly he is saying that if you have the conditions for an autojunction but you don't have the autojunction there (either autojunction is not enabled or you delete the junction), you may still have the connection in some circumstances. This is a pretty dangerous situation - it is interesting though that it has not come up a lot over the last 4 year. As far as I know, it is not some circumstances. If any wire segment ends anywhere on another wire segment, they ARE connected, 100% of the time, whether there is a dot there or not. Leaving autojunction enabled will help. At least then you may see stray connections - if you or a reviewer happens to notice them. Well, you HAVE to look for them - it is important. (DXP comment - DXP offers some help here. Firstly wire segments have little graphical details to show where they end. So if you do have two abutting wire segments you can see this little detail. Secondly, there is an option to optimise wires - this option will merge co-linear abutted line segments. This optimise option also offers a nice feature where is you drop a two wire component onto a wire the wire will be split into two nets at the two pins (you can drop in a series resistor, for example easily. As near as I can figure, after discussing this issue of merging line segments for years, the optimise function was added to DXP after I pointed out that you could draw a wire on a DXP sample schematic between two particular points and end up with stray auto-junction hot spots. I am not sure why but it seemed that the discussion in PEDA about this issue for years had not quite managed to make it into the required DXP feature list. Only after the problem was easily demonstrated in a Altium sample Sch did it become apparent why something should be done.) Well, that's nice to know that DXP helps with this problem. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
Brad Velander wrote: John, could the difference come in with which point you started drawing your wire? Starting at the resistor pin or starting from the other connection first? Just a thought. One would have to see exactly how you wired to or past that pin to understand exactly how you are getting the results that you got. Well, the problem is that breaks in an otherwise straight line are not displayed in a schematic. If you lay a crossing wire directly across a break in a wire, it forms a connection. With auto-junction on, a dot appears to warn you of that connection. But, the junction dot is not what CAUSES the connection, it is just a flag that a connection has been made. Some other software automatically REMOVES any breaks in straight lines as they are laid down. Protel doesn't. As well I always work with the auto junction on and have never turned it off. But doesn't the autojunction just aid in making junctions, it doesn't exclude making junctions. It really doesn't aid in making junctions, it MARKS them. The only place it actually makes a connection is when you manually place a dot on two intersecting and unbroken wire lines. Using ERC is still the only way to check a schematic, especially for missed/misplaced pin connections. Yes, but the ERC may not pick up all cases of unintended crossed nets. If one of them is unnamed, and doesn't violate an input/output rule (passive, perhaps) it would not cause an error. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
John Branthoover wrote: Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? This is an artifact of the schematic rules. In fact, that's why the auto-junction feature is there, I think. Any time there is a wire segment with vertices on some point, and another wire segment that either passes through the same point, or has a vertex at that point, these are considered connected, whether there is a junction dot shown or not. The rules are this way so that two wire segments that are in a straight line are connected, as you'd have no way to tell there was a break in the wire. The auto-junction only places a junction dot where a wire segment terminates ON another wire, so it is really just an INDICATOR of the connection, not the thing that CAUSES the connection. The real usefulness of the auto-junctions is that it SHOWS were an unintended connection may have been made. And, clicking and deleting the junction dot will NOT remove the connection, except in one special case. If you have two wires that cross without there being any vertex at the crossing point, and you place or remove a junction dot there, the dot DOES control the connectivity. I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. Yes, you need to have a break in the wire segments at the crossing point. That break, without auto-junction, is totally INVISIBLE - and, of course, that IS the danger there! I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! No, don''t lose faith in the package. Protel (and Accel's Tango) has ALWAYS behaved this way, it has worked like this for 15 years or more. The auto-junction feature, when left on, almost removes the danger of this. But, you have to understand the behavior of every program you use, and know the pitfalls. EVERY program has a few pitfalls. This particular one is something I've known about for many years, and since the auto-junction feature, it is not really a problem. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PEDA] P99SE Annotation
[EMAIL PROTECTED] wrote: Sounds good, blindingly obvious really, thanks.. Robert Igor Gmitrovic [EMAIL PROTECTED]To: Protel EDA Forum [EMAIL PROTECTED] om.au cc: Subject: Re: [PEDA] PEDA] P99SE Annotation 04-Aug-2003 12:36 AM Please respond to Protel EDA Forum It should work if the default designator is set int the sch library, e.g 10? for resistors or 20? for capacitors. Default designator is treated as a prefix and should not change when annotating. No, I think it needs to be 100? and 200? to get the 1 or 2 in the thousands digit. Otherwise, yes, it should do exactly what he needs. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Copper thickness VS mounted rails.
Brian Guralnick wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15 amps. Check with your PCB vendor on how much the extra thickness of copper will cost you. Then, compare with the rails, including the cost of having the assemblers deal with it. If the 4 or 6 Oz foil will carry the current with acceptable electrical characteristics, it sounds like the best solution, unless the extra cost is prohibitive. My guess is the extra foil thickness will be cheaper than all the extra handling to assemble the whole thing. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PEDA] P99SE Annotation
[EMAIL PROTECTED] wrote:
Hi
My company uses an internal designator naming standard for schematic
symbols. The standard is such that each type of component is assigned a
prefix and each designator will be 4 digits long, eg. 1st resistor: 1001,
2nd resistor: 1002, 25th capacitor: 2025, 54th diode, 3054, etc.
Is there anyway I can get P99SE to generate this automatically? I
understand that it can only do 11, 12, etc, and not 1001, 1002, etc.
Furthermore if I reset the designators, the prefix number gets wiped out
as well.
Yes, I think you can get most of the control of this scheme in 99SE.
All global editing of schematics can be limited to specific part types
in the global edit window.
The one thing that probably can't be made to work is the automatic
reannotation
feature. I usually do NOT use this feature anyway, as it is pretty
difficult to
control it. Using specific settings of the global edit {abc=def} and
the match
string [10*] sort of restriction should allow you to fairly easily set
up your
component designators.
One possible way to do it automatically, though, is to create the schematic
using R?, C?, D? etc., and then, AFTER the entire schematic is entered, use
the automatic reannotation one time only. Then, use the global edit to
change
all R100 to R999 with a replace string like {R=1}
all R10 to R99 with {R=10}
all R1 to R9 with {R=100}
in that order, then repeat for C, D, Q, etc.
You could even generate a macro script to do it all, I think.
Jon
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Re: [PEDA] design verification
[EMAIL PROTECTED] wrote: Also, treble check any parts you have created to ensure no duplicate pins or else Protel will start to route and just leave an unconnected track (it did it to me anyway). If I remember correctly, the unrouted net warning doesn't appear in this case. Yup, I have finally used up the batch of boards that had to be hand-edited because of this one. I had no idea this sort of error would slip under Protel 99SE's radar, which is otherwise VERY comprehensive at finding any discrepancies in the schematic. This is the only error I know of in the verification area. There are some quirks and difficulties related to supporting some HP printers, but that really isn't Protel's fault. As far as reliability, 99SE is unreliable on Windows 95, which you aren't supposed to use, anyway. It has been extremely reliable on Windows 2000 Professional, to the point of only having one or two hangups in the couple years I've been using it on that OS. The database was always saved, even when it hung up on 95! Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Viewing gerber files
Alfonso Baz wrote: Hi all On several occasions I've seen postings here, that suggest checking Gerber files for nefarious errors. I've examined these files and found them to be text files full of data (a lot like EPS files). I'm hoping that checking Gerber files doesn't mean understanding the data! 8-) My question is how do you view and/or check the gerber? Is there some gerber viewer program out there that I need to know about, or perhaps a feature in protel99se that I'm not aware of. Yes, you do an import of all the Gerber files to a new (blank) PCB file. Then, with display single layer, you can examine each Gerber plot by itself. You can actually detect a few odd things that are not clear on the standard PCB display, but especially problems in the generation of the Gerbers and the associated apertures. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [OT] Highway Robbery
Thomas wrote: $1200 AUS for the two day Protel 99SE Simulation Training course! Plus airfares, plus accommodation, do these people think I'm made of money? It's a pity, as it did sound worthwhile until I got to the bottom line. Why, yes, and they want a chunk of it! As for simulation, it almost works, I'm sure I could learn how to do a few things better, but I've figured out pretty much everything I need to know about getting chip-maker's models loaded into Protel and working. NOT easy, but it can be done. Otherwise, you need to know the ins and outs of SPICE to know why things go haywire, sometimes. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Re[2]: Protel99se and win2k fun etc etc
Phillip Stevens wrote: My guess though, is that my biggest gains may have come from the RDRAM in the new system vs the SDRAM in the old one. (I'm sure the faster CPU played some part too...) It is very application-dependent, of course, but many white papers on RDRAM, where exact same configurations and programs have been benchmarked with the two kinds of memory, were VERY inconclusive! Some showed as much as a 10% difference, but most showed less difference than that. CPUs with big caches do make a larger difference. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fan out Via clearance
Shuping Lew wrote: Jon, Thank you very much for your replied. Could you describe some more details? ---How to set up different grids for Vias and traces? Grid setting for traces should be much smaller than Via's... I'd like to set up 5mil for traces and 55 mil for vias so I can run a trace in between. Is there any way to set up different grids for auto router? Yes, you have a point, there. The detailed way to do this probably to set a rule such that vias cannot be closer than some calculated amount to other vias on a different net. (Does the autorouter follow such a rule?) Make that clearance enough so that a track plus the clearance on each side can then make it through between them. I can never remember exactly which rules the autorouter follows, and which it ignores. (The rules setup does tell you which ones are observed by the router.) Note that the grid is not an absolute restriction on track endpoints, however. If the track ends on some other primitive, it is allowed to go off-grid to hit the center of that primitive. That won't work for intermediate track segments, however. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fan out Via clearance
Shuping Lew wrote: Hello, all, I am using Protel 99Se Auto router for fan out Vias. I'd like to have one trace go in between fan out vias. Is there a rule to set it up? Thank you very much! Fortunately, fanout is one of the first things it does. You should be able to find a combination of track width, via OD, and grid that will cause the vias to be placed far enough apart to allow a trace to pass between them. It may take some tinkering. You may want to set particular rules, just do fanout in the autorouter run, then change the rules and run again, with lock all preroutes. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Bare board storage
Ben Uijtenhaak wrote: Although offtopic I like to submit a question to this forum because you guys are all professionals. More and more we need to store bare boards for a period of 3 months or even longer. Are there any requirements or so to prevent the boards from aging and/or absorbing moisture etc.? How do you guys handle this issue? For 3 months, you can probably leave them out on your desk (but don't spill coffee on them)! For 3 years, a plastic bag that zips closed or is taped shut with good masking tape is usually good. Make sure the corners of the boards don't pole holes in the plastic. Don't put any paper inside the bag with the boards, as some papers emit acid vapors that can tarnish the solder plating. Moisture is not likely to be a problem, but a 24-hour bake at 50 C should remove any moisture, anyway. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Template/s for computer motherboards??
Leonard Gabrielson wrote: Part 1.1Type: Plain Text (text/plain) Encoding: quoted-printable I bought an ATX motherboard made by Intel a few years ago, and made a custom enclosure for an industrial use for it. I found a document on the Intel web site that had detailed mechanical drawings of all the mounting holes, exterior dimensions of the board, and maybe placement of the connectors, too. You might poke around on the Intel web pages, and do a search for ATX. You'll get a bunch of hits on that, of course. Then, look for the detailed spec sheets for one of the models. If you can't find anything, I can dig out that document I got and hopefully find the exact URL for it. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout? - Shorted Planes
[EMAIL PROTECTED] wrote: Run a couple of amps (from a current limited power supply) through the short and use a 5 1/2 digit voltmeter on the millivolt range and you can get the short circuit location fairly easily. Yes, that's the procedure. But, with perhaps 500 holes tied to the ground plane, covering the whole board, the voltage drop across the planes can be REAL small. I ran 6.5 A between the power plane and ground, and was able to apply about 15-20 mV between the planes. The actual location of the short was found at a through hole with about 2 mV difference than the neighbors. But, there was probably 5 mV of voltage drop across the planes. So, it had to be compared to local pads that weren't shorted to spot the bad one. Then, I had to burrow into the board, through 2 layers, to dig out the short right next to a grounded pad. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Guard Traces
Robison Michael R CNIN wrote: Hello, I've drawn a schematic and now I'm attempting to interactively route the traces to match some old artwork, but I've run into some guard traces that I haven't got in the schematic. At least I think they are guard traces. They have a via to GND at one end and follow beside another trace for a while, and then simply stop close by the termination of the actual signal trace. These are Faraday shields, a bit different from a true guard trace. Generally, true guard traces are closed paths that surround a trace or several traces, and are charged to a level such that minimal current can flow through leakage on the board surface or inside the board to affect the charge of the protected trace. This kind of stuff is generally used in ULTRA-high gain amplifiers, and ultra-low current circuits like electrometers. Faraday shields ground out the electrostatic field generated by traces with fast voltage changes, reducing one of the modes of crosstalk. They don't offer much help for the magnetic field, which causes crosstalk when large currents are switched on traces. Having two bus buffers driving different ends of a trace to opposite polarities for a few nS is a classic cause of the this. To be honest, I don't really care about their electrical func- tion. However, we are attempting to as closely match the orig- inal artwork as possible, so the are definitely going on the board. My question is how do I add these to the board without causing a bunch of design rule errors in the end? Right now I'm simply laying the track and punching the via at the end and assigning the via to GND. I know the DRC is gonna hate this, and I depend on the DRC to verify my design and I'd like to not have to sift thru the DRC to decide what is a valid error and what isn't. I want a clean DRC at the end of my board design. If you place a track from point to point, it will be listed as no net. Double click on it and through the advanced tab, change the track to be part of net GND. Now, place a via at the end, and it will automatically connect to the ground plane, assuming this is a multilayer board. You can extend the track to follow the geometry needed. I don't think this will cause any DRC squawks. If it does, they will be of a unique class, and so you can probably know they are harmless. If you do get a DRC violation, you can probably set up special rules to permit this for the GND net. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - bd testing
Dennis Saputelli wrote: so how does a 'flying probe' test really work? i understand the general idea of a couple of probes walking around the comparing connectivity to a 'netlist' made from the gerbers but it seems to me and i think i read somewhere that this is better at finding opens than shorts It should ALWAYS find 100% of opens, as it should either test all possible combinations of points on a net, or walk down the net, checking from one end down to the farthest end. Checking all possible shorts, especially when opens may be present on the board, is not possible, due to combinatorial explosion. So, they have to use some sort of algorithm to figure out which nets are most likely to be shorted to another. nets which pass close to other nets, or have pads adjacent to another net, are the most likely. It is SUPPOSED to be correct practice to run the board again after fixing opens, so that the short detection can have a better chance of finding a short. whereas the good old bed of nails would (or could?) find both I think a flying probe may do better on large boards. The number of pins needed for a good-sized modern SMT board can run to the many thousands. The cost of the dedicated test fixtures, and the cost of wiring them up is a killer for low-volume boards. I suspect many outfits cheat on the test fixtures, and only place pins on the ends of nets. If you have a long, meandering net on an SMT board, it may not go through the pads much, so many small gaps in the traces could be missed. If you examine a tested board closely, you can actually see the marks made by the probes (either kind) and see how many points are being tested, and whether they are only testing from via to via, or pad to pad, etc. When volume gets above several tens of units, then the bed of nails is needed, as test time on the flying probe machine will become excessive. anybody know the down and dirty secrets of all this? This is one of those dark areas, where the fabricators don't care to have the buyers know exactly what they are doing. One reason is that many fabricators who CLAIM to have in house test, DON'T! There are test outfits that will test boards on a few hours notice, and the fabricators ship stuff all around to whoever has available time on their machines. I also would not be surprised, since I caught a manufacturer on this, once, that instead of generating a net list from the gerber and drill info, or from info supplied by the designer, they test the boards AGAINST EACH OTHER. IF they all have the same connectivity, they ALL PASS! I had a 6-layer board with some very convoluted split power planes in them. The fabricator increased the clearance around the non-connecting through holes on the inner planes without my approval, although I had already provided the clearance called out on their design rules. This split one of the planes into several sections. All the boards passed, because they all were split like that. They couldn't explain how this could happen, but I had a pretty good idea. This would be fine if they were supplied a golden board from a previous run, but testing a run against all members of that run allows all sorts of gremlins to get in, like corrupted Gerber files, Gerber files that trigger different interpretations of the way to draw something, missing layers, etc. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout?
Danny Bishop wrote: funnily enough it never happened to me, I have never found a fault on my boards, and hence don't concern myself too much with the tests on basic double sided. I've hardly ever had a problem on 2-sided, and they are easy to spot visually and fix in a moment. But, major trouble deep inside a 6-layer board will drive you nuts! Locating the exact point where two split planes or two power planes are shorted is a real bear! Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout?
Dennis Saputelli wrote: they said with a big plane it is harder to etch there must be at least a bit of truth to that because i have had this trouble with this type of board from 3 different shops - albeit not the highest tech shops kicking around the board was pretty long, about 15 inches, that may or may not be a factor Boards with large density variations can cause a problem. A single gap in a large plane of copper is usally etched first, and large areas of non-copper will locally deplete the etchant, preventing full etching in that area. Conversely, for plating, where most of the trace definition is done in the SMOBC process, the large areas of copper may deplete the copper bath, and leave the plating thinner there. Anyway, modern process gear is a lot more tolerant of this sort of variation, as the boards we design drive the industry to develop equipment that can handle it without stressing the process to where it becomes unreliable. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout?
Tim Exley wrote: Try http://www.dunneroberts.co.uk/allsites/gallery/images/big-top.jpg and http://www.dunneroberts.co.uk/allsites/gallery/images/big-bot.jpg WOW! I'm glad I didn't have to design (or pay for) that one! Vast numbers of big quad flat packs on BOTH sides! Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Complex boards and time to Layout?
Bagotronix Tech Support wrote: With a board that complex, your board vendor had better actually be doing electrical test, instead of just charging for it and not doing it... What? This is endemic in the industry? I've had to can several vendors for pulling this stunt. But, when they get caught by me, with my (in comparison) quite modest boards, there's no doubt what is going on, because the boards come back with 50% failure rate. IE. 50% of the boards have at least one internal short or open. I usually get the test report from Advanced Circuits, so I know what their yield is on multilayer boards. And, it is somewhere between 50 and 75% on most runs. The 2-sided usually come back at 90% or better passing. So, it is real hard for me to believe that many fabricators pull these stunts of pretending to do electrical test as a routine matter. I think they'd get caught WAY too often. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Collecting / reassigning primatives in Gerbers etc.
Abd ul-Rahman Lomax wrote: At 05:09 PM 9/24/2002 -0500, Jon Elson wrote: I don't think there is any automated way to do this, but it should not be a very difficult process, and should not take more than an hour even for a fairly complex board. That's pretty optimistic, I'd say wildly optimistic, having done quite a few such translations. First, it may be necessary -- it is usually necessary -- to create all the library parts. Using existing parts is not advisable because these *can* be slightly different and the goal of a gerber import is to reproduce the board to the resolution of the gerber files, so that one could re-fab it without there being any differences, or at least as few differences as possible. OK, if you need to build footprints, then it is going to take more time. I was not thinking of making Protel produce an identical Gerber output. I was mostly thinking of some way to automate extracting the netlist from gerber files. The footprint pads will all need to be assigned designators. Building a single component might take an hour, if it is sufficiently complex! (Protel does not have a good pad numbering tool. Tango DOS had a great one, easy to use) Yeah, there were a LOT of things that worked better in the old Tango! The schematic editor was a lot faster, and easier to move things around to clear up a spot to add a new component. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Twisted-pair tracks
Cam Andruik wrote: Has anyone ever tried to fake creating a twisted-pair on a PCB? I tried doing so on a recent board and our testing indicates that it did nothing. I think it is a waste of time to even attempt it but some people here think it is helpful. I did this on one board that had analog differential signals right next to 10 A, 80 V pulses with 40-100 nS Tr. It probably works, as there was no measurable crosstalk on the analog signals. I didn't however, make the board both ways and compare. I wouldn't even bother with two comparable low-level signals. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Board Shops with Online Quotes ?
mariusrf wrote: I've had very good results with www.pcbexpress.com for small quantities or protos . They don't charge tooling , also no electrical test for less than 20pcs protos . Well, when we made a manufacturing run of 10 6-layer boards with about 1000 components/board, we asked for, and paid for, electrical test. The boards had the white, circular ET stamp on them, too. But, obviously, not tested, as they were full of shorts and opens. They gladly took our money for the E test, too. 3 days 4 layers no soldermask , ALWAYS (and I mean always) on time with zero problems. 4 days 4 layers LPI soldermask +silkscreen both sides, ALWAYS on time with no problems. No monkeys flipping layers, changing layer order , adding holes, etc. Board quality looks good even under microscope , laminate schedule is consistent . Only drawback is everything is automated. Submit files via ftp, pay over the web, get boards 4 days later. No muss no fuss . Did I mnetion they're the least expensive of the bunch ? Far less than Advanced Circuits for same quality and quantity . There was a time, about 3 years ago, where AC got quite expensive, and www.pcbnet.com was HALF their price! But, I can't handle them not doing the electrical test and saying they did it! Fortunately, AC has come down and is often better than pcbnet's price, although I haven't checked them this year. You just don't get to speak on the phone with your favorite salesdroid , that's really sad . I do all my orders to AC electronically, too. I usually don't speak to anyone there unless my board goes on hold. Jon * Tracking #: E878D9E0CCA2C2448823C4CD9EE511792DFCBA3B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel clone on the way?!?!?!
Bagotronix Tech Support wrote: Wasn't AutoTrax the predecessor to Protel? I wonder if the original DOS code has been recycled into a Windows app? Did anyone on this list use the original DOS AutoTrax software? How does this compare? I used the original Protel Tango PCB, which I think was either the same as Autotrax, or a slightly later version sold in the US by Accel Technologies. It wasn't bad, for PCB editing, but was 4 layers only, and barely that. Foremost, it did NOT have NETLISTS! Or, at least, there was no connection between the netlist and the PCB tracks, except that it could highlight all the pads in a particular net. There was no DRC. It had no external ground plane facility, only inner plane. So, if you needed a front or back side ground plane, you had to plot the inner layer and hand retouch all the pads with pen and ink! I don't think a revival of the original Autotrax product would be of much value to the average designer today. Also, I think it is available as freeware from a number of net archives. Jon * Tracking #: E29D253CFD937848BF180A84B4CB10154CD755EB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel clone on the way?!?!?!
Tony Karavidas wrote: Yuck. Why don't you just run protel at home? If you (or anyone at work) isn't using it at work at the same time as you're using it at home, I think it's perfectly legal. The OLD user agreement definitely permitted this. I think they pulled this out about 3-4 years ago. I'm pretty sure it is a one machine only license now, no matter whether it is being used or not. Jon * Tracking #: 8F84F42BD4E8134EA54B57CCF5000A38A47CD071 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Board Shops with Online Quotes ?
Robison Michael R CNIN wrote: Hello, Purchasing is complaining about us buying so many boards without getting other quotes. I've done business with a couple other shops, but only for specialty work, like controlled impedance or an extreme dimension. I don't want to get quotes from these shops because it takes 2 weeks to get a quote back from them. For the straight- forward stuff that's simply unacceptable. The shop that does our normal boards has an online do-it-yourself quote that I can get in a matter of minutes by simply plugging in the board parameters. Can you folks please recommend to me two or three places besides Advanced Circuits where I can get a real fast quote, preferrably the online type I mentioned above? We used to use Imagineering, aka www.pcbnet.com, as they were cheaper than Advanced Circuits a few years ago. Beware, though, that they charge for electrical test but may not actually do the test. We had a 6-layer board that they did for us, it had the ET stamp on it, but a batch of the boards were NOT tested. We don't have the equipment to test them ourselves, so we find the inner layer shorts, etc. AFTER all the parts are on. Well, we have no other choice but to blacklist them on this particular type of problem. We have gone through about 5 fabricators due to this same game. Advanced Circuits has NEVER pulled this stunt on us. Before we went to Advanced Circuits the first time, we used Proto-Circuits in Alpharetta, GA, and left them for the same reason. I will say that Imagineering remade the batch of boards that were defective, but the two that were stuffed before we detected the problem had to be repaired by extensive effort to locate the inner-plane shorts. That can take 4+ hours to zero in on the exact pad where the defect is. Jon * Tracking #: DBFC7DAD68C6934F8D35CD4E1B36A04A69A6F842 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Long overbars on printed output
Ray Mitchell wrote: Tony, My printer is configured as a simple Ethernet IP printer. Several users here tried the HP Jet Admin stuff but it never worked properly. I'm not clear on the printer driver business, though. If a printer is networked does each user still need to fool with printer drivers on their individual machines or is the printer driver somehow now attached to the printer itself? The driver is part of Windows (sort of), and is associated with the icon you can select under control panel/printers. When problems showed up, I often downloaded a printer driver from HP's web site (for HP printers, of course) and installed it. This often fixed odd problems with the Windows default drivers. So, yes, you still need the RIGHT driver on your machine, and a generic Windows HP driver may not get all possible graphical possibilities to print exactly right. Actually, the long overbar problem just started. I'm not sure when, however. I'm beginning to wonder if Win2K SP3 might not have caused the problem, or possibly one of the other multitudinous periodic updates that Microsoft comes up with. Yes, that is possible. You may want to add an additional driver from HP and try it. Jon * Tracking #: B41BF3B030570C4797FC61D3355F2590993FD856 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject)
Anand Kulkarni wrote: Hi all, I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. ---OR do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? Generally, I think the answer is no. There may be some need to simulate critical traces, such as high-speed clocks, to evaluate need for termination, and similar things. A complete analog simulation of a complex digital circuit including the FPGA is beyond the capacity of todays computers, unless you have a HUGE budget, and a few months of real supercomputer time available. PCB designers generally are not involved in the verification of the circuitry, especially what is programmed into an FPGA. My personal approach to this is to possibly simulate a generalized case of a single signal, like one bit of a data bus, or possibly 2 bits to check cross-talk. Once you know the signal quality of a representative signal, and have varied some of the parameters to see over what range of trace lengths, for instance, proper operation is obtained, you can then apply this as a 'rule' against all the signals of the same character. Some of the people designing Pentium motherboards are supposed to be using lots of simulation, but I have no idea what tools they are using. I think it is pretty clear they are NOT using Protel99 for this. Jon * Tracking #: 5BBAE86F2A670642A7A4D94DB8F0729E3A643CF8 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Linux and Protel WAS: Spoofed email address
Katinka Mills wrote: And, by assisting with the so called Digital Rights Management developments he may also be driving a nail in the Open Source coffin for Linux, since it is impossible for an Open Source OS to truly be written so that DRM could not be removed by an end user. That coupled with his patents for the secured PC may make it virtually impossible for any competing OS to exist if the secured PC catches on. Lol this makes me laugh, this is a USA law, not international, all it means is that all development moves out side the USA, I know a few Manufacturers who are thinking of shifting base and will definately if these stupid laws come to pass. If taken to the extreme position, it should be interpreted to make it illegal for anyone to write any computer program without a license from the US government. And, you should expect lawyers to take ANYTHING to the extreme position. Jon * Tracking #: 45729975C09D4C43BA3EA63FAD502FB4DCA583A5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Spoofed email address (was: (Un)subscribe!!!)
[EMAIL PROTECTED] wrote: Part 1.1Type: Plain Text (text/plain) Encoding: 7bit I've wondered how one goes about spoofing the from address, since that's such a common tactic for spam and other undesirable mail. My sister just got an email with a virus the other day, and the return address claimed it was from me. I haven't seen any way within AOL to monkey with the return address - is this just an AOL restriction? Most unix and unix-like systems allow the user to put anything in the from field, by default. It is AMAZING that most of these systems have not been restricted to allowing only known users, or known source addresses to have access to the SMTP server. Many HUGE ISPs at least until recently, allowed anyone to send mail messages into them for relaying to unsuspecting 3rd parties. Since the Klez worm EXTENSIVELY exploits this feature, I suspect that many of these big holes will be plugged. I complained about this at our departmental server for a year before they found it necessary to restrict it. Glad to know AOL isn't part of the problem! Yes, it can be a pain when you are away from home, but the spammers are drowning us in garbage. Jon * Tracking #: 51EA88232F3D6841BEC804D7232B2F2D581DE732 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Spoofed email address (was: (Un)subscribe!!!)
Bagotronix Tech Support wrote: You need to make sure YOU don't have a virus. Some of these viruses can rifle through your address book and send e-mails without you knowing about it. But, many of the messages that look like they come from some particular user, actually came from another user who had the first user in his address book. There were some submissions to this list, and some to members of this (and other) list(s) that appeared to come from me. Fortunately, some of them came to me as originals, too, and I was able to inspect the headers and see that they were really coming from someplace outside the US, and were just spoofing MY address. Jon * Tracking #: 3CFEB46436C43E45A9AC3E0D7F7D313EA5BF4689 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP software mistake ?
Robison Michael R CNIN wrote: We bought a couple special-deal copies of Protel 99SE from Altium here recently, and they've been in-house now for a a while. I believe part of the deal on the cheapness was that it didn't upgrade automatically to DXP, and maybe not I notice that there aren't any registration numbers for it. Are they expecting me to naively go thru the entire installation just to find out I don't have a reg number, and then throw up my arms in surrender and immedi- ately send them a check for $7000 (or whatever they're charg- ing for it now)? Or has there been some sort of mistake? Most certainly, you wouldn't pay the full $7000 to upgrade, that is the new customer price. They discount everything if you are already a customer of a previous product. Jon * Tracking #: D80E47D6D4E8DC46A87BF69A4F775FF8A2428A06 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs.
Matt Pobursky wrote: On Wed, 31 Jul 2002 21:51:38 -0700, JaMi Smith wrote: Nothing crashes but Protel ! ! ! FWIW, nothing crashes on my system but Protel either. And I mean NOTHING. My drivers are all up-to-date (even my Intellimouse drivers!). My Win2K SP2 is patched up-to-date. My hardware is rock solid and tested thoroughly. I have only had 1 crash of Protel 99SE in the year or so I've been running it under Win 2K. That day, I had been chopping parts out of a bunch of libraries, and putting them into other libraries, and all sorts of odd things that I don't do very often. I got an invalid intruction or such dialog box, closed all the files, and everything was ok. That is the only time I have had a (program) error of any sort since changing to Win 2K. Jon * Tracking #: 3CA3B938F25EA24EAE545B51FBA2D73BFC2898EA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] P99 Xilinx support
Anand Kulkarni wrote: Hi everybody, I am a Graduate student and I am currently working on designing a PCB for a Xilinx FPGA. I have started using Protel-99-SE trial version for the same. Recently I noticed that the support site of Protel offers 2 documents to ATS members (altium total support) members which I might have use for. Now I think it may be unethical but still I think I need these 2 application notes.I was hoping somebody in this group who is also an ATS member could help me out with this.They ask for a valid 9-digit Serial (License) Number . The document names are : 1) Attributes for FPGA Devices and 2) Protel DXP Xilinx Interface I have tried to make Protel 99SE work for Xilinx FPGAs, but never had any luck. I sent a number of messages to Protel (now Altium) support, but they were not able to provide any help. I have corresponded with several people who also tried this, and none of us ever got it to work for FPGAs. I think it can be made to work for the CPLD parts with some difficulty. The problems I ran into were that the schematic library parts for the FPGAs were automatically converted from some other format, and a systematic error left connection dots off nearly all the clock lines. So, you get a raft of FF without clock errors. Also, after getting past that, the XNF files that would be needed to pass the hdl description to Xilinx's tools were not acceptable to the Xilinx programs. I sent the syntax error messages to Protel, but they never responded. The first document you mention may apply to both P99 and DXP, but the 2nd article is clearly for DXP, and probably won't help you with P99. I am the registered contact for TWO fully licensed P99SE sites, but I can't get into these documents, either! They promised they would not abrogate their agreement to continue to support P99SE users who bought before the advent of ATS, but that is apparently not true. I guess you have to plead your case. We all know how responsive Altium has been! Jon * Tracking #: 98EB3CAB2B373B42A18649952A31E1A401C9CF9C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject) - FPGA editor
Rene Tschaggelar wrote: I recently had a look into the subject of FPGA and Protel. I was told the FPGA router is still taken from the manufacturer (in your case XILINX). Meaning you're just using Protel to draw the schematics and send the netlist to the other tool doing the FPGA. These tools from various manufacturers are free available on the net. Since the programming interface is also in that manufacturer tool, I tend to fail recognizing the advantage of having Protel drawing the schematic. Have you ever used one of the Aldec-based FPGA tools? That is what Xilinx used as the sch- (x)HDL section of their tools. The very old one was bad, then last version they used had improved to passable. Then, they replaced the Aldec schematic entry with their own program. It is abominable! It is almost always necessary to erase a net to move a wire, or even relabel a net in many cases. Truly the worst schematic entry program I've ever seen! Protel 99SE schematic entry is so many light years ahead of Xilinx, it is like comparing programming minicomputers through the console switches to C++. Yes, using an external sch editor would be more keystrokes, chance of error, etc. But, when it takes half an hour to change one signal name, the extra effort would be minute. Apparently, there is a large EDA manager as the 'front panel' of the Xilinx tools, and you can splice in scripts to use external editors, library managers and sch-HDL compilers. Now that I know that Protel fixed the Xilinx FPGA translator bug in 99SE SP5, I will have to try this out on the next project. One advantage of not having the FPGA in protel is : The FPGA is a chip with pins and its internal is hidden. This allows the FPGA, in the EEPROM-type case to act as copy protection. Further, you won't have the library of functions that the XILINX tool offers. The sch. library for most FPGAs are pretty public, and I think Protel already has them. There were problems in some of the schematic level versions of this, years ago, but I think the pre-compiled macros are OK. I admittedly never tried the FPGA feature of Protel. I did. In the abstract, it seemed to work quite well. When I went to compile for specific Xilinx chips, things went bad. The Protel digital simulator is also pretty nice and fast to use (minimal keystrokes). The latest Xilinx simulator won't let you graphically edit timing diagrams. You have to compile a VHDL testbench as ASCII text every time you want to move an edge! I mean, what a step BACKWARDS! These guys are still in the IBM punch-card, mainframe batch processing mindset! Jon * Tracking #: 67AFF37B2B45474BBF60ACB726758B9791C7DCB6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs.
[EMAIL PROTECTED] wrote: For instance, I was happily running Office 97 under NT when the computer guys decided to give me an upgrade to Office 2000. Whether this event was related or not with other upgrades, shortly thereafter I got a failure to Speaking of upgrades breaking things, I once had a machine that would occasionally crash running Protel under Windows 95, and I decided to upgrade it to Windows 2000 that was then in Beta. Windows 2000 died immediately every time. Investigating revealed that I had been using the machine with a SIMM module that had 3 pins not soldered for over a year! I fixed the SIMM and the problems went away. It seems Protel was the only thing under Win95 that actually used the highest blocks of memory, while Windows 2000 used all of memory right away. So sometimes a software problem is really hardware. I think there is really a LOT more of this going on than people are aware of. I had an experience very early in my migration to Linux that brought this out. Long before that, I was in the middle of my biggest PCB design up to that time, using the last DOS version of Accel's Tango PCB. Things started going wrong faster than I could fix them, ie. half the board being lost when you closed and reopened the file, etc. So, I switched to Protel, which we had been evaluating for a while. I finished that project, and eventually the computer was retired to my basement. I tried to fire up Linux on it to experiment, and compiles of the kernel would consistantly quit with a signal 11, which is basically traceable to a bad page table lookup. Another identical motherboard worked fine. Obviously, I had been running Windows 3.1 and PCB cad software for several years on bad hardware! And, I'd been blaming the software for all of it. (Yes, the repeatable bugs I had with Tango WERE the software, I still remember how to make the program malfunction in about 5 keystrokes!) Jon * Tracking #: 7F3FE30AF03A314B9082E4D28B701C9B14E596D5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fastest possible Protel system, price is not a concern.
Bagotronix Tech Support wrote: I tried to talk him out of spending so much for diminishing returns, but he always wants the biggest, fastest thing available at the time. He says he only gets approval for stuff like that once every five years, so it has to last a long time! And besides, it's the company's money, not his, that is being spent. Personally, as a business owner, I would want my employees to be better stewards of my money than that. But then, there is much strife among the employees and management at the company he works for. Sounds very Dilbertian to me... It truly amazes me what goes on in large corporations, especially multinationals. I have some friends who work for MasterCard, and the stories out of there are beyond belief. If there is a specific product that has anything to do with computers, it has to be bought from the vendor that has been specified for computer acquisition for that year. So, if they need memory chips, or GPIB interfaces, or video monitors, or laptops, or IBM mainframes, they HAVE to order it from Unisys (the chosen vendor at least some of the years). I don't know what overhead Unisys would charge on a Dell laptop, or an IBM 390 mainframe, or a memory stick. But, it HAS to cost WAY over what you can just buy it from the manufacturer for. Also, it usually takes something like 2 days of manpower to make sure the chosen vendor actualy know what to buy for you from the actual manufacturer of the item! The internal overhead must cost them $1M a year, minimum, just at their St. Louis facility alone! Scott Adams might have to start a whole new comic strip if he knew what went on there! Jon * Tracking #: B6A3556EEB60CC45B4642F880D954558E105F6A4 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Duplicate component designator detection
Hello, all, A strange thing just happened. I've been using Protel 99SE SP6 for several years, suddenly, duplicate component designators no longer are detected as an error in schematics! I can't imagine what I've done to break this. The check box for dup designators IS checked in the ERC setup box. It detects a number of different types of errors, but totally misses these! I closed the schematics, closed the DDB and reopened it, but same result. Has anyone seen this and know why it is failing to detect these errors? It fails to detect them even if the dups are on the same sheet, and you just check that sheet. Thanks, Jon * Tracking #: 221B9BADB8A8074B87924C0D945FC9479E47AF8B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Duplicate component designator detection
OOps, sorry, guys - I WASN'T at SP6, this install was at SP2, as it came from the CD. I forgot to upgrade when I moved over to a new computer! Yikes! That's a pretty serious error to get out in the production CDs! Sorry for any testing anyone has done! Jon * Tracking #: E621C55871B4574B96C85792A40815A2D6ABBC02 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Does the Autorouter actually work?
Bagotronix Tech Support wrote: Evidently I have much better luck with the autorouter than most of you folks do. I have used it on boards ranging from 2-sided to 8 layer. I admit that there are sometimes things it does which baffle me, but I don't get the design rule violations like was described in the original post. And I almost always get 100% completion. And it's fast! It is VASTLY faster than the autorouter on Protel98, which was so bad we never were able to use it. The thing with the autorouter is you must practice with it to get good results. Tweak every parameter you can think of and see what happens. I will typically have to tweak parameters and do trial routes until I get satisfactory results. On an 8-layer PCB I might spend an afternoon trying different things. Then maybe 15-30 min. of manual cleanup after I get the result I like (or hate least). Yes, this is imperative. I have seen enough to know it is true, but I don't think I am anywhere near good at properly setting it up, yet. Jon * Tracking #: CCE3A4B0C891054FA61AB0D242D398C22E6B7C4E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Anybody plagued by Protel executable corruptions recently?
Brad Velander wrote: Hi all, this is just a wild fishing trip. Recently I have been plagued by my Protel install being corrupted repeatedly. It seems to be corrupted Borland/Delphi library files (i.e. VCL50.bpl in particular). I can do a clean install that includes deleting all bpl and dpl files, reinstall Protel and everything is fine, a week or so later I end up having to do it again. Anybody seen/seeing anything similar? Note: I have not installed/reinstalled any applications since reinstalling Protel, so it is not being written over by a new version to the best of my knowledge. See if you can get diagnostics for your machine. At least, run one of the bootable memory test programs overnight. You may have defective memory, a flaky CPU or cache bus, or possibly a flaky IDE channel to the hard drive. I really don't think this is a problem with Protel code. It is unfortunate that Protel seems to write stuff back onto the executable file, I think. That is a dangerous practice. If memory contents are corrupted, then what is written back will be contaminated. You could save a copy of the executable file under a different name and in a different directory. Then, you could compare the two to detect changes, or just copy it back. That would be faster than reinstalling the whole thing. (It might also cause the copy protection to refuse to allow the software to run. Well, then you would have to reinstall.) Jon * Tracking #: 1CC38CCCA5B1D848A5EE77C47F29712D6FF02B83 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Anybody plagued by Protel executable corruptions recen tly?
Brad Velander wrote: Dennis, you are exactly correct, the annotate facility crashes immediately upon clicking annotate. The message points to the VCL50.bpl file. I hadn't bothered checking the other functions that were acting up last time, just assumed they could be gone as well. I had reinstalled about a week ago and it worked fine after getting their modified clean install from Protel. However this morning it is back and even after doing the clean install it is still there so I have to try a few other things right now. After I get it running I am going to note all the pertinent details about these *.bpl files and save a clean copy somewhere safe as Jon suggested. That was already on my to do list. Jon, if you are reading this, they write back to the BPL files? I thought these were just library files similar to DLLs? I don't know for sure. Last modification dates should tell the story. I used to know pretty well exactly which files had preferences updates in them, but Protel has grown so much, I don't any longer know for sure. All libraries that are available in the PCB or SCH document at least get new dates, even if you change nothing in the library. The preferences seem to be in ...Design Explorer\system\ADVPCB.DFT Good luck, Jon * Tracking #: 8FE71717813DCB418CEB2A1EB28EB240314E3695 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 90 degree C?
Michael Biggs wrote: Hi all, Anyone run very hot traces @ like 90 degree C on there PWBs and or use surface mount heat sink around the component( like a D-PAK)? Thanks for any response. I know this is a Protel questions group but everyone seem knowledgeable in design layout. I would assume that over a fairly short time the epoxy holding the copper to the laminate would deteriorate, and the foil would lift off the board due to the thermal mismatch. Some cycles of this might cause the foil to crack. I'm pretty sure a recognized safety testing lab would not approve any device designed that way, if they discovered that is what you were doing. Using a foil area to draw heat away from a heat source is pretty common practice. I imagine some people let their junctions run at 90 C, but I suspect the heat sink surface runs cooler than that. Jon * Tracking #: E17219ECD51CDF48ACDF490FB27BDC77807B5A59 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hardware questions (upgrade time - yuk!)
mariusrf wrote: I'm using 2 17 LCD's at 1280x1024 each, with a dual head card. I wouldn't go back to a CRT . 17 LCd's can be had for little money now, paid $1000 for both months ago. All things considered, the 2 lcd's give me more viewing area for the money, more resolution , take less desk space and are sharper than crt's for the same resolution . I have a Dell 17 LCD monitor, it works quite well for Protel. It is the model 1702FP. List price is $799. It seems best to keep it at 1280 x 1024 resolution, although it does a pretty good job of interpolating for 1024 x 768. Some other resolutions really show artifacts. I've been using it for 9 months or so, and am real happy with it. I can't say it is BETTER than a really fine CRT with a good video card, but it definitely is not worse. Even color rendition on photographic or synthetic images with smooth color gradients looks as good as a good CRT. I also tried a 15 Dell LCD, and it definitely was inferior. Jon * Tracking #: D0E1512DE4399749ACE1B7EF156FAEE55E1CF3AA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 'Ghost' mouse presses
Terry Creer wrote: Part 1.1Type: Plain Text (text/plain) Just recently I have been getting 'ghost' button presses from my mouse in P99SE. When placing a track, I press the left button to start it, and it is as if I had pressed the button twice. It's starting to get annoying. Any suggestions? The mouse is a Logitech optical scroll mouse. I'm using the latest drivers from Logitech (Mouseware 9.61) and running a P4 1.6GHz with 391 Mb RAM. Your button switches may be wearing out. I have had this happen on several mice and trackballs (which I prefer for CAD work). I buy the closest matching switch from Digi-Key or Newark, and replace them. In a pinch, I can move the center switch to replace the worn-out one. If there is a mouse test program, you might try it to see if it is detecting double or erratic button presses. Jon * Tracking #: FD1E8DB9E6915A44AAE37128A224B63EE0EEC0F7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fwd: OS bugs WAS: Problems with schematic annotate function. Linux Added.
Jason Van Dellen wrote: So, you're saying Protel 99SE works well under Win4Lin? Yes, but you still need the cab files and a Lisence. Yes, I knew that. I tried VMware a while ago and found it very bulky and slow, is that still the case? It would have to be remarkably bulky to fill up my 20 GB disk. The rpm file is just under 10 MB, which is pretty big. As for the size of all the installed files, I really don't know. This does include the documentation. As for speed, I think it runs as fast as Win2K on the native hardware, although it is a little hard to tell. A 1 GHz machine is so fast, unless you time autoroutes or something, I don't know how to accurately gauge performance. I certainly am NOT complaining, it is plenty fast enough running Protel 99SE for my needs! Jon * Tracking #: CC2FC2022F2624419B7D8086D7171D8C3F7E2A93 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] ATS - don't do it! (was restore defaults...)
Igor Gmitrovic wrote: Tom, many of them will join us, they just keep it quiet. It would be probably better from our users' point of view if more people voiced their opinion. That would hopefully let them understand we are serious when we say 'We are not buying this anymore'. We made the mistake of blindly buying Protel 98, and were very disappointed. When 99 came out, we said NO WAY, and kept using what we had. When 99SE came out, I tried it with trepidation, assuming it would be even worse. But, it worked well, solved some shortcomings in the earlier software, so we then upgraded. But, we will look long and hard before paying for any more upgrades. The need to do something major that we can't do now would be the only reason to upgrade. Protel 99SE pretty much does what it is supposed to do for schematic = PCB. Maybe people using microvias or something might need more features. Jon * Tracking #: 7A135105E47AC749A03B32D4CB8D84A1E38D13BC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] ATS - don't do it! (was restore defaults...)
Tony Karavidas wrote: I think you're in the minority on P98. I remember really enjoying the update from prior versions. What didn't you like about P98? Well, I was running it on Windows 95, which wasn't recommended. But, that's what I had. The major problem was with the autorouter, and I think there was a real problem there. But, I saw a lot of processes hanging, etc. and it seemed really unstable. I was hesitant to install P99 because of the DDB issue, but after I got used to it, I liked it a lot. Well, when I tried P99SE on the same machine, same OS, it seemed to work a LOT better. It still would crash daily or so, due to Win 95, but was otherwise pretty stable, and the autorouter worked about as well as the default router used to work. Not great, but definitely better than the 15% completion per day, which was the BEST we'd ever gotten out of P98. I suspect the computer and OS were responsible for a large part of this, and I didn't know about that until P99 was out. Jon * Tracking #: FA3A11977FBA2242A0D77B1AA77F2D8125CBBAF6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fwd: OS bugs WAS: Problems with schematic annotate function. Linux Added.
Jason Van Dellen wrote: If I need to run Windows Apps(eg Protel), I run Win4Lin. http://www.netraverse.com/ So, you're saying Protel 99SE works well under Win4Lin? I've been running it under Win2K in a VMWare virtual machine, but if I can skip all that, it may be a lot better than running (and managing) two whole OSs. Jon * Tracking #: 519020D84E31744E9994D9092416F61ABC4095DB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Re[2]: Drag Selection in PCB Editor
Igor Gmitrovic wrote: Jon, in PCB Editor you go to Tools-Preferences-Options-Component Drag and choose Connected Tracks mode. That would enable you to drag tracks. It works as it always did, since the DOS times. I have W2K and P99SE SP6. It drags the first segment of the track connected to the component. And while you are in the drag mode, you can't rotate the component. That's something I never really liked. Maybe someone would like to put that on the list for the DXP release. For me, with the ATS and the inflated pricing expected for the DXP, upgrade is a very, veeery distant possibility. Yes, I know how to enable the VERY limited drag tracks with component feature in Protel, but it is VERY limited! I want to be able to drag tracks with a selection, and maybe have the option of dragging all tracks that pass through the region, as well. It really does a poor job of this. I also seem to remember that it drags the tracks, rather than dragging the track ENDPOINTS, which would be MUCH more useful. That would keep the tracks connected. How about selecting a bunch of track segments, either within region or by toggle selection, and then doing a drag on all of them, just like it does a drag on one track. I seem to remember that it can't do this, either. It breaks the tracks rather than rubberbanding the connected track segments. Jon * Tracking #: 4450EECD84E6E2428C98565349B87E8177AC1421 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fwd: OS bugs WAS: Problems with schematic annotate function. Linux Added.
Igor Gmitrovic wrote: Don, for the same reasons I see Protel (ie Altium) starting to lose thier user base. With the ATS useless and increase in prices people will start looking elsewhere. How could they explain charging us for the ATS and then they claim to stop support for the P99SE. What do they want us to pay them for? What bugs have they fixed so far, does anyone know? Have they fixed schematic annotation? I wonder if Mr. Protel (excuse' moa, Altium) knows what's happening in the field and how much would their management care anyway. There were number of other people in this forum with the views similar to mine. If they don't change something it looks to me they are going M$ way, down. Slowly, but surely. Well, if they really believed that their user base was going to walk out on them, they'd do something in a hurry. So many companies ignore obvious signs of customer dissatisfaction for so long, however, that by the time they finally wake up, it is WAY too late! Anyone heard of a Linux based PCB CAD program? There have been a couple of starts, SourceForge has one that is a pretty decent schematic editor, but no PCB function that is worth consideration. I'm keeping an eye on it. Jon * Tracking #: 567C4A6FBA77B048A29F13D5914363A4B11B6BB0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
