[PEDA] Protel 99SE - Pick-and-Place in ASCII
Hello, Our assembly house is requesting the pick-and-place file in ASCII rather than XY. Does Protel 99SE generate ASCII format? Thanks, Ray Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Flipping a PCB layout - 99SE
Is there a way to flip an entire PCB layout along the Y axis, thereby producing a view of everything from the bottom layer to the top? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Flipping a PCB layout - 99SE
I was not clear. I want to flip the entire PCB layout and be able to work on and modify it - not just view it. At 04:09 PM 5/17/2004 -0400, you wrote: At 03:03 PM 5/17/2004, Ray Mitchell wrote: Is there a way to flip an entire PCB layout along the Y axis, thereby producing a view of everything from the bottom layer to the top? This has been discussed extensively, and Mr. Wilson produced a server that would flip a whole PCB. I forget the status of that server, it might not be available. But Mr. Mitchell spoke about producing a view. This is quite a different thing from actually flipping .. a layout. Protel does not have direct flip view capacity, though I think you can do it with the 3D viewer. However, CAMtastic can be used to view flipped gerbers. Gerbers can be generated as mirror images, or flipped, I think, in CAMtastic. You can then, if you wish, import gerber back in, perhaps putting it on a mechanical layer. I've done this to create single assembly drawings showing both sides of the board. I haven't played with it, but I think the Print facilities can also produce flipped views It has been suggested that there be a view command that flips the PCB display window. That would actually be relatively simple, it is a little surprising to me that it hasn't been done yet. Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Can't see PCB Connections
Hello, I'm running Protel 99SE SP6 on Windows XP. On a new PCB I working on none of the net connections show (you know, the stringy little threads between unconnected nets!). I've gone into Document Options - Layers and turned everything on, including the Connections. I've also made sure that the color for connections is different from the background color. Is there some other place this might be turned off? Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Auto router Can't Initialize error
I'm running Protel 99SE SP6 on Windows XP. Sometimes when I try to start the auto router I get a Can't Initialize error. This most often occurs if I'm trying to autoroute a specific net, but I'm also now getting it when trying to autoroute All. I have a bunch of manual pre-routes I don't want to lose, otherwise I'd just unroute the whole thing and start over. Any suggestions? Thanks Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Keepouts on Planes
Hello, I would like my various planes to be back 50mil from the edges of the PCB. I placed a line on the keepout layer and set my clearance constraint to 50mils. While this does keep the autorouter from placing anything closer than 50mils from the edge, when I look at the Gerbers for the various planes it appears that they go right up to the edge and ignore the keepout. What is the correct procedure? Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] False DRC Clearance Constraint Error (99SE)?
Hello, I have a clearance constraint between a trace on the keepout layer and a component on the top layer set to 0mil (I've also tried -1mil) but it still gives me a DRC error between the keepout trace and the component pad that sits on top of it. This is obviously not the correct approach. Suggestions? Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Can't add Planes 2-10
Hello, 99SE: During my initial PCB layout stages I created internal planes 1-13. For the final product I reduced it to 3 internal planes. To delete the excess planes I temporarily placed everything I could (split planes, etc.) on Plane 1 and deleted everything from the other planes. I was then able to delete all those planes (using the Layer Stack Manager), leaving only plane 1. However, when I try to add new planes the numbering always starts with plane 11, skipping 2-10. When I look at the Design-Options-Layers dialog it says that only internal plane 1 is being used. However, when I look at Tools-Preferences-Colors, only internal planes 11-16 are grayed out. It sounds like some part of the application is retaining some memory of previously used planes. Any ideas? Thanks, Ray Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] 99SE router gets into an infinite loop
Hello, I have noticed that about 20% of the time after I move a PCB component then try to reroute using Protel 99SE it gets in some sort of infinite loop where it appears to be placing then removing the same route over and over. It makes me wish it had some sort of Kick in the ass button that would somehow force it to move on. I end up having to stop it, move some component, then try again. Is there some setting that controls this type of thing? Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Good schematic/PCB development suite recommendation?
Our group has used Protel for years. I've tried to get everyone to change to something else for most of that time but the resistance has been fairly great. It seems that the the philosophy has been that pain you know is preferable to the pain you don't know. However, with the introduction of DXP/2004 everyone is starting to realize that a good tool is needed. Is there something that is generally considered to be the best? I realize that some of the tools cost significantly more but when the frustration, poor results, and wasted time are considered, it may not actually be that expensive. One of the guys here uses PADS and really likes it. If we make a change we don't want to make the same mistake we made with Protel again. Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Are fiducials necessary?
I was reading about fiducials in J-STD-013. Are they necessary or just something that may come in handy? Might a board assembler tell you he can't pick and place if you don't have them? My board has 4.9mil traces and spaces and many of my components are 10mils apart. Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Are fiducials necessary?
That's good enough for me. I'll use them. My understanding is that in general: 1. They should be 1mm in diameter and have a clearance of at least 1mm around them. 2. They should go as close to each part as possible but need not have any specific or consistent distance from the parts. 3. They should be copper with no solder mask. 4. There should be some global fiducials. 5. Different assembly shops have differing needs/preferences. Is this reasonable? Thanks for your help. Ray At 03:46 PM 4/9/2004 -0400, you wrote: Ray, I work for a contract manufacturer specializing in small - medium production volumes. Fiducials are more than just handy! The Pick Place equipment uses fiducials to identify board location and fine pitch part location. If they're not present we have to jump through hoops to get parts placed correctly. As a result placement accuracy suffers which can force re-work. This means we have to charge you more! Regards, Steve Allen Project Engineer Manufacturing Services, Inc. Kennewick, WA n a message dated 4/9/2004 12:32:38 PM Pacific Standard Time, [EMAIL PROTECTED] writes: I was reading about fiducials in J-STD-013. Are they necessary or just something that may come in handy? Might a board assembler tell you he can't pick and place if you don't have them? My board has 4.9mil traces and spaces and many of my components are 10mils apart. Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel 99SE - Routing vias are all 20mil diameter w/28mil hole!
Hello, In my design rules I've specified that all routing vias are to be 20mil diameter with a 10mil hole. However, the router makes them all 20mil diameter with a 28mil hole. Nice feature! I know it hasn't always done this - only sometimes. I only have one design rule for routing via style. Its scope is Board and it is enabled. Am I holding my mouth right for some routes and wrong for others? Ray Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Creating selective keepouts
I'm using Protel 99SE SP6. I have components on the top and bottom of my board. In one area of the bottom I would like the autorouter to be allowed to place both vias and traces as needed. In another area of the bottom, however, I would like it to be able to place vias, as needed for routing on other layers, but I don't want it to be able to place any traces. I've tried specifying NOT USED in the design rules for the bottom layer but when I do that it will not route anything anywhere. Any thoughts on this? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] The Protel 99SE router (router?)
Hello, Is anyone big defender of the Protel 99SE router (except maybe Protel)? Here are some features I have noticed. I'm sure this is this the tip of the iceberg. Is DXP/2004 any better? I wish that instead of producing new bad products they would spend their time fixing the bad ones they've already sold us. 1. When I route my board using 4 signal layers it is unable to route 12 signals. When I give it 6 signal layers it is unable to route 24 signals. Is this backwards or what? 2. It rips up and reroutes some locked pre-routed traces. 3. In some cases it stops a trace about 1/16 from its destination pad even though there is nothing in the way, then produces a DRC error because of it. 4. It sometimes brings vias from different nets up into a no-net polygon pour, shorting them all together, then produces a DRC error because of it. 5. It sometimes lays a track from one net onto another, shorting them out, then produces a DRC error because of it. Oh well, it still beats tape and a light table! Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Need some router basics
Hello, I do PCB layouts very infrequently. I've now got a fairly complicated routing job to do and I would appreciate some tips about the capabilities of Protel 99SE. Hopefully someone can tell me if the following are possible and and give me some hints/suggestions: 1. I have certain areas on several layers (different on each layer) that I don't want the autorouter to place traces in. However, I do want it to be able to place vias in these areas as needed to help with trace routing on other layers. Is this possible? 2. My other option to the previous idea is to use blind vias in these areas. What is the common wisdom concerning blind vias. Are they considered nothing special, or do board fabricators consider them a big deal and they should be used only as a last resort? 3. I have areas on several layers that I don't want the autorouter to place anything in but it's okay if it routes in this area on other layers. I believe I've seen something in the help regarding the ability to do this. 4. I have several BGAs with different pitches requiring different trace widths for escape paths. Is it possible to have the autorouter use a narrower trace until it gets past the narrow area, then widen out? Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] 99SE: 2 of every net name?
I've never seen this before. In 99SE (Win2K) I've created a schematic and am starting the PCB layout. When I double-click on a pad and look at the net attached to it, as well as all the available nets, I noticed that there are two of every net. For example, there are 2 A5 nets. Some of the A5 pads are connected to one of these nets while others are connected to the other, even though they all have the same A5 name. My manually going through all the pads and selecting, for example, the first A5 of the pair I can get all A5 pads to connect together, etc. Any ideas? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] A DXP annotation feature?
I don't use DXP myself but a coworker here has no choice since 99SE won't work on WinXP. Anyway, when it came time to annotate his schematic to get rid of all the question mark designators he went through the standard procedure. When it was done he found that several schematic symbols had been arbitrarily moved to other pages and plopped down right in the middle of nowhere! In addition, some existing symbols had been duplicated and placed in arbitrary places on arbitrary pages. Therefore, his solution is to simply go through all 12 pages of his schematic every time he annotates in order to correct DXP's errors (or should this be considered a feature?). Has anyone seen this behavior? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A DXP annotation feature?
At 05:33 PM 3/17/2004 -0500, you wrote: -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 17, 2004 5:05 PM To: [EMAIL PROTECTED] Subject: [PEDA] A DXP annotation feature? I don't use DXP myself but a coworker here has no choice since 99SE won't work on WinXP. Anyway, when it came time to annotate his schematic to get 99SE has been running fine on XP Pro here for ages. That's encouraging to hear. Many of the people here have not been able to get it to run. In fact, many of them have gone back to Win2k just so they don't have to downgrade to DXP. I'll pass this on to them. Thanks. -- Dean Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE: 2 of every net name?
Mike, I don't understand what I need to do to clear all nets. I told it to un-route (although nothing had been routed). From within the PCB editor I then told it to load all nets. It indicated that there were many redundant nets. I told it to execute and it proceeded to remove all nets and all parts. It's a good thing that the UNDO works! I've placed many of my components already. Does this mean I must redo all of that? If anyone can tell me the format of the offending portion of the .DDB file I'm not adverse to using a binary editor on it. This approach is probably way too complex for the average person, though, since it's obviously too complex for the Protel developers themselves. Thanks, Ray At 05:29 PM 3/17/2004 -0500, you wrote: Ray, If the problem is not in your netlist meaning nets A5 are not showing up twice: you must do this to avoid double nets in PCB 1. Clear all nets, 2 Load the netlist 3 Connect copper to pads 4. Run DRCs I am saddened to report this problem still exist in 2004 Mike Reagan -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 17, 2004 4:58 PM To: [EMAIL PROTECTED] Subject: [PEDA] 99SE: 2 of every net name? I've never seen this before. In 99SE (Win2K) I've created a schematic and am starting the PCB layout. When I double-click on a pad and look at the net attached to it, as well as all the available nets, I noticed that there are two of every net. For example, there are 2 A5 nets. Some of the A5 pads are connected to one of these nets while others are connected to the other, even though they all have the same A5 name. My manually going through all the pads and selecting, for example, the first A5 of the pair I can get all A5 pads to connect together, etc. Any ideas? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE: 2 of every net name?
That did it! Thanks for all the help. Ray At 11:44 AM 3/18/2004 +1100, you wrote: Ray, The Menu Design, Netlist Manager, then right click and select clear all nets. No, you don't need to remove any components. There is nothing you can do in the ddb file. Darren Moore -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Mike, I don't understand what I need to do to clear all nets. I told it to un-route (although nothing had been routed). From within the PCB editor I then told it to load all nets. It indicated that there were many redundant nets. I told it to execute and it proceeded to remove all nets and all parts. It's a good thing that the UNDO works! I've placed many of my components already. Does this mean I must redo all of that? If anyone can tell me the format of the offending portion of the .DDB file I'm not adverse to using a binary editor on it. This approach is probably way too complex for the average person, though, since it's obviously too complex for the Protel developers themselves. Thanks, Ray Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Common PCB footprint specifications
Everyone, Thanks for all the responses on footprints. This whole issue is pretty sickening actually. Since we produce low quantities of diverse products we have no dedicated PCB layout people. All engineers do their own circuit designs and parts specification and ultimately are expected to do tiny PCB layouts of everything and get them to work. The thing that gets me is that it seems like it would be extremely simple for parts vendors to provide land patterns for their parts along with the mechanical drawings of the parts themselves. Some do but most don't. I just talked to Maxim about this and they said they simply don't provide this information. They recommended IPCSM782. Of course a good percentage of the parts you need are not listed in this document and a lot of them that are there do not match the recommendations of the vendors of the parts. I asked Maxim how they layout their own eval boards since they provide no guidelines and no guidelines exist in IPCSM782. They didn't have an answer but I suspect they rely on rules of thumb and intuition, which is what we end up doing with our designs here most of the time. After enough bad yields and scolding from our PCB fabricators we manage to stumble into something that seems to work. I did find what I thought was a good layout for 0402, 0603, etc. from AVX capacitors. Upon closer inspection, however, I found that their recommended footprints violated their own guidelines given on a different page of the same document. Go figure! Ray Mitchell At 04:59 PM 3/11/2004 +, you wrote: -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 5:36 PM To: [EMAIL PROTECTED] Subject: [PEDA] Common PCB footprint specifications Hello, I'm sure this is a repeat, but is there a simple specification readily available that gives the commonly accepted (if there is such a thing) dimensions for 0402, 0603, ..., SIOC-14, etc., and all the other standard footprints? I don't really want to wade through a bunch of technical stuff to derive all of this myself and I certainly don't want to trust a priori the patterns that come with Protel or any other product. It's really annoying when part manufacturers don't provide these footprints, assuming they are common knowledge. Ray I have accumulated quite a library of such footprints but most of them will have been optimised to suit our in house processes more than following the IPC standards. The supplied Protel IPC land patterns are not too bad, they are certainly a good basis to build your own on. But most libraries stop at the land pattern stage, which is what the IPC are looking to change. A lot of the way the IPC are trying to structure library conventions are along the lines of what I was already doing for years anyway, not because it is good, but because it make life easier for us internally if the naming conventions for footprints already match vision library footprints on placement machines (which then relates to mechanical dimensions as well, as a Murata 16V X7R 0603 will have different dimensions to a Kemet 16V X7R 0603 in same voltage) and other EDA packages we use etc. I especially like the way the new IPC recommendations take account of things like, 0 deg positions in tape or tray, if Protel could also make allowances for rotation on non-polarised chip parts (only use 0,90) to reduce un-necessary head rotations on turret head placers that would be even better as I currently use an in house utility to parse the PP files and check for string matches on footprint part number to identify non-polarised parts and it will replace 360 or 180 values with 0 and 270 values with 90. In DXP I planned to use a parameter for that at SCH level, so I only need to check for one match, but that's another story, no time for documenting or agreeing how this should be done internally yet. Same with pad sizes, I slightly oversize SMT pads in some cases against IPC recommendations (not much) to allow for place tolerances when reducing Z height down pressure, Vac release and place speed, especially on Chip r/c's as well as wave flow direction and so on. Same for connector placement, especially for IDC and connector rows 2.54mm, I sometimes enlarge the pads beyond IPC recommendations in one direction to get the best out of the features on our wave soldering equipment (Vitronics-Soltec with Select-X debridging). If Protel could assign a different footprint for rotation, or side, based on some sort of logical system, then it would make life so much easier to define DFM rules even at SCH level. Perhaps that's worth a new feature request on the DXP forum :) To me a library has to be more than just a symbols collection, or the manual pre-processing required diminishes its value, very little third party libraries do this, so IMO are not worth it. I like the IPC new offerings for library recommendations very much, and would like to see it adopted
[PEDA] Common PCB footprint specifications
Hello, I'm sure this is a repeat, but is there a simple specification readily available that gives the commonly accepted (if there is such a thing) dimensions for 0402, 0603, ..., SIOC-14, etc., and all the other standard footprints? I don't really want to wade through a bunch of technical stuff to derive all of this myself and I certainly don't want to trust a priori the patterns that come with Protel or any other product. It's really annoying when part manufacturers don't provide these footprints, assuming they are common knowledge. Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] The road to DXP, one mans story, warning long post, (was)2004 DXP Looks Great,
gave up with the router in 98/99/DXP almost from the start and decided to waste no more time on it, I use another layout/router package for boards that need it. Works better for me that way, although I have had some boards, using Protel router, pass my desk, that look pretty good to me, but how much time it took to get that way who knows. The above is just some thoughts of mine, Ill skip the temptation to rant about the query system, as my issues with this system is mostly due to my own failings in understanding\attaining the disciplines needed to drive the beast efficiently. John Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] New PC tested with Protel for at least 1 month now...
I'm glad to hear someone has had good luck with ASUS. Some time ago I went through several ASUS 400MHz CUSL2 motherboards, different CPUs, different brands of memory, different power supplies, and everything else to try to stop random crashes. It wasn't just with Protel either. I finally ended up slowing the memory bus down to 100MHz even though everything was spec'd at 133.I'll never touch ASUS again. I was using Win2K. Has anyone had any problems with Protel with Intel motherboards? I've heard their not barnburners but are extremely stable. At 03:19 PM 3/10/2004 -0500, you wrote: I do believe the stability of my new system is that all the peripherals, 24 bit/96KHz sound, USB, 1394, Ethernet, SATA raid controller, ATA raid controller are all on the motherboard the video card was also made by Asus ensuring a trouble free 8X AGP functionality. It even more stable than my old Dual PIII 1 GHz. Also, the 2 X 120 Gbyte Western Digital HDs read write at over 100 Megabytes / second on a continuous basis. I'm sure if I added 1 card to the PCI bus, the boot time would probably double. Additional, I have successfully over clocked this motherboard to 4.1 GHz, though, I don't think it's worth the potential headaches. _ Brian Guralnick - Original Message - From: Tony Karavidas [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, March 10, 2004 12:37 AM Subject: Re: [PEDA] New PC tested with Protel for at least 1 month now... I'm only using a 300 watt power supply and it takes my XP box 25 seconds to boot. (that's a joke!) Seriously though, don't install a bunch of crap on that PC or else the boot time will grow horribly. (And it may not shut down properly...sort of like this WinXP box.) Tony -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Tuesday, March 09, 2004 7:45 PM To: Protel EDA Forum Subject: Re: [PEDA] New PC tested with Protel for at least 1 month now... 2 other things, It completely boots right to the XP password prompt in under 5 seconds. (I didn't think that was possible...) I'm using a 450 watt power supply. _ Brian Guralnick - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, March 09, 2004 10:31 PM Subject: [PEDA] New PC tested with Protel for at least 1 month now... New PC (tested now for 1 month): Mobo: ASUS P4P800 Deluxe, On board stuff: 3.6 GHz Intel CPU. 2GB DDR sdram in dual channel mode. AD1985 - on board sound card, v3630 drivers. Intel 82801ER Serial ATA raid controller with 2 x 120GB SATA WD hds. 3Com gigabit LOM (3C940) Firewire port 8 USB 2.0 ports Parallel Port Serial Port Video AGP: ASUS V9520/TD - GeForce FX5200 (not the best card for extreme high end 3D, but, the 8X agp makes Protel 99se fly.) Drivers - Nvidia direct - 53.03. Current bugs: -sharpness settings mess up after an APPLY. -custom color overlay settings are erased when you swap, or enable / disable the opposite monitor output. -monitor output #2's sync gets disrupted when you right click on the NVidia control panel icon. OS: WinXP Pro. I have yet to see Protel crash, or, Altera's QuartusII 3.1 web edition. In fact, the only crash I've seen yet was in Internet Explorer on some lousy Java code... _ Brian Guralnick Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using Protel 99SE with Xilinx 6.1i Project Navigator
At 06:14 PM 1/14/2004 -0600, you wrote: Ray Mitchell wrote: Hello, In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome. I have done this, but it gets a bit messy. I'm not sure my method is actually any improvement. The only thing I found that worked was VHDL (architectural) netlists. An annoying bug is that P99SE Sp6 will only output one VHDL netlist, then you have to restart P99. If you don't restart P99 each time, it will hang on the netlist step. If you wait half an hour, it outputs 65536 lines of garbage before the valid netlist. But, you get a netlist almost ready for Xilinx isp. You have to manually add the library unisim and the line use unisim.vcomponents to get the use of those library components. You can edit away the _sch extension from all VHDL files made from schematic sheets. You have to manually remove duplicate component declarations for all of the user-created components. This only comes up on sheets where you have placed the same user-created library component multiple times. The rough edges are that P99 wants input and output pads on the top level page for sim and ERC, but Xilinx DOESN'T want pads, it assumes any ports on the top page are pads. Jon Jon, Yes, messy but not as messy as trying to use the ISE 6.1i abomination that they're trying to pass off as a schematic tool. From what you describe it seems like it might be reasonable to write a small program to post-process the Protel VHDL files to massage them into a form that ISE wants. If you don't mind, I'd like some clarification on some of the things you mentioned. When I created XNFs for ISE 3.1i Design Manager in the past I had to create a Protel .PRJ sheet that merely contained Sheet Symbols with Sheet Entries. The actual logic was on the .SCH sheets and was tied together by the .PRJ sheet. I always found it annoying Sheet Symbols were needed since they're not needed when doing a schematic for a board layout. I'm most confused about your last statement and I'm not sure what you're telling me about pads. I've always used them for my FPGAs in the past for XNFs. Are you saying that now I should just use IBUFs and OBUFs as my entry and exit components and not attach IPADs and OPADs at all? I didn't think Protel itself cared anything about IPADs and OPADs since they are not used in board schematics. Am I correct in assuming that you regenerated all of the Protel library components for Xilinx as VHDL files also? Thanks for your response, Ray [EMAIL PROTECTED] Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Using Protel 99SE with Xilinx 6.1i Project Navigator
Hello, In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome. Thanks, Ray Mitchell Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] stackups - Capacitance - Book Recommendation Wanted
There are obviously a lot of analog things to worry about when designing a fast, dense digital board. I fought a large digital board I did through 3 iterations by simply trying different things without fully knowing what I was doing. It eventually worked but I don't know if my next design will! I would appreciate it if someone could recommend some books on high speed board design that cover topics such as stackups, capacitor resonances, trace thickness, and any other important issues. Of course, I would prefer a cookbook approach if possible since I don't want to get into the heavy math of it all if I can avoid it. Thanks, Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance
At 03:44 PM 6/3/2003 -0400, you wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since they are farther apart. My stackup (as mentioned in an earlier post, and repeated below) gives you copper balance, better decoupling, and your signals are still only 1 layer away from a pwr or gnd plane. And since the pwr and gnd planes are effectively the same thing to high frequencies, a signal being next to a pwr plane is the same as that signal being next to a gnd plane. sig gnd1 pwr1 sig sig gnd2 pwr2 sig While we are on this subject, I like to use 0.01 uF caps for decoupling, not the 0.1 uF caps you frequently see on digital circuits. The reason is that 0.01 uF caps have a higher self-resonance frequency than 0.1 uF caps, which makes them better able to decouple the high-speed transients that are so common in today's circuits. Also, 0.01 uF caps are less expensive and take up less space (0805 vs. 1206). First, my experience regarding layout is minimal at best since I seem to exhaust all the wrong ways first. I once took a class in multilayer layout and was told that the capacitance between the power/ground planes themselves was sufficient for decoupling high frequencies and that adding capacitors could cause tuned circuits and troublesome resonances. I'm simply asking, any views on that theory? Ray * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] How to copy Protel schematics into other documents
Everyone, Several months ago I posted to this newsgroup requesting information about simply using Protel 99SE as a nice schematic drawing tool with the ultimate goal of being to incorporate the drawings as an imbedded objects in other applications such as Microsoft Word. I only wanted the schematic part and not the border and extra space that might surround a small drawing on a large sheet. At the time I either misunderstood the responses or somehow got the impression that it couldn't be done reasonably. As a result I looked around for other schematic applications that would permit this. I stumbled upon CircuitMaker 2000, which will let you export drawings as a .wmf files. However, in my opinion it has the absolute worst GUI interface I've ever encountered in modern times (yet they actually charge real money for this product). As a result I decided to fool around with Protel some more. I found the following, which many or all of you probably already know. 1. To copy and paste the entire drawing sheet simply select the portion of the schematic you want and copy it to the clipboard using ctrl-Insert (or equivalent). Then go into your other application and paste it there. 2. This still does not address the issue of the sheet border being part of what gets pasted or the issue of empty space surrounding your drawing. To get around this: A. Paste the desired section of the schematic onto the lower-left corner of a new Protel schematic sheet by itself. B. Double-click the border of the new sheet to bring up the Document Options dialog box. C. In the Document Options dialog box uncheck all the boxes you don't want on your copied drawing, such as Show Border and Visible Grids. D. Check the Use Custom Style box and enter the dimensions of your drawing without leaving excessive space around it. E. Click the OK button and copy and paste as described previously. Neat isn't it! My wish list on this is that: A. Rather than the pasted object being a picture, it would be whatever is necessary such that double-clicking it within in the target application would reopen the original Protel schematic for editing. B. It would be nice if within Protel you could merely drag the edges of a sheet to a new size rather than having to go to the Document Options dialog box and actually type in the new dimensions. Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Long overbars on printed output
Hello, I'm using Protel 99SE w/SP6 on Windows 2000. Many of my schematic symbols (from the Protel Libraries) have overbars on the low-true signal names. When viewed on my monitor they look fine but when I print the page all of the overbars become several inches long, extending out of the entire symbol itself in many cases. This totally destroys and confuses the look of the printed schematic. I'm using an HP 4MV in landscape mode for all printing. I imagine this must have something to do with a printer font problem, although everything else I print other than Protel schematics comes out fine. Any ideas or specifics on how to remedy this? How about if someone invents something, maybe we should call it WYSIWYG, so that what you see is what you get:-) Thanks, Ray Mitchell [EMAIL PROTECTED] * Tracking #: BAB253005421794DB82EBAD5B2886258B8073B1B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Long overbars on printed output
Tony, My printer is configured as a simple Ethernet IP printer. Several users here tried the HP Jet Admin stuff but it never worked properly. I'm not clear on the printer driver business, though. If a printer is networked does each user still need to fool with printer drivers on their individual machines or is the printer driver somehow now attached to the printer itself? Actually, the long overbar problem just started. I'm not sure when, however. I'm beginning to wonder if Win2K SP3 might not have caused the problem, or possibly one of the other multitudinous periodic updates that Microsoft comes up with. Ray At 11:38 AM 9/5/2002 -0700, you wrote: Hi Ray, The long overbars used to be a problem (for me) quite a while ago. I'm not sure when it was fixed, but I'm looking at several examples of 11x17 prints I did with my HP4MV and there are no problems. Possibly the printer driver??? I have my 4MV setup on ethernet, so I have to print to an IP address using HP's oddball driver. I used to have more problems with Win2K and the older jetadmin s/w, but now I'm running XPPro and for some reason the new jetadmin for XP seems to be much smarter. (I'm sure I could have installed the new jetadmin on W2K but I didn't for unknown reasons) There are a zillion parameters to the printer driver. You might want to mess around with them. Font substitution table, output protocol, etc. I don't know if any have an effect on what you're seeing. Tony -Original Message- From: Ray Mitchell [mailto:[EMAIL PROTECTED]] Sent: Thursday, September 05, 2002 11:09 AM To: Protel EDA Forum Subject: [PEDA] Long overbars on printed output Hello, I'm using Protel 99SE w/SP6 on Windows 2000. Many of my schematic symbols (from the Protel Libraries) have overbars on the low-true signal names. When viewed on my monitor they look fine but when I print the page all of the overbars become several inches long, extending out of the entire symbol itself in many cases. This totally destroys and confuses the look of the printed schematic. I'm using an HP 4MV in landscape mode for all printing. I imagine this must have something to do with a printer font problem, although everything else I print other than Protel schematics comes out fine. Any ideas or specifics on how to remedy this? How about if someone invents something, maybe we should call it WYSIWYG, so that what you see is what you get:-) Thanks, Ray Mitchell [EMAIL PROTECTED] ** ** * Tracking #: BAB253005421794DB82EBAD5B2886258B8073B1B * ** ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Long overbars on printed output
Yes, that's how I printed the bad ones. I just tried it again but opened them all first and it worked correctly. Should Protel classify this as a feature and charge more for it, or as a bug and fix it (or maybe just punt)? Thanks to everyone for your help. Ray Mitchell At 12:36 PM 9/5/2002 -0700, you wrote: I just tried that, and it works ok for me. -Original Message- From: Madhu Annapragada [mailto:[EMAIL PROTECTED]] Sent: Thursday, September 05, 2002 12:22 PM To: Protel EDA Forum Subject: Re: [PEDA] Long overbars on printed output I saw this problem when printing multi-sheet schematics with only one of the sheets open. The problem would disappear if I opened all the sheets associated with the schematic before printing. Madhu I'm using Protel 99SE w/SP6 on Windows 2000. Many of my schematic symbols (from the Protel Libraries) have overbars on the low-true signal names. When viewed on my monitor they look fine but when I print the page all of the overbars become several inches long, extending out of the entire symbol itself in many cases. This totally destroys and confuses the look of the printed schematic. I'm using an HP 4MV in landscape mode for all printing. I imagine this must have something to do with a printer font problem, although everything else I print other than Protel schematics comes out fine. Any ideas or specifics on how to remedy this? How about if someone invents something, maybe we should call it WYSIWYG, so that what you see is what you get:-) ** ** * Tracking #: FE1E3D62D152F64E8857395349EF6331AC6BF878 * ** ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Print/Preview Problem
I'm using Protel 99SE with SP6 on Win2K. I can create a .PPC from a .PCB, play with it, print it out, etc. without a problem. However, when I go to another project then return to my .PPC, or close Protel then reopen and return to my .PPC, although the .PPC is still there it appears empty. I do a Browse PCB Print and it still lists all the correct layers I originally set up, but they simply don't appear. I do a Rebuild but nothing happens. Finally, I discovered that if I do a Process PCB the selected layers reappear but the page has been shrunk down to a very tiny size. I must change the view to get it back to where I started. Is this a bug or a feature or am I simply doing something wrong? Thanks, Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PCB view from bottom of board??
Hello, Is there any way within Protel 99SE's PCB tool to cause the view to be from the bottom of the board rather than from the front? Thanks, Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Merging libraries?
(Protel 99SE) Over the years I've created many Schematic and PCB libraries and as fate (and sloppy programming practice) would have it, I've ended up with many duplicate or semi-duplicate parts in different libraries. I'd like a reasonable way to merge everything into one library. Ideally, if a duplicate part were found I'd be given the option of which one to keep. Is this asking too much? Thanks, Ray Mitchell SPAWAR Systems Center San Diego, Ca. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Getting a .wmf figure to reload automatically
Hello, I'm using Protel 99SE/SP6 on Win2k. I have created several custom drawing templates for schematics and some of them contain a reference to a .wmf file containing our company logo. When I first created the templates the logo showed up fine, just like I wanted. However, when I shut down then bring everything back up all that shows up in place of the logo is some text claiming the .wmf file is not available. If I fool around with things (I'm not exactly sure what I actually do since it's more trouble than it's worth) I can get the logo to reappear, but the next time I open up the project the logo is gone again. I've tried placing the logo file in the .ddb file as well as placing it in several different directories but in all cases it simply won't appear on the appropriate sheet consistently. Any suggestions? Thanks, Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Exporting a schematic as a simple jpg, bmp, gif, etc.
Hello, I would like to use Protel 99SE to draw some schematics with the intent of eventually using these schematics simply as drawings, as if I had drawn them with Visio, Corel, Micrographics, Paintshop, or some other generic drawing program. I would then like to insert these drawings into Word, Wordpad, or whatever. Does anyone have any insight into doing this? Thanks, Ray Mitchell SPAWAR Systems Center San Diego, Ca. 92152 (619)553-5344 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Consolidating Schematic/PCB Libraries
Over time I have ended up with several different versions of the same schematic library as well as several different ones. As I look through them I notice that some contain different versions of a part but with the same part number. In addition, the same library might contain different parts having the same part number. Although I agree that I should have let my libraries get into this mess, the fact is that they are already in it. My question is twofold: 1. Is there any automated way to merge multiple libraries into one, hopefully with notification of duplicate names? 2. Is there any automated way to detect and eliminate, with notification, duplicate names from the same library? Along the same lines, is such a tool available for PCB libraries too? Thanks, Ray Mitchell [EMAIL PROTECTED] Ray Mitchell SPAWAR Systems Center San Diego, Ca. 92152 (619)553-5344 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Using equations rather than logic gates?
Is there a (reasonable) way to enter equations into the Protel 99SE schematic tool rather than placing logic symbols? Usually the logic symbols are fine but in some cases equations seem like a more straightforward approach. I'd like to be able to mix the two. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Keystroke macro recorder?
Is there a macro recorder available for Protel 99SE? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
