Thanks again everyone for the response. Again my lack of experience is showing. Oh well, I have to learn some how. I hope that every body has a nice weekend.....
-----Original Message----- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Friday, January 17, 2003 4:13 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 . Andrew, my understanding is that he is talking of the component placement DRC check. It checks the area bounding all portions/layers of the land pattern to the bounding area of the next land pattern. It isn't a copper check but a component to component clearance check. Like myself or a number of others, you probably have it turned off since early in the P99 days. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com > -----Original Message----- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Friday, January 17, 2003 12:05 PM > To: Protel EDA Forum > Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE > SP6 . > > > Okay, call me dumb, but I am having a hard time understanding > how the DRC > even comes into play, since the clearance constraint is, by > definition, a > constraint on copper layers only. Since the silkscreen is not a copper > layer, the clearance constraint shouldn't even be invoked... > > What am I missing in this "equation"? > > aj > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
