Hello Michael,
Try placing a net label on the unused pin in the schematic. For instance
FPGA_NC001, FPGA_NC002 etc. If I recall it correct this wil result in a
netname for the unused pin. Test it before you fill the schematic with a lot
of labels. At the moment I am not in the situation to check
:[EMAIL PROTECTED]]
Sent: Thursday, April 25, 2002 6:47 PM
To: '[EMAIL PROTECTED]'
Subject: [PEDA] FBGA fan outs with no net name
I am working with a design that has a large FBGA and each pad on this part
has a via fanout from it. Not all the pads are assigned a net name on this
FBGA. The pins
PROTECTED]
Sent: Thursday, April 25, 2002 4:30 PM
Subject: Re: [PEDA] FBGA fan outs with no net name
Dan,
have you found some certain condition where the Short circuit
constraint works? Previously most of us have thought it was broke (a bug),
because we could not get it to do anything correctly
PROTECTED]]
Sent: Friday, April 26, 2002 8:42 AM
To: Protel EDA Forum
Subject: Re: [PEDA] FBGA fan outs with no net name
I'm not sure how to respond. I use the short ciruit rule for
standard DRC
and it has not given me problems. I must admit, however,
that I pay more
attention
] FBGA fan outs with no net name
I am working with a design that has a large FBGA and each pad on this part
has a via fanout from it. Not all the pads are assigned a net name on this
FBGA. The pins that are not used have no net name and therefore the pad has
no net name but I am still giving it a fan
I am working with a design that has a large FBGA and each pad on this part
has a via fanout from it. Not all the pads are assigned a net name on this
FBGA. The pins that are not used have no net name and therefore the pad has
no net name but I am still giving it a fan out with a small connection
us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.
-Original Message-
From: Michael Biggs [mailto:[EMAIL PROTECTED]]
Sent: Thursday, April 25, 2002 3:47 PM
To: '[EMAIL PROTECTED]'
Subject: [PEDA] FBGA fan outs with no net name
I am working with a design that has
-
From: Michael Biggs [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Thursday, April 25, 2002 3:47 PM
Subject: [PEDA] FBGA fan outs with no net name
I am working with a design that has a large FBGA and each pad on this part
has a via fanout from it. Not all the pads are assigned a net name
, April 25, 2002 4:09 PM
To: Protel EDA Forum
Subject: Re: [PEDA] FBGA fan outs with no net name
Yes. In Design Rules go to Other tab and select Short
Circuit Constraint.
When you pull it up, change both of the Objects Filtered
boxes to say Net
Class rather than Whole Board and select
