[PEDA] Padstack

2001-11-29 Thread Wesley Webb
Hi, Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want the voltage to see them before the leg of

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
Hi Wesley, This is what I would do, if I understand what you described... Make a physical clearance in the inner plane where you put the via so it will not connect... If you are using power/gnd planes and not polygon fills then you need to just put a fill or pad in the area on the negative

Re: [PEDA] Padstack

2001-11-29 Thread rlamoreaux
Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want the voltage to see them before the leg of the

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 10:55 AM 11/29/01 -0500, Wesley Webb wrote: Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 08:40 AM 11/29/01 -0800, Brooks,Bill wrote: Make a physical clearance in the inner plane where you put the via so it will not connect... If you are using power/gnd planes and not polygon fills then you need to just put a fill or pad in the area on the negative layer where the via is, and make

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
That DOES work if its a Pad and not a Via...(only because you can't uniquely identify a single via other than by its size and hole if they were different than all the rest of the vias on the board. Place a free PAD out there and call it '1', connect the net to 'gnd'. Then you can define a rule

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
Nicely put ABD... I didn't attempt to address the cap placement issue because I am not familiar with his design...But as a general rule I put bypass caps as close as I can to the lead of the IC that needs decoupling and drop a via to the ground plane as close as possible to the CAP foot print

Re: [PEDA] SV: Phatom polygons another tip

2001-11-29 Thread Jenkins, Charlie
I find that after the polygon pours and dead copper is removed, there are areas that I would like to keep the copper that was removed because no connection to a net could be made. In those cases I use a net seed like a via or little fill patch with a net assigned to it. I place the patch and

Re: [PEDA] Protel and Netmeetink plus Acces database questions.

2001-11-29 Thread Watnoski, Michael

[PEDA] Seeking Popular or Standard Footprint for Surface Mount LEDs

2001-11-29 Thread Leonard Fischer
We are considering changing from through-hole to surface mount LEDs in a design that is currently at prototype stage. Is there a popular/standard footprint that we could use that would let us choose LEDs from a variety of manufacturers? Either in the Protel libraries or just as a

[PEDA] Blind and buried via's Mayhem

2001-11-29 Thread Jeff Stout
1. Can I use a hole pair that goes through the prepreg, but does not go through the core material above or below that level? I just don't see how it can be manufactured. 2. Does anyone have an opinion on using BB vias in a PCB for hi temperature hi vibration environment? Jeff Stout * * * * *

Re: [PEDA] Seeking Popular or Standard Footprint for Surface Mount LEDs

2001-11-29 Thread Frank Gilley
Len, While there surely must be more shapes, sizes, and mountings for LEDs than almost any other component, there are quite a few SMT LEDs available in a variety of standard footprints like 0603, 0805, 1206, 1210, and SOT-23 just to name the more common ones. SMT LEDs do not lend themselves

Re: [PEDA] Blind and buried via's Mayhem

2001-11-29 Thread Jeff Stout
[snip] At 03:53 PM 11/29/2001 -0600, Jeff Stout wrote: 1. Can I use a hole pair that goes through the prepreg, but does not go through the core material above or below that level? I just don't see how it can be manufactured. No. At least not to my knowledge. My understanding of the

Re: [PEDA] Blind and buried via's Mayhem

2001-11-29 Thread Ted Tontis
Have you considered using micro vias? You can place them in the pads and solder right over them, you will never see them on the top layer. Also laser drilling is less expensive than mechanical drilling. Regards, Ted -Original Message- From: Jeff Stout [mailto:[EMAIL PROTECTED]] Sent:

Re: [PEDA] Blind and buried via's Mayhem

2001-11-29 Thread Frank Gilley
At 05:16 PM 11/29/2001 -0600, Jeff Stout wrote: So in a PCB, with a stack up like: T --C-- 1 --P-- 2 --C-- 3 --P-- 4 --C-- B (Typical 6 layer/3 core stackup) It's only possible to manufacturer: T - 1 T - 3 T - B 2 - 3 2 - B 4 - B Yes, you cannot connect layers 1 2 (as you have them notated)

Re: [PEDA] Padstack

2001-11-29 Thread Geoff Harland
Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want the voltage to see them before the leg of the

Re: [PEDA] Padstack

2001-11-29 Thread Michael Beavis
Place a free PAD out there and call it '1', connect the net to 'gnd'. Then you can define a rule for plane connect and set the power plane connect style filter kind to PAD and and look for free pad 1 and set the Rule Attributes to No Connect. This will make a clearance around the pad

Re: [PEDA] data for 3D footprints

2001-11-29 Thread Ian Wilson
On 10:41 AM 30/11/2001 +1200, Liane Williams said: Hi all, I teach first year students electrical drawing with CAD. We create schematics and pcbs (single and double-sided only), to give them the basic concepts and to enable them to use the software to help in other areas of their courses

Re: [PEDA] data for 3D footprints

2001-11-29 Thread Geoff Harland
I teach first year students electrical drawing with CAD. We create schematics and pcbs (single and double-sided only), to give them the basic concepts and to enable them to use the software to help in other areas of their courses (electronics etc). We have just upgraded to Protel 99SE after

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
Very good point! Michael, In fact the diligence in reviewing the macros is key if you want to retain things like mounting holes that have a connection to ground, or Fiducials that are named components in your design...most of us do not include such things in the schematic... the macros created

Re: [PEDA] Protel and Netmeetink plus Acces database questions.

2001-11-29 Thread Abd ul-Rahman Lomax
At 07:45 PM 11/29/01 +0100, David Ponížil wrote: Is somethink strange in Acces database file format??If you chose this ddb format isn't groving and grovingfrom little PCB file is quickly BIG file.Any experience or comments?Empty recycle bin inside ddb doesn't help. Emptying the recycle bin

Re: [PEDA] SV: Phatom polygons another tip

2001-11-29 Thread Abd ul-Rahman Lomax
At 01:46 PM 11/29/01 -0500, Jenkins, Charlie wrote: I find that after the polygon pours and dead copper is removed, there are areas that I would like to keep the copper that was removed because no connection to a net could be made. Why? In those cases I use a net seed like a via or little

Re: [PEDA] Blind and buried via's Mayhem

2001-11-29 Thread Abd ul-Rahman Lomax
The responses in this thread, quite appropriately, have focused on standard printed-circuit board technology. However, that is not the universe. I'm working now with a co-fired ceramic module technology that has only one restriction on vias: (1) a via stack should not be more than 20 layers

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 11:27 AM 11/30/01 +1100, Michael Beavis wrote: Free pads allow for more powerful design rules to be employed but it is possible to lose them when synchronising from SCH if care is not taken. If the 'Delete component' option is selected in the sync process and the free pads do not appear on the