Re: [PEDA] Fw: Altium - Think it, Design it, Build it!

2001-08-07 Thread Abd ulRahman Lomax
Here is my reaction to Altium. I am rather desperately hoping it is a hoax Altium sounds like a name for a company that is trying to imitate something modern without quite making it. It's very nineties. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message:

Re: [PEDA] Spam trawlers in this group

2001-08-25 Thread Abd ulRahman Lomax
At 11:13 AM 8/24/01 -0500, Frank Gilley wrote: Just curious, but lately I have been getting spammed from what would appear to be email addy trawlers in this group. Anyone else getting spam from .au's? after posting here? This is not the usenet, surely we don't have to have addy trawlers in our

Re: [PEDA] Altium Total Support Brochure

2001-12-05 Thread Abd ulRahman Lomax
At 03:13 PM 12/5/2001 -0500, Brian Guralnick wrote: Usually when I purchase any software, or hardware, from any other vendor, I can get support for free almost indefinitely without having to renew some sort of membership. Actually, indefinite support is, in my experience, the exception

Re: [PEDA] Altium Total Support Brochure

2001-12-05 Thread Abd ulRahman Lomax
At 03:51 PM 12/5/2001 -0500, Bagotronix Tech Support wrote: I think that free support should be maintained for old products forever, as long as there is no cost associated with maintaining that free support. No cost support is possible. It consists of downloadable service packs for the

Re: [PEDA] Footprint pads moving during or after copy/paste/move processes.

2002-04-02 Thread Abd ulRahman Lomax
At 06:05 PM 4/1/2002 +1000, Ian Wilson wrote: Harmless unless you actually have unlocked the component - and then the classic missing pad can be generated. Select a net (or connected copper), which includes components with unlocked primitives. Delete the selection and away go the pads. This

Re: [PEDA] pad jump

2002-04-02 Thread Abd ulRahman Lomax
At 03:11 PM 4/1/2002 -0800, Dennis Saputelli wrote: i am reasonable certain that my mysterious pad jump happened right after and as a possible consequence of a File Save As It would be rather surprising if that was not merely a coincidence. File Save As does not have any effect on the file

Re: [PEDA] Out-of-workspace items (ex Extended selection spells)

2002-04-02 Thread Abd ulRahman Lomax
At 12:43 AM 4/3/2002 +1000, Geoff Harland wrote: I understand what you are saying, but I do wonder how much space you want while you are moving items about; after all, 100 inches by 100 inches is a pretty big area :) (i.e. much much larger than any PCB which I am ever likely to be called upon to

Re: [PEDA] Excluding a component footprint from a DRC check

2002-04-05 Thread Abd ulRahman Lomax
At 01:08 PM 4/5/2002 +0100, [EMAIL PROTECTED] wrote: Is there any way of excluding a component footprint from a DRC check? You can set special rules for footprints, components, component classes, or specific footprint pads, from some DRC checks, particularly Clearance Constraint and a series

Re: [PEDA] Selection when in single layer mode

2002-04-08 Thread Abd ulRahman Lomax
Unfortunately, single-layer mode has not be implemented in the best way. It was apparently designed to be used for viewing, not really for editing. The solution might be for Protel to disable selection entirely in single-layer mode, or make single-layer mode edit the same as having the same

Re: [PEDA] flies in the archive

2002-04-08 Thread Abd ulRahman Lomax
At 08:23 AM 4/8/2002 -0700, Brad Velander wrote: Ted, they are in the protel-users group. You get access to them by clicking the files menu on the right hand side of the screen. Just checked and they are definitely there. That is an older archive. There is a current archive kept on

Re: [PEDA] flies in the archive

2002-04-09 Thread Abd ulRahman Lomax
At 11:49 AM 4/9/2002 +1000, Ian Wilson wrote: Brad is correct - the original enquiry was not about archives but about the servers and basic scripts. As Brad said, these are stored in the Files store of the yahoo users group. Not really important, yes, the original inquiry was about those

Re: [PEDA] Excel to Protel Schematic

2002-04-10 Thread Abd ulRahman Lomax
At 04:27 PM 4/8/2002 -0700, Shuping Lew wrote: I try to add IC power table to Schematic... Others gave good advice as to how to make a table in Schematic. So I'm responding to the basic idea of making an IC power table. It is essential, of course, that actual connections be made to power pins,

Re: [PEDA] library orientation of designators and types ??

2002-04-10 Thread Abd ulRahman Lomax
At 09:34 AM 4/9/2002 +0200, Edi Im Hof wrote: I noticed this also. I just hit the spacebar fout times (rotate 360°) and everything is fine. Clearly a bug. Actually, a feature. Here is why this happens, I think: Protel assumes, when you are placing parts, that you will want the relative

Re: [PEDA] flies in the archive

2002-04-10 Thread Abd ulRahman Lomax
Sorry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: *

Re: [PEDA] library orientation of designators and types ??

2002-04-10 Thread Abd ulRahman Lomax
At 09:10 AM 4/10/2002 -0700, Peter Bennett wrote: Sounds like a good theory... However, [...] Normally, I try to thoroughly verify what I report. Sometimes, however, I am unable to do that. Like now. So what I wrote should be treated as nothing more than an unproven hypothesis. If I had time,

Re: [PEDA] BMP2PCB Question (slightly off topic)

2002-04-12 Thread Abd ulRahman Lomax
At 02:06 PM 4/12/2002 -0700, Embedded Matt wrote: Thanks to a tip from the FAQ for this mailing list, I got a copy of the BMP2PCB that I want to use to add my company logo to a PCB. I noticed that the tracks generated are 1 mil. Do board houses typically complain about these 1 mil tracks or do

Re: [PEDA] FW: Access violation -- Is it a Protel bug?

2002-04-17 Thread Abd ulRahman Lomax
At 03:23 PM 4/16/2002 -0700, Shuping Lew wrote: I tried to load a netlist file to PCB. It has over 1,100 components. I receiced a warning of access violation. It says: Access Violation at address OF086CC6 module Exception Occurred in PCB: Netlist... First of all, yes, I would strongly

Re: [PEDA] FW: Access violation -- Is it a Protel bug?

2002-04-17 Thread Abd ulRahman Lomax
At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote: ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. If the problem was, for example, that you had an incorrect scope such that some net names were duplicated between sheets even

Re: [PEDA] transparent backgrounds ??

2002-04-17 Thread Abd ulRahman Lomax
At 02:13 PM 4/17/2002 -0500, Robison Michael R CNIN wrote: it was mentioned here a while ago that if i had hardcopy artwork, i could scan it, get it sized appropriately, and add it as a transparent background for me to use as a guide for interactive routing. is this correct? There are several

Re: [PEDA] FW: Access violation -- Is it a Protel bug?

2002-04-17 Thread Abd ulRahman Lomax
At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote: I use some notes on every schematic project. So I created a schematic symbol named note for it. To avoid the warning of missing footprint, I also created a footprint named blank to associate with that symbol. I think there is a better way. You can

Re: [PEDA] Tango to Protel Translator

2002-04-18 Thread Abd ulRahman Lomax
At 05:33 PM 4/17/2002 -0500, Jon Elson wrote: BUT, this applies ONLY to PCB, not schematic. ... I still don't know of a way to do it Tango Schematic can be read by Accel PCAD schematic (since that is the descendant program) and PCAD schematic is convertible to Protel Schematic through the

Re: [PEDA] dual monitors

2002-04-18 Thread Abd ulRahman Lomax
At 07:36 AM 4/18/2002 -0700, Graham wrote: At a recent Protel 99SE training session by Altium, I heard mention of the use of dual monitors in a single instance of Protel. Does anyone know how this is set up? It would be great to view two full-screen documents simultaneously. Thanks. Windows

Re: [PEDA] net connections for a fill ?

2002-04-18 Thread Abd ulRahman Lomax
At 09:41 AM 4/18/2002 -0500, Robison Michael R CNIN wrote: thanks for responding. but i'm not exactly sure about what you mean when you say polygon planes don't connect to other nets. is the fill connecting to every thru- hole within its boundaries? Yes. A fill is a bit misnamed. It is

Re: [PEDA] changing electrical type

2002-04-18 Thread Abd ulRahman Lomax
At 10:07 AM 4/18/2002 -0500, [EMAIL PROTECTED] wrote: Is there anyway I can change the electrical type of a pin to one that is not listed in the drop down menu? I would like to put an open drain on one of the pins. I rather doubt that there is a way. It would have to be in some kind of system

Re: [PEDA] integrating effort ?

2002-04-19 Thread Abd ulRahman Lomax
At 08:33 AM 4/19/2002 -0500, Robison Michael R CNIN wrote: [...] the problem is that its a 10 layer board with very complex polygon pours, and everything must match closely with some legacy raster images of the layers. [...[ management asked me if there was anything i could do to speed the job

Re: [PEDA] dual monitors

2002-04-19 Thread Abd ulRahman Lomax
At 10:30 PM 4/18/2002 -0400, Brian Guralnick wrote: When you install the matrox drivers, you must select 'Install enhanced multimonitor support'. Once in windows, in your advanced display control settings, for multimonitor mode, you muse select different resolution # of colors foe each

Re: [PEDA] integrating effort ?

2002-04-19 Thread Abd ulRahman Lomax
At 08:51 AM 4/20/2002 +1200, Simon Peacock wrote: your best bet is to do a round the world processing.. that way the board can be worked on 24 hours a day by people in different time zones :) .. but expect to pay through the nose :) I did this with a job which was more complex than what Mr.

Re: [PEDA] IPL netlist to Protel

2002-04-22 Thread Abd ulRahman Lomax
If a translator cannot be found, it is not terribly difficult to massage almost any netlist format into Protel form, unless the format is binary instead of text. Sometimes one can use just a word processor, but if this list is not organized by net, a spreadsheet like Excel can help with

Re: [PEDA] PADS translation error

2002-04-22 Thread Abd ulRahman Lomax
At 03:26 PM 4/22/2002 -0400, [EMAIL PROTECTED] wrote: Hi all, I just tried to import a PADS ascii pcb and while some layers and fills showed up, only two components came across. I received the following errors in a report file -Load Errors : 1612 -Expected number in line: 4518 at position 0

Re: [PEDA] dual monitors

2002-04-23 Thread Abd ulRahman Lomax
At 09:52 PM 4/19/2002 -0400, Brian Guralnick wrote: | I'll look into this, it may prevent the boot messages, etc. from spanning, | though that is a minor annoyance. | It does. Yes, it does, but it causes other problems. Six of one and a half dozen of the other. No time to write about this

Re: [PEDA] Power plane clearance rule

2002-04-23 Thread Abd ulRahman Lomax
There is another problem with this rule If I am correct, it is indeed, a hole clearance. But true clearance will be about 3 mils less, more or less, because the holes are drilled oversize so that 1.5 mils of plating (1 oz) will bring it back to the specified size. That is a conductive

Re: [PEDA] Tango to Protel Translator

2002-04-23 Thread Abd ulRahman Lomax
At 02:11 PM 4/18/2002 -0500, Jon Elson wrote: Abd ulRahman Lomax wrote: At 05:33 PM 4/17/2002 -0500, Jon Elson wrote: BUT, this applies ONLY to PCB, not schematic. ... I still don't know of a way to do it Tango Schematic can be read by Accel PCAD schematic (since

Re: [PEDA] New rules?!

2002-04-23 Thread Abd ulRahman Lomax
At 09:16 AM 4/23/2002 +0100, Gareth Bradley wrote: Hi, I was wondering if it is possible to stop Protel placing vias under /any/ components as the only method of manufacture I have is pin and hole vias. Protel places vias under PH components (which I'm not /so/ bothered about) but also under

Re: [PEDA] Shortened Designator on Silkscreen

2002-04-24 Thread Abd ulRahman Lomax
At 11:30 AM 4/23/2002 -0700, JaMi Smith wrote: Most of these boards are built in house, but the error rate on stuffing components (the wrong ones in the wrong locations) is very high and the trouble-shooting time to find these assembly errors is exhorbinate, so I really do need the silkscreen

Re: [PEDA] Ground plane floods on top and bottom of PCB

2002-04-24 Thread Abd ulRahman Lomax
At 12:14 PM 4/24/2002 -0700, Afshin Salehi wrote: Hello all, Currently on PCB's I flood the top and bottom layers with a ground plane after routing. I've started doing that on certain boards, particularly fine-pitch SMT boards. It can make a good 6-layer stackup, with power and

Re: [PEDA] Importing a large image file into Protel PCB

2002-04-25 Thread Abd ulRahman Lomax
At 11:05 AM 4/25/2002 -0400, Jim Vegh wrote: I have search all over the web and the previous forum posts and cannot find bmptopcb anywhere. There is a program which was donated to the user's group in the filespace for [EMAIL PROTECTED]

Re: [PEDA] Print preview bug on Arcs

2002-04-25 Thread Abd ulRahman Lomax
At 02:58 PM 4/25/2002 +0100, Michael Binning wrote: Dave, I have just tried creating a simple design using tracks in arc mode, as a test. Got to print preview OK, but as soon as I hit the print button, bye bye Protel. Locked solid. The problem may be file-specific, so it is crucial to save a

Re: [PEDA] FBGA fan outs with no net name

2002-04-29 Thread Abd ulRahman Lomax
The technique to automatically assign a net to a single pin has already been given. (But note that if the include single-pin nets is not checked next time net information is transferred, this will be lost.) The behavior of the autorouter may not be as desired, however; of course this only is

Re: [PEDA] recovering data

2002-04-30 Thread Abd ulRahman Lomax
At 12:53 PM 4/30/2002 -0400, Bagotronix Tech Support wrote: Since Protel DDBs are so huge now, fitting a large project on one CD-R might be a problem. Protel DDBs get large if one does not empty trash and compact the database. The latter is the most important and the least visible problem, the

Re: [PEDA] mirroring or flipping a PCB (was:...)

2002-05-01 Thread Abd ulRahman Lomax
At 03:45 PM 4/30/2002 -0700, Mira wrote: The meaning in Pcad is that you get all layers swapped. Top goes to bottom, silk top - to silk bottom. So it's like looking at the PCB from the bottom side (or routing as the bottom side it your top side). There are three possible aspects to mirroring and

Re: [PEDA] Acrobat Reader to Protel sw

2002-05-01 Thread Abd ulRahman Lomax
At 08:57 AM 5/1/2002 -0700, Tony Karavidas wrote: No, PDF is a completely foreign file format. I don't imagine ANY EDA tool reads PDF files and makes use of the 'information within. Right. However, there may be a path to get some data in. Protel will import DXF, and there are, I understand,

Re: [PEDA] mirroring or flipping a PCB (was:...)

2002-05-03 Thread Abd ulRahman Lomax
At 03:00 PM 5/1/2002 -0700, Mira wrote: Does anybody know how expensive Phoenix will be? I'm not sure that Altium even knows for sure. But they have announced that pricing will be in line with current pricing, i.e., $7995 for 99SE full regular price. There are often sales and specials for

[PEDA] Current virus danger

2002-05-03 Thread Abd ulRahman Lomax
I have been notified by a subscriber to this list that he received what is probably a copy of one of the W32.Klez viruses, and that the mail appeared to be from me. This virus is known to spoof outgoing mail addresses, and it is quite unlikely that I am infected -- though it is remotely

Re: [PEDA] Want to buy 16-bit Protel w/License

2002-05-03 Thread Abd ulRahman Lomax
At 05:21 PM 5/1/2002 +, [EMAIL PROTECTED] wrote: I am interested in purchasing Protel PCB/Schematic Software with license. Prefer Protel 98 or newer. For the information of our readers, older Protel licenses which have not been used for upgrade are eligible for upgrade pricing. Right now,

Re: [PEDA] propagate net

2002-05-03 Thread Abd ulRahman Lomax
At 05:49 PM 5/3/2002 +0200, Rene Tschaggelar wrote: I have unassigned tracks (no net) and would like to proagate the connected net. In schematic there is a 'design/update pcb' that has a checkbox for 'Assign net to connected copper'. That somewho does not appear to work. It should. It is

Re: [PEDA] All Servers gone

2002-05-03 Thread Abd ulRahman Lomax
At 11:29 AM 5/3/2002 -0600, Cam Andruik wrote: Well this is wierd. Yesterday Protel worked fine. Today I start it up and it will not open a database. I have no Servers installed. If I add them, the next time I start Protel they are all gone again! Anyone ever seen this before? Not this.

Re: [PEDA] propagate net - solved, thanks

2002-05-06 Thread Abd ulRahman Lomax
At 01:42 PM 5/4/2002 +0200, Rene Tschaggelar wrote: Thank to all for these quick replies. The netlist manager solved it. I didn't try to propagate through unassigned vias, since they usually don't pick up the changes in net assignment. So I did repeat {assign, place via} until all nets were

Re: [PEDA] mirroring or flipping a PCB (was:...)

2002-05-06 Thread Abd ulRahman Lomax
At 10:06 AM 5/4/2002 +1000, Ian Wilson wrote: On 01:03 PM 2/05/2002 -0400, Abd ulRahman Lomax said: ..snip.. I do understand that the Protel training, with Mr. Wilson, is quite good Not me - I do not do any Protel training. Maybe some other Mr Wilson :-) Ian Wilson Yes, Rick Wilson

Re: [PEDA] recovering data

2002-05-07 Thread Abd ulRahman Lomax
At 09:38 AM 5/7/2002 -0500, David VanHorn wrote: Stop! Don't confuse the terms! I'm not confused. This has gotten a tad out of hand. The subject of this list is Protel software, not RAID systems or whether person A or person B is or is not confused. A RAID discussion is peripherally

Re: [PEDA] deleting a string

2002-05-10 Thread Abd ulRahman Lomax
At 02:00 AM 5/10/2002 -0700, Mira wrote: Ian, I use S-A and everything is selected. No hidden layers. Even though the strings on all layers could not be deleted. The strings are definitely selected and could be moved. E-D doesn't work. S-A selects everything. I checked this on all layers. E-L

Re: [PEDA] round PCB?

2002-05-13 Thread Abd ulRahman Lomax
At 12:22 PM 5/13/2002 -0500, Jon Elson wrote: If you do autoroute, you need to make the keep-out line out of straight track segments. This is the only limitation I know of. A hint for quickly and accurately making the outline out of arcs: draw an arc of the right size and position, gerber

Re: [PEDA] Issue w/ lomax short Kelvin Paths and Copper pour

2002-05-14 Thread Abd ulRahman Lomax
If gerber plots were not rounded off, there would be no problem with the virtual shorts, and, in fact, if fab houses fabbed the boards as-is without modifying the gerber, there would also be no problem. But Protel does some rounding and it is not easy to exactly control aperture assignments

Re: [PEDA] Issue w/ lomax short Kelvin Paths and Copper pour

2002-05-15 Thread Abd ulRahman Lomax
in the (bad) case of using center origin and using gerber 2.3 i think the result was a 2 mil gap as the edges of the pads were pulled back toward the center to the nearest mil this notwithstanding it has proven to be a useful and clever tool Dennis Saputelli Abd ulRahman Lomax wrote: If gerber

Re: [PEDA] Protel DXP beta testing

2002-05-15 Thread Abd ulRahman Lomax
At 04:59 PM 5/15/2002 +1000, Thomas wrote: I received an invite to apply for Protel DXP beta testing today. As I have not signed it yet, I don't suppose its breaking the NDA to let you know this. It's my understanding that Beta testing was only being offered to those who had already signed up

Re: [PEDA] Protel DXP beta testing

2002-05-15 Thread Abd ulRahman Lomax
At 08:02 AM 5/15/2002 -0400, [EMAIL PROTECTED] wrote: I received it yesterday. However, I haven't yet decided whether to sign or not. Perhaps the biggest sticking point is that the license specifically forbids me to use the beta to do real work - above and beyond the usual disclaimers of

Re: [PEDA] AW: Kelvin Paths and Copper pour

2002-05-15 Thread Abd ulRahman Lomax
Due to a mail system error, this did not go out yesterday when it was written: At 11:57 AM 5/14/2002 +0200, Georg Beckmann wrote: For to do this, I use dummy parts usually 0402 resistors for the routing. You have different nets for current and sense, you can also give them different rules. After

Re: [PEDA] New Netlisting Problem

2002-05-15 Thread Abd ulRahman Lomax
Due to a mail system error, this did not go out yesterday when it was written: At 05:36 AM 5/14/2002 -0700, Fisher, Jerry wrote: Did you run an ERC to see if the resistor is flagged with a connection error. This is absolutely the first thing that should be done; and the ERC matrix should be

Re: [PEDA] Protel DXP beta testing

2002-05-15 Thread Abd ulRahman Lomax
At 08:49 AM 5/15/2002 -0700, Brad Velander wrote: [...]Another impact on revenue figures for this half is the re-scheduling of our next major product release. Protel DXP, which is now expected to go into external beta testing in May and released for sale in July 2002. So I guess anybody can talk

Re: [PEDA] rooms?

2002-05-15 Thread Abd ulRahman Lomax
At 11:26 AM 5/15/2002 -0700, Tony Karavidas wrote: Rooms are great. Yes, though their automatic generation can be a small nuisance. The checkbox for adding rooms is the default setting, as I recall, so I'm often getting rooms when I don't want them I'd prefer the default to be settable or

Re: [PEDA] Too many hole sizes

2002-05-16 Thread Abd ulRahman Lomax
At 11:31 AM 5/16/2002 -0700, Brad Velander wrote: The KB 1472 is so nice, they don't even suggest that letter characters might solve the problem so you are left to wonder. Is there a limit of 16 sizes even with the letter symbols? Actually, in my opinion, the best practice is to use

Re: [PEDA] Too many hole sizes

2002-05-16 Thread Abd ulRahman Lomax
At 01:37 PM 5/16/2002 -0700, Brad Velander wrote: Abd ul-Rahman, I agree with your general idea but suggest it is not practical with a most designs. Depends on how one tries to use it, doesn't it? The text size would have to be so small as to make it unreadable on anything but an E

Re: [PEDA] Too many hole sizes

2002-05-17 Thread Abd ulRahman Lomax
At 08:16 AM 5/17/2002 -0700, [EMAIL PROTECTED] wrote: 4. It is good practice to provide fabricators with your whole design or at least the .pcb file because often slight corrections are necessary to be made just to adapt the pcb to their technologies, and let them generate files and reports

Re: [PEDA] OT Too many hole sizes

2002-05-17 Thread Abd ulRahman Lomax
At 11:08 AM 5/17/2002 -0700, Brad Velander wrote: I developed my undying adoration for Fab dwgs at one employer where we purchased our PCBs in various shops usually located in China, Hong Kong, Singapore, India or Korea. Try doing that without very complete and thorough Fab Dwgs. You (and your

Re: [PEDA] Power plane questions

2002-05-20 Thread Abd ulRahman Lomax
At 03:02 PM 5/19/2002 -0700, Embedded Matt wrote: 1. I placed an arc on the plane (my board is circular) to form a circle all the way around the edge of the board. The idea is to keep the plane away from the edge of the board. The assigned net for the arc is No Net. Is this the correct

Re: [PEDA] More Qs :)

2002-05-20 Thread Abd ulRahman Lomax
At 02:35 PM 5/20/2002 +0500, Waheed Bajwa wrote: Whats a polygon good for? For filling an area of a PCB with copper. Also called a copper pour. Properly set up, the inside of the polygon will fill with copper (track) except for clearances as determined by the appropriate design rules around

Re: [PEDA] Too many hole sizes

2002-05-20 Thread Abd ulRahman Lomax
At 10:36 AM 5/20/2002 -0700, Brooks,Bill wrote: Okay, I'll jump in... The PCB fab house can do what ever it wants to make the board.YOUR FAB DRAWING allows your company to ACCEPT/REJECT it if it does not meet your standards. Yes. Another reason not to specify as-drilled sizes. It is a lot

Re: [PEDA] bitmap into PCB converter?

2002-05-20 Thread Abd ulRahman Lomax
There is a free bmp to protel converter in the filespace for [EMAIL PROTECTED] To access it, one must be registered with yahoo as a member of the mailing list. There is another converter from a designer in New Zealand: -- from a 1999 post by Harry Selfridge. I don't know if Mr. Velthuizen is

Re: [PEDA] Schematic Port questions

2002-05-20 Thread Abd ulRahman Lomax
At 12:16 PM 5/20/2002 -0700, Embedded Matt wrote: Two easy ones (I think): (1) I have a multi-page schematic with ports to connect nets between pages. Is there any way, besides adding a net label, to force Protel to give the net the port name in the netlist instead of something like R54_1? If

Re: [PEDA] Place net name cross project?

2002-05-21 Thread Abd ulRahman Lomax
At 11:03 AM 5/21/2002 -0400, Phillip Stevens wrote: Is there a way to get cross project net names (net names from all sheets in a project, not just the current schematic sheet) to appear in the place net name dialog box pull down list? Assuming that you have the panel displayed, with Browse

Re: [PEDA] hidden pin problem

2002-05-21 Thread Abd ulRahman Lomax
At 03:52 PM 5/21/2002 -0500, Robison Michael R CNIN wrote: hi bruce, oh! i used no name for them. and it went ahead and netted everything together, even across different packages and specific parts! i'll look into this. maybe i can name them and lose the bad net. I don't think so. Hidden

Re: [PEDA] Gerber to Protel, was Boardmaker to Protel

2002-05-23 Thread Abd ulRahman Lomax
At 10:47 AM 5/23/2002 +0100, Ivor Davies wrote: I have just joined this list and have my first query. We have a huge number of PCB designs in Boardmaker (an old DOS package written by Tsien of Cambridge, UK) and require to import them somehow into Protel. BTW, there is a much newer version of

Re: [PEDA] TO3 footprint

2002-05-23 Thread Abd ulRahman Lomax
At 09:26 AM 5/23/2002 -0400, Jeff Adolphs wrote: Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3 footprint has pins 1, 2, and two pin 3's. I thought this would work but the pin 3's do not have netnames in the layout. Do I have to use a schematic and footprint pin 3A and

Re: [PEDA] Hole annular ring

2002-05-23 Thread Abd ulRahman Lomax
At 11:14 AM 5/23/2002 -0700, Embedded Matt wrote: I have placed a few pads on my PCB with the following properties: X size: 0 Y size: 0 Don't do that Round Hole size 147 mil Multi-layer Not plated These are supposed to be mounting holes. I get annular ring violations on these pads. Of

Re: [PEDA] Adding extra tracks and vias.

2002-05-23 Thread Abd ulRahman Lomax
Another solution, besides those already given, is to use, in the footprint, through pads the size of vias and with the same hole size, given the same net as the SM pad. You will have complete DRC protection Another solution which might be better in some ways is to add a test point (single

Re: [PEDA] Gerber to Protel, was Boardmaker to Protel

2002-05-23 Thread Abd ulRahman Lomax
At 11:31 AM 5/23/2002 -0700, Brad Velander wrote: Abd ul-Rahman or others, do you know of a process using Protel V2.8 whereby you can read in gerber type data with a unique name applied to pads or vias of certain sizes. No. Then you can replace these uniquely named pads and via

Re: [PEDA] TO3 footprint

2002-05-23 Thread Abd ulRahman Lomax
At 04:29 PM 5/23/2002 -0400, you wrote: I fixed the TO3 by assigning only one pad as pin 3. Will multiple pins with one pin number work? Yes. Fully with Schematic/Update PCB, and with a known bug which is harmless once you know what it is with Netlist Load. I have not had a problem with

Re: [PEDA] Hole annular ring

2002-05-24 Thread Abd ulRahman Lomax
At 06:19 AM 5/24/2002 -0700, Embedded Matt wrote: Thanks for all the help on this question. I think the best solution for me is to create a special rule for these pads as some have suggested. I also appreciate the information on non-plated holes. Let me just add that the reason that I wanted a

Re: [PEDA] Gerber to Protel, was Boardmaker to Protel

2002-05-24 Thread Abd ulRahman Lomax
At 02:03 PM 5/23/2002 -0700, Brad Velander wrote: Abd ul-Rahman, the naming is performed on the Gerber data (how I don't remember) such that you have a pad flash with unique names for each different size assignment. Then you can replace those assignments with a multilayer pad globally. I

Re: [PEDA] Unlocking Spreadsheets

2002-05-30 Thread Abd ulRahman Lomax
At 01:14 PM 5/29/2002 +1000, [EMAIL PROTECTED] wrote: I just discovered another 'bug' fix for the spreadsheet editor. It always seems to default to locked and therefore any update you try to paste back from Excel (a usable spreadsheet package) causes a crash and suggests a reboot. That the

Re: [PEDA] Gerber to Protel, was Boardmaker to Protel

2002-05-30 Thread Abd ulRahman Lomax
At 02:25 PM 5/24/2002 -0700, Brad Velander wrote: Abd ul-Rahman, no you are not describing the process that I was trying to recall. Trust me, your description in no way resembles the process, nor is your process limited to Ver. 2.8 is it? No, it is not so limited. The process, as Mr.

Re: [PEDA] Systematically find unwanted antennas

2002-05-30 Thread Abd ulRahman Lomax
At 11:07 PM 5/28/2002 -0600, John W. Childers wrote: On a revision of a board, unwanted antennas can remain and must be found and removed. These are tracks that branch out from a net, but don't terminate on a pad, and can generate noise as electromagnetic waves, much like an antenna on a

Re: [PEDA] New Netlisting Problem

2002-05-31 Thread Abd ulRahman Lomax
At 01:41 PM 5/31/2002 +0200, Shahab Sanjari wrote: Sorry I was not at work due to an operation on my nose! we won't ask any nosy questions. But thank you all. As I stated, the problem occurs regardless of type or footprint. I will call this Remaining Netlisting Macros. Which means, after

Re: [PEDA] Systematically find unwanted antennas

2002-06-03 Thread Abd ulRahman Lomax
At 11:45 AM 5/31/2002 -0700, Brad Velander wrote: John, my personal thoughts on the spreadsheet method was that it would only work in the limited case where the track was only connected at one end. In my past I have found a great deal of stubs where this method wouldn't work because

Re: [PEDA] Solder and Paste Masks for Via in Pad BGAs

2002-06-03 Thread Abd ulRahman Lomax
At 10:57 AM 6/1/2002 -0500, David W. Gulley wrote: I am doing some via-in-pad BGAs and need to figure out if there is a good way to provide the top solder and top paste masks while keeping the bottom solder mask and bottom paste masks off. I defined the BGA pads as multilayer since I am doing

Re: [PEDA] Size of New Component Designator and Comment

2002-06-04 Thread Abd ulRahman Lomax
At 06:27 AM 6/4/2002 -0400, [EMAIL PROTECTED] wrote: I also have the same request, but the suggested setting doesn't seem to affect the string sizes. I long ago set the defaults to 30/6, but anything new loaded via the netlist (either netlist load or PCB update) seems to load with 60/10 strings.

Re: [PEDA] Problem with Polygon Planes and Pads

2002-06-04 Thread Abd ulRahman Lomax
At 04:49 PM 6/4/2002 +0300, EDA Software Technical Dpt. wrote: My PCB file contains Polygon Plane with 5 mils Clearance from the 18 mils pads. Ouch! 5 mils clearance from a plane is much more difficult to fab than 5 mils clearance between ordinary objects, because the plane clearance is

Re: [PEDA] negation character redux

2002-06-04 Thread Abd ulRahman Lomax
At 11:02 AM 6/4/2002 -0700, Bruce Walter wrote: Anybody know if there would be a problem using a dash (minus sign) as a prefix? I think it works, but as another mentioned, WR will be sorted in a different place than -WR. Personally, I use an asterisk at the end, not because it is necessarily

Re: [PEDA] Drawing Dashed Lines in Schematic

2002-06-05 Thread Abd ulRahman Lomax
At 09:31 PM 6/4/2002 -0400, Mitch Berkson wrote: I'd like to draw graphical dashed lines in a schematic to indicate guard traces which should be placed during PCB layout. Is there a way to do this in Protel 99SE SP6? Others have noted how to place a dashed line, and also that such a line has

Re: [PEDA] changing layer stack looses power plane connectivity

2002-06-05 Thread Abd ulRahman Lomax
At 11:18 AM 6/5/2002 -0600, Gordon Price wrote: I decided to take a couple of layers and move them around from the way they were and delete one of two ground plane layers( both named GND). [...] I deleted one of the ground plane layers and replaced it with a signal layer. I also moved the layers

Re: [PEDA] how to expend DIGEST mode

2002-06-05 Thread Abd ulRahman Lomax
At 10:19 AM 6/5/2002 -0400, Darryl Newberry wrote: I switched my list prefs to DIGEST mode, but was annoyed to discover that the digest is a hierarchy of attachments within attachments, to several levels. This means I can't search by topic, and it's ridiculously time consuming to find a

Re: [PEDA] Drawing Dashed Lines in Schematic

2002-06-05 Thread Abd ulRahman Lomax
At 02:19 PM 6/5/2002 -0400, Mitch Berkson wrote: Just as a point of interest - the type of guard trace I will be using is not necessarily connected to ground. It is guarding the high impedance input of an op amp with a low impedance signal at the same voltage in order to minimize leakage

Re: [PEDA] Power Planes in Layer Stack

2002-06-07 Thread Abd ulRahman Lomax
What does the Stack Manager show? What shows in the Design/Split Planes dialog? At 10:10 AM 6/6/2002 +0200, [EMAIL PROTECTED] wrote: I set up a board with 5 power planes; lateron I found out that by efficiently using split planes I could reduce them to 4. The obsolete power plane was named

Re: [PEDA] Protel / MSoft

2002-06-07 Thread Abd ulRahman Lomax
At 11:24 AM 6/6/2002 +0200, Rene Tschaggelar wrote: Complaining is one thing and acting another. While I tend to think the ATS period of 2k$ to be a bit short with one year, I also have to calculate what this investment brings. Note that the Protel web site now gives US$1495 as the value of the

Re: [PEDA] negation character redux

2002-06-07 Thread Abd ulRahman Lomax
At 06:05 AM 6/6/2002 -0700, Mira wrote: I just tried to debugg a board, which schematic was in Protel and the net names were RESET and RESET_. [...] Due to the way the net labels are attached to the wire in Protel, the underscore overlaps the wire and hardly could be seen. That was what I meant.

Re: [PEDA] Splitting a design to two PCBs

2002-06-07 Thread Abd ulRahman Lomax
At 12:10 PM 6/7/2002 -0400, Richard Sumner wrote: You might simply add the mating connector pair to the schematic, and run all required signals through both connectors. No net name changes needed. Everything else is done in pcb layout. You end up with one board design which is designed to

Re: [PEDA] Protel / MSoft

2002-06-08 Thread Abd ulRahman Lomax
At 03:12 PM 6/7/2002 -0700, Brad Velander wrote: Not to argue with you Abd ul-Rahman but Protel customer service has specifically stated to me, a couple of times, with complete sincerity that common CAD maintenance programs are typically 20% - 25% in the industry. Cadence has been 15% for a long

Re: [PEDA] Room Properties (Colors?)

2002-06-08 Thread Abd ulRahman Lomax
At 05:26 PM 6/7/2002 -0400, [EMAIL PROTECTED] wrote: I have just begun exploring the use of the Rooms feature, which is tailor-made for a current board. I notice that the crosshatching which indicates a room sometimes changes color, from a dark yellow to a dark red. This is an on-line DRC

Re: [PEDA] unused QFP pins

2002-06-08 Thread Abd ulRahman Lomax
At 06:13 PM 6/7/2002 -0700, Dennis Saputelli wrote: i've got a 144 pin PQFP 0.5mm pitch there are only a small number of connected pins, maybe a dozen or so excluding power i am thinking about deleting a lot of unused pads to possibly open up top side routes and reduce inspection and bridging

Re: [PEDA] How To Set Defaults

2002-06-10 Thread Abd ulRahman Lomax
At 07:39 AM 6/10/2002 -0700, Robert Ritchey wrote: This has probably been gone over before but I am just coming up to speed on 99SE. How can I set the default for the pad clearances and reliefs on the inner planes for split planes? Thanks, Design/Rules/Manufacturing/Power Plane Clearance

Re: [PEDA] Equalize Net Lengths?

2002-06-10 Thread Abd ulRahman Lomax
At 11:15 AM 6/10/2002 -0700, Joey Nelson wrote: The online help for matched net length rules seems to imply that if I set a rule for a set of nets and then run Tools-Equalize Net Lengths, that the shorter net will be accordioned to make up the difference, space allowing. But this does not

  1   2   >