Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread David Cary





Dear Kirk Haderlie,

If you really want a thermal relief on your vias, listen to Ian Wilson.

On the other hand, I don't want thermal relief on any of my vias. I always
want direct connect on my boards. (When I double-click my polygons, I make sure
[Y] pour over same net is enabled, and Grid size: 0 is set to zero.)

Would you indulge my curiosity ? How is thermal relief better than direct
connect on your board ?

--
David Cary


Ian Wilson [EMAIL PROTECTED] on 2001-02-19 helpfully explained:

.
On 06:22 PM 19/02/2001 -0800, Kirk Haderlie said:
We do a ground polygon fill on the top and bottom of our boards.  Has anyone
been successful getting relief connections on vias?  I have tried a polygon
connect style design rule that applied only to vias on the GND net but this
does not work.

Kirk Haderlie
Design Engineer
Vivid Image Technology
[EMAIL PROTECTED]

This is a known bug. The polygon connect style for vias is not obeyed.

You must change the vias to pads and then change you connect rule to apply
to these pads.

You can easily change (selected) vias to pads using the
Tools|Convert|Convert Selected vias to pads command.

In order to control application of the rule you may want to consider naming
the pads something like PGND (poly gnd) so you can restrict the application
to Free-PGND pads only.  While the pads are selected (from the convert
operation) is a good time to do this as a global change matching by selection.

Ian Wilson







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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Ian Wilson

On 06:22 PM 19/02/2001 -0800, Kirk Haderlie said:
We do a ground polygon fill on the top and bottom of our boards.  Has anyone
been successful getting relief connections on vias?  I have tried a polygon
connect style design rule that applied only to vias on the GND net but this
does not work.

Kirk Haderlie
Design Engineer
Vivid Image Technology
[EMAIL PROTECTED]

This is a known bug. The polygon connect style for vias is not obeyed.

You must change the vias to pads and then change you connect rule to apply 
to these pads.

You can easily change (selected) vias to pads using the 
Tools|Convert|Convert Selected vias to pads command.

In order to control application of the rule you may want to consider naming 
the pads something like PGND (poly gnd) so you can restrict the application 
to Free-PGND pads only.  While the pads are selected (from the convert 
operation) is a good time to do this as a global change matching by selection.

Ian Wilson



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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Dennis Saputelli

I think that's just the way it is
you can do a convert to pads and rebuild
but why do you want it that way?
Dennis Saputelli

Kirk Haderlie wrote:
 
 We do a ground polygon fill on the top and bottom of our boards.  Has anyone
 been successful getting relief connections on vias?  I have tried a polygon
 connect style design rule that applied only to vias on the GND net but this
 does not work.
 
 Kirk Haderlie
 Design Engineer
 Vivid Image Technology
 [EMAIL PROTECTED]
 
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___
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   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110



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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Edi Im Hof

At 18:22 19.02.01 -0800, you wrote:
We do a ground polygon fill on the top and bottom of our boards.  Has anyone
been successful getting relief connections on vias?

No. As far as I know, Protel allways connects the vias direct to planes and 
fills.
Convert the vias to free pads, there's a command t oto this somewhere. Then 
you can apply your rules to free pads.
Vias are supposed (by Protel) only to connect between layers, not to solder 
something in it. So they do not need a thermal relief.


Edi

   I have tried a polygon
connect style design rule that applied only to vias on the GND net but this
does not work.

Kirk Haderlie
Design Engineer
Vivid Image Technology
[EMAIL PROTECTED]




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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Kirk Haderlie

We are hand soldering the prototypes and having a hard time heating all the
copper attached to the GND vias.  The reliefs on the polygon fill might make
it a little easier to solder.

-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]]
Sent: Monday, February 19, 2001 7:06 PM
To: Multiple recipients of list proteledausers
Subject: Re: [PROTEL EDA USERS]: Relief on Vias


I think that's just the way it is
you can do a convert to pads and rebuild
but why do you want it that way?
Dennis Saputelli

Kirk Haderlie wrote:
 
 We do a ground polygon fill on the top and bottom of our boards.  Has
anyone
 been successful getting relief connections on vias?  I have tried a
polygon
 connect style design rule that applied only to vias on the GND net but
this
 does not work.
 
 Kirk Haderlie
 Design Engineer
 Vivid Image Technology
 [EMAIL PROTECTED]
 
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   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110



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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Brad Velander

Kirk,
as has been mentioned several times in the replies you have gotten
so far, you can't get there from here. Not without converting the vias to
free pads Therefore after they will be stupid Free pads and they will be
replaced by Vias, but not deleted themselves, if you reroute. One or two
others asked the best question, why do you want thermal relieved vias? The
only purpose of thermal reliefs on pads/vias is to reduce the conduction of
heat away from the pad to the polygon or plane during soldering. Thus this
increases the heat available on the pad and allows for better reflow and
desoldering. You are not the first to ask, nor will you probably be the last
to ask but I am constantly wondering why people want to due this on vias? Is
there a reason or do you just not know better? If you don't know better
there is lots of advice available from this group, as we were all newbies
once.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Kirk Haderlie
Sent: Monday, February 19, 2001 6:23 PM
To: Multiple recipients of list proteledausers
Subject: [PROTEL EDA USERS]: Relief on Vias


We do a ground polygon fill on the top and bottom of our boards.  Has anyone
been successful getting relief connections on vias?  I have tried a polygon
connect style design rule that applied only to vias on the GND net but this
does not work.

Kirk Haderlie
Design Engineer
Vivid Image Technology
[EMAIL PROTECTED]



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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Michael Beavis



 Would you indulge my curiosity ? How is thermal relief better than
direct
 connect on your board ?

 --
 David Cary


Jumping in
Soldering pth vias on planes improves the reliability of the connection and
to achieve this, thermal relief is recommended (IPC-D-279).
Cyclic thermal excursions cause a mismatch between the Cu in the plated hole
and the surrounding dielectric (eg.FR4) due to differing CTE's and can cause
seperation of the via land from the hole plating resulting in open or worse
still, intermittant connections. I have seen this happen and spending
several days in a walk in temperature cycling chamber debugging a batch of
boards isn't easy to forget.
The mismatch relies on the ductile properties of Cu to take up the slack but
over time, temperature cycles, vibration and any other environmental
hazards, this property is reduced (work hardening of metals). Solder is far
more ductile than Cu and thus offers greater reliability.
Wave soldering tends to fill untented vias anyway so they may as well be
filled properly.
The draw back of increased weight versus higher reliability is a no brainer
when it comes to our applications which are required to work under extremes
of vibration and temperature.

Best regards

Michael Beavis

Advanced Mining Technologies Pty Ltd
Research  Development dept
PO Box 376 Wyong NSW 2259 Australia
(20 Lucca Road, North Wyong, NSW 2259)
Tel: (+61) 2 4351 1778
Fax:  (+61) 2 4351 1764
Email:  [EMAIL PROTECTED]
Website:  www.advminingtech.com.au




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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Geoff Harland

  I think that's just the way it is
  you can do a convert to pads and rebuild
  but why do you want it that way?
 
  Dennis Saputelli

 We are hand soldering the prototypes and having a hard time heating all
the
 copper attached to the GND vias.  The reliefs on the polygon fill might
make
 it a little easier to solder.

 Kirk Haderlie

*Unless* the PCBs you are hand soldering are *not* through-hole plated, why
do you want to apply solder in the locations of the vias? As long as the
*pads* (to which you are soldering components' leads to) are thermally
relieved, the *vias* don't have be thermally relieved as well. (When PCBs
are reflow soldered or wave soldered, it is not customary for vias to be
thermally relieved, and hand soldering is no different in that regard.)

Perhaps you have a good reason for having PCBs manufactured that are *not*
through-hole plated, such as delivery times or cost considerations. However,
I recall one time, back in 1984, when I installed components on a prototype
PCB (incorporating a microprocessor, memory, and I/O interface chips) which
was not through hole plated. I think I spent the best part of a whole day on
the one task of soldering bits of wire to join the two sides of each via in
the PCB, all the while praying that I wouldn't end up missing any of these
(or at least none of the vias *under* components such as ICs). As such, if
you can possibly help it, get plated-through PCBs manufactured, including
prototype runs.

Regards,
Geoff Harland.
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Re: [PEDA] [PROTEL EDA USERS]: Relief on Vias

2001-05-07 Thread Ian Wilson

On 12:30 PM 21/02/2001 +1100, Michael Beavis said:

 
  Would you indulge my curiosity ? How is thermal relief better than
direct
  connect on your board ?
 
  --
  David Cary
 

Jumping in
Soldering pth vias on planes improves the reliability of the connection and
to achieve this, thermal relief is recommended (IPC-D-279).
Cyclic thermal excursions cause a mismatch between the Cu in the plated hole
and the surrounding dielectric (eg.FR4) due to differing CTE's and can cause
seperation of the via land from the hole plating resulting in open or worse
still, intermittant connections. I have seen this happen and spending
several days in a walk in temperature cycling chamber debugging a batch of
boards isn't easy to forget.
The mismatch relies on the ductile properties of Cu to take up the slack but
over time, temperature cycles, vibration and any other environmental
hazards, this property is reduced (work hardening of metals). Solder is far
more ductile than Cu and thus offers greater reliability.
Wave soldering tends to fill untented vias anyway so they may as well be
filled properly.
The draw back of increased weight versus higher reliability is a no brainer
when it comes to our applications which are required to work under extremes
of vibration and temperature.

Best regards

Michael Beavis

Good points - this is especially relevant for anyone using teflon based 
PCBs as teflon undergoes a phase change at about 19deg C (room temp) where 
its Z-axis CTE changes very quickly - even quite mild temperature cycling 
of marginal quality teflon boards can readily show barrel cracking as 
Michael said - I too have debugged intermittent failures due to this.

However a problem with making relief connections on Teflon is that usually 
a teflon PCB is designed fro high freq work and so the increased inductance 
of the relief is undesirable :-(

Ian



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