Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-20 Thread Abd ul-Rahman Lomax
At 12:08 AM 1/18/2003, Robert M. Wolfe wrote: Abd ul-Rahman Isn't this just really saying the silkscreen IS the defining factor No. The extents of the footprint are the defining factor in 99SE, if I am correct -- I didn't check it. Often the silkscreen is the outermost primitive. IMHO

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-19 Thread Julian Higginson
, Ultimo, NSW, 2007, Australia. mailto:[EMAIL PROTECTED] - http://www.lake.com.au -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Saturday, January 18, 2003 6:49 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-19 Thread Ian Wilson
On 09:40 AM 20/01/2003 +1100, Julian Higginson said: Can't you set a negative clearance for this problem? Work out your overlay line thickness and then set the component clearance to -(thickness/2) This should work, though it is untested No, negative clearances do not work. I have been

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6.

2003-01-17 Thread JaMi Smith
John, You are not doing anything wrong, it's just Protel. This has been a pet peeve for a long time. Every other system out there will allow this. This is the old problem of having a whole row of 0603 or some other components with a rectangular box around each one of them and Protel demanding

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread ajenkins
in this equation? aj -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: Friday, January 17, 2003 2:27 PM To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6. John, You are not doing anything wrong

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Robert M. Wolfe
constraint shouldn't even be invoked... What am I missing in this equation? aj -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: Friday, January 17, 2003 2:27 PM To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] A Question About PCB Design Rules. Protel

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Abd ul-Rahman Lomax
At 03:04 PM 1/17/2003, [EMAIL PROTECTED] wrote: Okay, call me dumb, but I am having a hard time understanding how the DRC even comes into play, since the clearance constraint is, by definition, a constraint on copper layers only. Since the silkscreen is not a copper layer, the clearance

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Brad Velander
John, adding to Jami's list. 5) Do as I do, turn off the component placement DRC check completely. It just doesn't work in any usable manner. Use your eyes and personal knowledge. The component placement DRC uses any land pattern item, visible, invisible, regardless of layer to

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Brad Velander
- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Friday, January 17, 2003 12:05 PM To: Protel EDA Forum Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6 . Okay, call me dumb, but I am having a hard time understanding how the DRC even comes

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread ajenkins
Frankly, I don't even understand concerns about silkscreen and pads. The silkscreen simply will not be printed over the solder area, since the pad-mask prevents adherence of the ink to these areas. Admittedly, one might lose bits of a character or outline this way, but the person responsible for

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Abd ul-Rahman Lomax
At 04:30 PM 1/17/2003, [EMAIL PROTECTED] wrote: Frankly, I don't even understand concerns about silkscreen and pads. The silkscreen simply will not be printed over the solder area, since the pad-mask prevents adherence of the ink to these areas. The component clearance rule is not about the

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 . Thanks....!

2003-01-17 Thread John Branthoover
EDA Forum' Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6 . Andrew, my understanding is that he is talking of the component placement DRC check. It checks the area bounding all portions/layers of the land pattern to the bounding area of the next land pattern

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread JaMi Smith
] Sent: Friday, January 17, 2003 11:48 AM Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6 . John, adding to Jami's list. 5) Do as I do, turn off the component placement DRC check completely. It just doesn't work in any usable manner. Use your eyes and personal

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Robert M. Wolfe
Abd ul-Rahman Isn't this just really saying the silkscreen IS the defining factor IMHO the silkscreen layer should never have been used as an indicator or ultimately the real extents of a part. There really needs to be a user defined layer that will be used at the extents of a part to check