Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-20 Thread Abd ul-Rahman Lomax
At 12:08 AM 1/18/2003, Robert M. Wolfe wrote:

Abd ul-Rahman

Isn't this just really saying the silkscreen IS the defining factor


No. The extents of the footprint are the defining factor in 99SE, if I am 
correct -- I didn't check it. Often the silkscreen is the outermost primitive.

IMHO the silkscreen layer should never have been used as an indicator
or ultimately the real extents of a part. There really needs to be a user
defined layer that will be used at the extents of a part to check part
clearance.


Yes. I think that's what I wrote.


And that layer does not necesarily have to be an assembly layer.


There is no such thing as a P99SE assembly layer. There are only 
mechanical layers, which the user can personally define as assembly if 
desired.

I have seen systems that define both actual part and real world
clearances required for assembly/test/rework etc., and control over
which rule pending level of technology required for design.


Let me guess. What did those systems cost?


And line widths really should have nothing to do with it
when you are defining a clearance just center as if it were
a zero width line.


Yes. Again, this has all been said not only in this thread but before.


 Only silkscreen itself should be considered
for thickness itself with respect to all other features. But part
clearance should be to a dimension MMC, etc not ever dealing
with the thickness of a line defining it.


Of course. Now, to do it at present -- sort of -- , use a mech layer to 
create a clearance layer with zero width lines (yes, Protel will display 
them at one pixel) at MMC. Make this a part of all footprints. Do not allow 
silkscreen lines or any other primitive to extend outside this area. The 
present clearance rule will only report real collisions (assuming that all 
parts are rectangular in maximum extent.) This will not work perfectly, but 
it would work for most parts. And with the DXP additional rules, it will 
work even better.

But it would still be better to check for line intersections between 
different footprints on that clearance layer. And the huge problem with 
this solution is that one would have to rework all footprints.

Protel's way of dealing with this can of worms was to use the component 
extents. This was a quick-and-dirty solution, almost better than nothing. 
The mistake was in using true primitive extents (which goes to the outside 
of outlines) and/or in not allowing negative clearance. Probably better to 
have used line-center for the silkscreen portion of the extents instead of 
line-edge as they did. There isn't really a need for negative clearance 
except as a compensation for the first mistake

DXP then adds the exception rules which allows one to disable checking for 
particular parts, so that, one, for example, could place one part under 
another while suppressing the collision error.

The comment made by one writer that they would rather see 100 false error 
messages than miss one real problem (or something like that) misses the 
point. If you see 100 false error messages you are very likely to miss the 
one real error. What are you going to do the next revision? Check every one 
of those 101 errors again? This is why, in my opinion, good design requires 
killing all the phoney ERC reports in schematic; preferably one designs so 
that the error reports don't come up, but where that is impractical one 
suppresses them with a No-ERC Directive. In PCB one can do something like 
this, sometimes, with a special rule. We have asked for better special 
rules, perhaps a PCB equivalent of No-ERC, which is truly generic, it will 
suppress *any* error report.


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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-19 Thread Julian Higginson

Can't you set a negative clearance for this problem?

Work out your overlay line thickness and then set the component clearance to
-(thickness/2) This should work, though it is untested I tend to turn
off component clearance check too, it is annoying. And really, as long as
the copper clearances are OK then your design should be alright, as long as
you don't accidentally place any component under any other component.

Also, there are three types of clearance checking. Quick check and
multilayer check are both a bit retarded, full check is still not so great,
but seems a lot better to me.

As far as what a clearance of 0 should mean, I actually think that Protel
is corrrect, as if the outer edges of two components are just touching,
there is a clearence of 0 which is what you've specified!!


Julian


--
Julian Higginson - Design Engineer - Lake Technology.
502/51-55 Mountain St, Ultimo, NSW, 2007, Australia.
mailto:[EMAIL PROTECTED] - http://www.lake.com.au 
 

 -Original Message-
 From: Brad Velander [mailto:[EMAIL PROTECTED]]
 Sent: Saturday, January 18, 2003 6:49 AM
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
 SP6 .
 
 
 John,
   adding to Jami's list.
 5) Do as I do, turn off the component placement DRC check 
 completely. It
 just doesn't work in any usable manner. Use your eyes and personal
 knowledge.
   The component placement DRC uses any land pattern item, visible,
 invisible, regardless of layer to determine the maximum extent of the
 component. It then draws a bounding box around all these items, this
 constitutes the component boundary for the placement 
 checking. Therefore any
 designator, comment, text string, etc. gets included with the 
 actual desired
 component boundary.
   As you have found setting 0 allows placement down to 
 touching but
 will still show a violation if items actually touch. I too 
 think that this
 is a failing of Protel/Altium, a setting of 0 should allow 
 items to touch.
 It probably should allow overlap as well but I wouldn't push 
 it that far
 because I don't see that being really useful or a common need.
 
 Sincerely,
 Brad Velander.
 
 Lead PCB Designer
 Norsat International Inc.
 Microwave Products
 Tel   (604) 292-9089 (direct line)
 Fax  (604) 292-9010
 email: [EMAIL PROTECTED]
 http://www.norsat.com
 
 
  -Original Message-
  From: John Branthoover [mailto:[EMAIL PROTECTED]]
  Sent: Friday, January 17, 2003 9:57 AM
  To: Protel EDA Forum
  Subject: [PEDA] A Question About PCB Design Rules. Protel 
  99SE SP6.
 SNIP
  
  What am I doing wrong?  Any information that you can 
  give will be greatly
  appreciated.  Thank you for your time and have a nice day.
  
  
  
  John Branthoover:
  Electrical Design Engineer  :
  Acutronic  R  D:Phone  (412) 968-1051
  640 Alpha Drive :Fax(412) 963-0816
  Pittsburgh PA 15238 :Email  [EMAIL PROTECTED]
  USA :WEBhttp://www.acutronic.com
 

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-19 Thread Ian Wilson
On 09:40 AM 20/01/2003 +1100, Julian Higginson said:


Can't you set a negative clearance for this problem?

Work out your overlay line thickness and then set the component clearance to
-(thickness/2) This should work, though it is untested


No, negative clearances do not work.

I have been encouraging Altium to implement negative clearances for a while 
now.  However, I suspect that if they did address this it would be part of 
a much more elaborate system that would link into the 3D stuff  - component 
clearance is after all a 3D issue in some cases.  I don't know anything 
that you don't about this - just a guess.

DXP has a sort-of-solution that is OK for me.  The more elaborate rules and 
queries allows you to turn *off* component clearance checking between just 
the two (or few) affected components, without preventing clearance checking 
between all the other components (and in fact between all the other 
components and the two affected components).  This is done by using a rule 
that excludes checking between these components rather than trying to make 
a rule that pertains to just these two components.  In other words instead 
of an ALL-ALL rule you have a rule that is something like 
Not(InComponentClass('OverlappingStuff')-Not(InComponentClass('OverlappingStuff') 
rule, where 'OverlappingStuff' is a component class you have set up 
containing just the components that you want to allow an overlap on.  If 
you don't follow don't worry - it would be obvious enough to those at all 
familiar with DXP.

I would prefer, though, that the DXP was modified to accept and check 
negative clearances in the interim.  In most cases this would be sufficient 
- full 3D modelling is not required all that often.  I would not expect to 
see P99SE updated to accept negative clearances, whoever nice it may be.

bye for now,
Ian Wilson

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6.

2003-01-17 Thread JaMi Smith
John,

You are not doing anything wrong, it's just Protel.

This has been a pet peeve for a long time.

Every other system out there will allow this.

This is the old problem of having a whole row of 0603 or some other
components with a rectangular box around each one of them and Protel
demanding that you add and waste additional space between components rather
than simply line them up next to each other with a common silkscreen line
between them.

Protel doesn't understand that this is not really a Design Error, and that
it is not a short, and that at worst it should only give you warning (or
at least provide a standard means of allowing you to do this without
having to resort to kludging something).

Options:

1. Make a new component combining the two jumpers, with the silkscreen line
seperating them drawn within the component itself.

2. Make a special component with one side of the silkscreen missing so that
you can combine it with the other normal component.

3. Use a component that does not have an outline, and place the two of them
where you want them, and manually draw your own outlines the way you want
them to appear on the silkscreen (Overlay) layer. While this may be the
simplest way around the problem, it is a kludge in and of itself simply
because it takes extra time and everything gets screwed up if you ever try
and move anything involved since the lines are not part of the component.

4. Ignore the DRC Error and overlap the edges of the component so that it
does exactly what you want it to do, and then put a note in a text file
stored within the database that explains the problem to the next guy who has
to work on the project.

While I am sure that there will be some out there that will will reply to
this post that will have some way to modify some special rule somewhere, my
feeling on this is that making special rules for special circumstances
is something that should be anathema in EDA Systems simply because the
next guy to work on the project will never find it or understand it, and
then when someone else (or even you after you forget about the kludge)
copies your database at a later date and modifies your file for a similar
project he will now end up having a screwed up database with non standard
rules that he doesn't even know about and will never find, and you will
propagate the special rule for special circumstances kludge down the
line ad infinitium, which is shear stupidity.

Go with the fourth option above and a note. At least everyone will be able
to see it (the DRC Error) and even if they do not understand it, it won't
get overlooked and lost in the process.

JaMi Smith


- Original Message -
From: John Branthoover [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, January 17, 2003 9:57 AM
Subject: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6.


 Hello All,
 I have two (2) position jumpers with a rectangular silkscreen drawn around
 them.  I want to place them on my PCB such that one side of the silkscreen
 overlap.  I created a component jumper class and added these two jumpers.
 In the design rules under Placement, Component Clearance Constraint I set
up
 a rule for the jumper class to have a gap of 0 mil with scope A and B both
 set to the jumper class.  I did this thinking that it would allow me to
 place the jumper side by side with the silkscreen s on one side
overlapping
 while not affecting other components.  I also left the default Component
 Clearance rule in place - 10 mil gap with scope A and B set to board.

 When I attempt this I get a violation as soon a s the silkscreen over lap.
 If I un-check the On-line Component Clearance check box (under Design Rule
 Check),  I stop getting the violations.  How ever,  if click on the Run
DRC
 button,  I still get a violation.  Of coarse this also goes away when I
 un-check the Report Component Clearance check box also under Design Rule
 Check.

 What am I doing wrong?  Any information that you can give will be greatly
 appreciated.  Thank you for your time and have a nice day.



 John Branthoover:
 Electrical Design Engineer  :
 Acutronic  R  D:Phone  (412) 968-1051
 640 Alpha Drive :Fax(412) 963-0816
 Pittsburgh PA 15238 :Email  [EMAIL PROTECTED]
 USA :WEBhttp://www.acutronic.com

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread ajenkins
Okay, call me dumb, but I am having a hard time understanding how the DRC
even comes into play, since the clearance constraint is, by definition, a
constraint on copper layers only. Since the silkscreen is not a copper
layer, the clearance constraint shouldn't even be invoked...

What am I missing in this equation?

aj

 -Original Message-
 From: JaMi Smith [mailto:[EMAIL PROTECTED]]
 Sent: Friday, January 17, 2003 2:27 PM
 To: Protel EDA Forum
 Cc: JaMi Smith
 Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
 SP6.
 
 
 John,
 
 You are not doing anything wrong, it's just Protel.
 
 This has been a pet peeve for a long time.
 
 Every other system out there will allow this.
 
 This is the old problem of having a whole row of 0603 or some other
 components with a rectangular box around each one of them and Protel
 demanding that you add and waste additional space between 
 components rather
 than simply line them up next to each other with a common 
 silkscreen line
 between them.
 
 Protel doesn't understand that this is not really a Design 
 Error, and that
 it is not a short, and that at worst it should only give 
 you warning (or
 at least provide a standard means of allowing you to do this without
 having to resort to kludging something).
 
 Options:
 
 1. Make a new component combining the two jumpers, with the 
 silkscreen line
 seperating them drawn within the component itself.
 
 2. Make a special component with one side of the silkscreen 
 missing so that
 you can combine it with the other normal component.
 
 3. Use a component that does not have an outline, and place 
 the two of them
 where you want them, and manually draw your own outlines 
 the way you want
 them to appear on the silkscreen (Overlay) layer. While 
 this may be the
 simplest way around the problem, it is a kludge in and of 
 itself simply
 because it takes extra time and everything gets screwed up if 
 you ever try
 and move anything involved since the lines are not part of 
 the component.
 
 4. Ignore the DRC Error and overlap the edges of the 
 component so that it
 does exactly what you want it to do, and then put a note in a 
 text file
 stored within the database that explains the problem to the 
 next guy who has
 to work on the project.
 
 While I am sure that there will be some out there that will 
 will reply to
 this post that will have some way to modify some special rule 
 somewhere, my
 feeling on this is that making special rules for special 
 circumstances
 is something that should be anathema in EDA Systems simply 
 because the
 next guy to work on the project will never find it or 
 understand it, and
 then when someone else (or even you after you forget about 
 the kludge)
 copies your database at a later date and modifies your file 
 for a similar
 project he will now end up having a screwed up database with 
 non standard
 rules that he doesn't even know about and will never find, 
 and you will
 propagate the special rule for special circumstances 
 kludge down the
 line ad infinitium, which is shear stupidity.
 
 Go with the fourth option above and a note. At least everyone 
 will be able
 to see it (the DRC Error) and even if they do not understand 
 it, it won't
 get overlooked and lost in the process.
 
 JaMi Smith
 
 
 - Original Message -
 From: John Branthoover [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Friday, January 17, 2003 9:57 AM
 Subject: [PEDA] A Question About PCB Design Rules. Protel 
 99SE SP6.
 
 
  Hello All,
  I have two (2) position jumpers with a rectangular 
 silkscreen drawn around
  them.  I want to place them on my PCB such that one side of 
 the silkscreen
  overlap.  I created a component jumper class and added 
 these two jumpers.
  In the design rules under Placement, Component Clearance 
 Constraint I set
 up
  a rule for the jumper class to have a gap of 0 mil with 
 scope A and B both
  set to the jumper class.  I did this thinking that it would 
 allow me to
  place the jumper side by side with the silkscreen s on one side
 overlapping
  while not affecting other components.  I also left the 
 default Component
  Clearance rule in place - 10 mil gap with scope A and B set 
 to board.
 
  When I attempt this I get a violation as soon a s the 
 silkscreen over lap.
  If I un-check the On-line Component Clearance check box 
 (under Design Rule
  Check),  I stop getting the violations.  How ever,  if 
 click on the Run
 DRC
  button,  I still get a violation.  Of coarse this also goes 
 away when I
  un-check the Report Component Clearance check box also 
 under Design Rule
  Check.
 
  What am I doing wrong?  Any information that you can give 
 will be greatly
  appreciated.  Thank you for your time and have a nice day.
 
 
 
  John Branthoover:
  Electrical Design Engineer  :
  Acutronic  R  D:Phone  (412) 968-1051
  640 Alpha Drive :Fax(412) 963-0816
  Pittsburgh PA

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Robert M. Wolfe
Well I guess that is also why when you move a Ref Des on a
part that is tied to VCC or GND it take a bit of time
to keep analyzing VCC under DRC. Never seen a
system do that. I can see a need to specifically drc silkscreen
to pads etc on the board but not every time you touch a Ref'Des.
And yes you can turn off DRC bu tit still seems to do it and
actually whay should you have to turn it off just to touch a silkscreen?


Bob Wolfe.


- Original Message -
From: [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, January 17, 2003 3:04 PM
Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6 .


 Okay, call me dumb, but I am having a hard time understanding how the DRC
 even comes into play, since the clearance constraint is, by definition, a
 constraint on copper layers only. Since the silkscreen is not a copper
 layer, the clearance constraint shouldn't even be invoked...

 What am I missing in this equation?

 aj

  -Original Message-
  From: JaMi Smith [mailto:[EMAIL PROTECTED]]
  Sent: Friday, January 17, 2003 2:27 PM
  To: Protel EDA Forum
  Cc: JaMi Smith
  Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
  SP6.
 
 
  John,
 
  You are not doing anything wrong, it's just Protel.
 
  This has been a pet peeve for a long time.
 
  Every other system out there will allow this.
 
  This is the old problem of having a whole row of 0603 or some other
  components with a rectangular box around each one of them and Protel
  demanding that you add and waste additional space between
  components rather
  than simply line them up next to each other with a common
  silkscreen line
  between them.
 
  Protel doesn't understand that this is not really a Design
  Error, and that
  it is not a short, and that at worst it should only give
  you warning (or
  at least provide a standard means of allowing you to do this without
  having to resort to kludging something).
 
  Options:
 
  1. Make a new component combining the two jumpers, with the
  silkscreen line
  seperating them drawn within the component itself.
 
  2. Make a special component with one side of the silkscreen
  missing so that
  you can combine it with the other normal component.
 
  3. Use a component that does not have an outline, and place
  the two of them
  where you want them, and manually draw your own outlines
  the way you want
  them to appear on the silkscreen (Overlay) layer. While
  this may be the
  simplest way around the problem, it is a kludge in and of
  itself simply
  because it takes extra time and everything gets screwed up if
  you ever try
  and move anything involved since the lines are not part of
  the component.
 
  4. Ignore the DRC Error and overlap the edges of the
  component so that it
  does exactly what you want it to do, and then put a note in a
  text file
  stored within the database that explains the problem to the
  next guy who has
  to work on the project.
 
  While I am sure that there will be some out there that will
  will reply to
  this post that will have some way to modify some special rule
  somewhere, my
  feeling on this is that making special rules for special
  circumstances
  is something that should be anathema in EDA Systems simply
  because the
  next guy to work on the project will never find it or
  understand it, and
  then when someone else (or even you after you forget about
  the kludge)
  copies your database at a later date and modifies your file
  for a similar
  project he will now end up having a screwed up database with
  non standard
  rules that he doesn't even know about and will never find,
  and you will
  propagate the special rule for special circumstances
  kludge down the
  line ad infinitium, which is shear stupidity.
 
  Go with the fourth option above and a note. At least everyone
  will be able
  to see it (the DRC Error) and even if they do not understand
  it, it won't
  get overlooked and lost in the process.
 
  JaMi Smith
 
 
  - Original Message -
  From: John Branthoover [EMAIL PROTECTED]
  To: Protel EDA Forum [EMAIL PROTECTED]
  Sent: Friday, January 17, 2003 9:57 AM
  Subject: [PEDA] A Question About PCB Design Rules. Protel
  99SE SP6.
 
 
   Hello All,
   I have two (2) position jumpers with a rectangular
  silkscreen drawn around
   them.  I want to place them on my PCB such that one side of
  the silkscreen
   overlap.  I created a component jumper class and added
  these two jumpers.
   In the design rules under Placement, Component Clearance
  Constraint I set
  up
   a rule for the jumper class to have a gap of 0 mil with
  scope A and B both
   set to the jumper class.  I did this thinking that it would
  allow me to
   place the jumper side by side with the silkscreen s on one side
  overlapping
   while not affecting other components.  I also left the
  default Component
   Clearance rule in place - 10 mil gap with scope A and B set
  to board.
  
   When I

Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Abd ul-Rahman Lomax
At 03:04 PM 1/17/2003, [EMAIL PROTECTED] wrote:

Okay, call me dumb, but I am having a hard time understanding how the DRC
even comes into play, since the clearance constraint is, by definition, a
constraint on copper layers only. Since the silkscreen is not a copper
layer, the clearance constraint shouldn't even be invoked...

What am I missing in this equation?


The Component Clearance rules are separate from the copper clearance rules.

Design Rules/Placement/Component Clearance Constraint.

It is an example of where the feature was pretty obviously not run through 
extensive testing with real designers before being frozen. There were 
several possible solutions, not at all difficult, I'd think, but they 
didn't do it. This should have been fixed by SP6

My solution to this problem, since Protel component clearance checking is 
too defective to use, unless one specially designs footprints (i.e., 
footprints with the outline retracted sufficiently so that the *outside*, 
not centerline, of the outline is at minimum clearance -- I haven't done 
this, but it should work, maybe one would have to retract another mil), 
I disable the component clearance checking.

(uncheck the Enabled box for all clearance rules that can cause problems, 
i.e., that will generate phony errors.)



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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Brad Velander
John,
adding to Jami's list.
5) Do as I do, turn off the component placement DRC check completely. It
just doesn't work in any usable manner. Use your eyes and personal
knowledge.
The component placement DRC uses any land pattern item, visible,
invisible, regardless of layer to determine the maximum extent of the
component. It then draws a bounding box around all these items, this
constitutes the component boundary for the placement checking. Therefore any
designator, comment, text string, etc. gets included with the actual desired
component boundary.
As you have found setting 0 allows placement down to touching but
will still show a violation if items actually touch. I too think that this
is a failing of Protel/Altium, a setting of 0 should allow items to touch.
It probably should allow overlap as well but I wouldn't push it that far
because I don't see that being really useful or a common need.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


 -Original Message-
 From: John Branthoover [mailto:[EMAIL PROTECTED]]
 Sent: Friday, January 17, 2003 9:57 AM
 To: Protel EDA Forum
 Subject: [PEDA] A Question About PCB Design Rules. Protel 
 99SE SP6.
SNIP
 
   What am I doing wrong?  Any information that you can 
 give will be greatly
 appreciated.  Thank you for your time and have a nice day.
 
 
 
 John Branthoover:
 Electrical Design Engineer  :
 Acutronic  R  D:Phone  (412) 968-1051
 640 Alpha Drive :Fax(412) 963-0816
 Pittsburgh PA 15238 :Email  [EMAIL PROTECTED]
 USA :WEBhttp://www.acutronic.com

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Brad Velander
Andrew,
my understanding is that he is talking of the component placement
DRC check. It checks the area bounding all portions/layers of the land
pattern to the bounding area of the next land pattern. It isn't a copper
check but a component to component clearance check.
Like myself or a number of others, you probably have it turned off
since early in the P99 days.
Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


 -Original Message-
 From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
 Sent: Friday, January 17, 2003 12:05 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
 SP6 .
 
 
 Okay, call me dumb, but I am having a hard time understanding 
 how the DRC
 even comes into play, since the clearance constraint is, by 
 definition, a
 constraint on copper layers only. Since the silkscreen is not a copper
 layer, the clearance constraint shouldn't even be invoked...
 
 What am I missing in this equation?
 
 aj
 

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread ajenkins
Frankly, I don't even understand concerns about silkscreen and pads. The
silkscreen simply will not be printed over the solder area, since the
pad-mask prevents adherence of the ink to these areas.

Admittedly, one might lose bits of a character or outline this way, but the
person responsible for laying out a board should IMO be doing a visual check
after layout anyway, and this should catch any glaring problems, ie, entire
designators sitting atop ajoining pad(s)...

Okay, I admit I can see a reason for DRC'ing ref-designators vs. pad holes,
anwyay, at least for dense designs...

aj

 -Original Message-
 From: Robert M. Wolfe [mailto:[EMAIL PROTECTED]]
 
 Well I guess that is also why when you move a Ref Des on a
 part that is tied to VCC or GND it take a bit of time
 to keep analyzing VCC under DRC. Never seen a
 system do that. I can see a need to specifically drc silkscreen
 to pads etc on the board but not every time you touch a Ref'Des.
 And yes you can turn off DRC bu tit still seems to do it and
 actually whay should you have to turn it off just to touch a 
 silkscreen?
 
 From: [EMAIL PROTECTED]
 
  Okay, call me dumb, but I am having a hard time 
  understanding how the DRC even comes into play,
  since the clearance constraint is, by definition,
  a constraint on copper layers only.
  Since the silkscreen is not a copper layer, the 
  clearance constraint shouldn't even be invoked...
 
  What am I missing in this equation?
 
   From: JaMi Smith [mailto:[EMAIL PROTECTED]]
  
   John,
  
   You are not doing anything wrong, it's just Protel.
   From: John Branthoover [EMAIL PROTECTED]
  
I have two (2) position jumpers with a rectangular
   silkscreen drawn around them.  I want to
 place them on my PCB such that one side of
   the silkscreen overlap
   
When I attempt this I get a violation as soon as the
   silkscreen over lap
   
What am I doing wrong?  

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Abd ul-Rahman Lomax
At 04:30 PM 1/17/2003, [EMAIL PROTECTED] wrote:

Frankly, I don't even understand concerns about silkscreen and pads. The
silkscreen simply will not be printed over the solder area, since the
pad-mask prevents adherence of the ink to these areas.


The component clearance rule is not about the silkscreen, it merely uses 
the silkscreen as an indicator of component extents. The idea is great, the 
implementation fell short. We have talked about dedicating a mech layer to 
a true component outline, the clearance rule would then use that layer, 
looking for clearance between the outlines. There are plenty of details to 
be worked out, such as tolerances -- part outlines would be drawn at MMC, 
not at nominal, and the clearance would either be centerline or the 
outline would compensate so that the outer edge of the outline trace was 
the maximum possible condition

Then the component clearance rule would actually refer to true component 
clearance (i.e. minimum clearance) instead of to some nominal value or worse.

The clearance function should look for distance between outline tracks on 
the component outline layer, not to the extents box, which does not work 
with some kinds of component shapes. The rule should also allow negative 
clearance, i.e., overlap (which, had it been done, would have allowed the 
present system to function well enough to use.)



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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 . Thanks....!

2003-01-17 Thread John Branthoover
Thanks again everyone for the response.  Again my lack of experience is
showing.  Oh well, I have to learn some how.  I hope that every body has a
nice weekend.

-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Friday, January 17, 2003 4:13 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
SP6 .


Andrew,
my understanding is that he is talking of the component placement
DRC check. It checks the area bounding all portions/layers of the land
pattern to the bounding area of the next land pattern. It isn't a copper
check but a component to component clearance check.
Like myself or a number of others, you probably have it turned off
since early in the P99 days.
Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


 -Original Message-
 From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
 Sent: Friday, January 17, 2003 12:05 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE
 SP6 .


 Okay, call me dumb, but I am having a hard time understanding
 how the DRC
 even comes into play, since the clearance constraint is, by
 definition, a
 constraint on copper layers only. Since the silkscreen is not a copper
 layer, the clearance constraint shouldn't even be invoked...

 What am I missing in this equation?

 aj


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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread JaMi Smith
I agree that turning off component clearance checking completely is a
solution of sorts, but I myself am not comfortable doing that, since I am
not quite perfect yet (almost, but not yet), and I would rather have to look
at an error on the screen due to a bogus problem with Protel 99 times out of
100 (is that where the 99 came from), as opposed to look at an error in the
built hardware just once because I blew it and it wasn't caught because I
turned off the clearance checking.

JaMi

- Original Message -
From: Brad Velander [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Friday, January 17, 2003 11:48 AM
Subject: Re: [PEDA] A Question About PCB Design Rules. Protel 99SE SP6 .


 John,
 adding to Jami's list.
 5) Do as I do, turn off the component placement DRC check completely. It
 just doesn't work in any usable manner. Use your eyes and personal
 knowledge.
 The component placement DRC uses any land pattern item, visible,
 invisible, regardless of layer to determine the maximum extent of the
 component. It then draws a bounding box around all these items, this
 constitutes the component boundary for the placement checking. Therefore
any
 designator, comment, text string, etc. gets included with the actual
desired
 component boundary.
 As you have found setting 0 allows placement down to touching but
 will still show a violation if items actually touch. I too think that this
 is a failing of Protel/Altium, a setting of 0 should allow items to
touch.
 It probably should allow overlap as well but I wouldn't push it that far
 because I don't see that being really useful or a common need.

 Sincerely,
 Brad Velander.

 Lead PCB Designer
 Norsat International Inc.
 Microwave Products
 Tel   (604) 292-9089 (direct line)
 Fax  (604) 292-9010
 email: [EMAIL PROTECTED]
 http://www.norsat.com


  -Original Message-
  From: John Branthoover [mailto:[EMAIL PROTECTED]]
  Sent: Friday, January 17, 2003 9:57 AM
  To: Protel EDA Forum
  Subject: [PEDA] A Question About PCB Design Rules. Protel
  99SE SP6.
 SNIP
 
  What am I doing wrong?  Any information that you can
  give will be greatly
  appreciated.  Thank you for your time and have a nice day.
 
 
 
  John Branthoover:
  Electrical Design Engineer  :
  Acutronic  R  D:Phone  (412) 968-1051
  640 Alpha Drive :Fax(412) 963-0816
  Pittsburgh PA 15238 :Email  [EMAIL PROTECTED]
  USA :WEBhttp://www.acutronic.com

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Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE SP6 .

2003-01-17 Thread Robert M. Wolfe
Abd ul-Rahman

Isn't this just really saying the silkscreen IS the defining factor
IMHO the silkscreen layer should never have been used as an indicator
or ultimately the real extents of a part. There really needs to be a user
defined layer that will be used at the extents of a part to check part
clearance.
And that layer does not necesarily have to be an assembly layer.
I have seen systems that define both actual part and real world
clearances required for assembly/test/rework etc., and control over
which rule pending level of technology required for design.
And line widths really should have nothing to do with it
when you are defining a clearance just center as if it were
a zero width line. Only silkscreen itself should be considered
for thickness itself with respect to all other features. But part
clearance should be to a dimension MMC, etc not ever dealing
with the thickness of a line defining it.

Bob Wolfe

 The component clearance rule is not about the silkscreen, it merely uses
 the silkscreen as an indicator of component extents. The idea is great,
the
 implementation fell short. We have talked about dedicating a mech layer to
 a true component outline, the clearance rule would then use that layer,
 looking for clearance between the outlines. There are plenty of details to
 be worked out, such as tolerances -- part outlines would be drawn at MMC,
 not at nominal, and the clearance would either be centerline or the
 outline would compensate so that the outer edge of the outline trace was
 the maximum possible condition


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