Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Mike Reagan



I know what the website says,   I also know what my hard earned money
says... I just purchased manuals about 2 months ago and had to pay full
price.Read my last post again , The IPC will not accept your coupon
unless you are full member of the IPC,  however they did honor the coupon
from the designer's council  in previous years.

Mike Reagan




- Original Message -
From: Abd ul-Rahman Lomax [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, July 10, 2001 1:38 AM
Subject: Re: [PEDA] Layer Stackup Info.


 At 08:55 PM 7/9/01 -0400, Mike Reagan wrote:

 I would like to correct you about the discount IPC offers. The coupon
they
 issue to the designers council members is not redeemable, you must be an
IPC
 member not a member of the designers  council.   They must have started
this
 policy this year because I redeemed my coupons in the past, but his year
 they did  not honor it when I purchased additional manuals.  Have they
 honored yours?  I had to pay full price.

  From the Designer's Council web site:

 Free Designers Council Membership!

 Did you know that when you join or renew your IPC Designers Council
 membership we give you a $50.00 coupon to be used towards attending a
 workshop or seminar or the purchase of IPC documents? This is like getting
 your IPC Designers Council membership for free! Also, up to three coupons
 can be saved up to use towards seminars or workshops. That's $150.00 off
 the price of a class! These are just some of the value added benefits that
 Designers Council members receive.

 The DC site implies that one may Save money on design by using IPC design
 standards, listing this as a benefit of membership, but it is not
explicit
 that one receives the same discount as IPC members on publications.

 However, on the page about the certification packages, there is a list of
 IPC publications for use in study for the exam, with member and
 nonmember prices. The non-member prices are the same as are advertised
to
 the public. The member prices are half the nonmember prices. When I
joined,
 I got the $50 coupon plus I paid the member prices. I was told that this
 was a benefit of membership.

 Perhaps only those specific publications are offered to DC members, which
 would be a tad misleading

 [EMAIL PROTECTED]
 Abdulrahman Lomax
 P.O. Box 690
 El Verano, CA 95433


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Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Abd ul-Rahman Lomax

At 07:22 AM 7/10/01 -0400, Mike Reagan wrote:

I know what the website says,   I also know what my hard earned money
says... I just purchased manuals about 2 months ago and had to pay full
price.Read my last post again , The IPC will not accept your coupon
unless you are full member of the IPC,  however they did honor the coupon
from the designer's council  in previous years.

I don't need to read it again, since I got it the first time. Mr. Reagan is 
reporting to us that the IPC did not honor the DC coupon. However, the DC 
is an IPC activity. When you join, you are joining the IPC/Designers Council.

Note that I wrote:

  Perhaps only those specific publications are offered to DC members, which
  would be a tad misleading

However, Mr. Reagan has now been even more explicit. It is not just that 
they do not offer the member price to DC members -- assuming that whoever 
told Mr. Reagan that was following IPC policy instead of simply being 
mistaken -- but also that they are not honoring the coupon *at all*.

The Designer's Council is clearly advertising in such a way as to cause a 
reasonable reader to believe that they will receive, for joining or 
renewing, a $50 coupon good toward IPC publications. If that is not true, 
they are guilty of consumer fraud.

However, since the Designer's Council is an IPC activity, and it has, with 
permission, used the IPC name, the IPC is responsible for promises DC 
makes. I would consider reminding them of this fact. The Designer's Council 
is not separately incorporated, at least not in Illinois.

I think they are also obligated to give the member discount *in addition*, 
but that is less obvious. Under consumer fraud laws in some states, they 
clearly would have this obligation. I was once served with a 
cease-and-desist order from the Arizona Attorney General's office for 
selling a single photocopy for 5 cents to a customer who was outraged 
because the sign outside said Copies 3 cents, and that only applied, by 
our stated policy in the store, to *additional* copies after the first 10. 
It was the best price in town, by far, but not low enough to satisfy that 
customer. Ironically, he was a rather wealthy acquaintance who did not know 
that I owned the business

If customers *are* deceived by making a reasonable construction of the 
advertising, it does not matter if there was no intention to deceive, the 
law has been violated. Mr. Reagan clearly thought that the coupon would be 
honored, and his expectation was clearly reasonable. I thought the same thing.



[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Ted Tontis

Mike,
What standards did you purchase? I believe that if you are a IPC
designer council member you can only purchase standards, visit seminars, and
use your coupon on subjects related to design. So assembly stuff is out. 

Abd ul-Rahman,
I just attended a IPC cert. course. There where a few people from
Motorola, Northrop, and other companies that have defense contracts with the
government. They told me that all of there designers have to be IPC cert.
and that the MIL. standards are slowly being replaced by IPC standards, per
some of there contracts. Most had been in the business for more than 15
years with feeling the need to be cert. Deter was our instructor and he had
stated that in the future all designers will have to be cert. before they
can get a job. Honestly I cant put much faith in information from some one
who works for IPC regarding this information. By the way the advanced IPC
cert. is going to be bataed this year.

Ted 

-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 10, 2001 6:23 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Layer Stackup Info.




I know what the website says,   I also know what my hard earned money
says... I just purchased manuals about 2 months ago and had to pay full
price.Read my last post again , The IPC will not accept your coupon
unless you are full member of the IPC,  however they did honor the coupon
from the designer's council  in previous years.

Mike Reagan




- Original Message -
From: Abd ul-Rahman Lomax [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, July 10, 2001 1:38 AM
Subject: Re: [PEDA] Layer Stackup Info.


 At 08:55 PM 7/9/01 -0400, Mike Reagan wrote:

 I would like to correct you about the discount IPC offers. The coupon
they
 issue to the designers council members is not redeemable, you must be an
IPC
 member not a member of the designers  council.   They must have started
this
 policy this year because I redeemed my coupons in the past, but his year
 they did  not honor it when I purchased additional manuals.  Have they
 honored yours?  I had to pay full price.

  From the Designer's Council web site:

 Free Designers Council Membership!

 Did you know that when you join or renew your IPC Designers Council
 membership we give you a $50.00 coupon to be used towards attending a
 workshop or seminar or the purchase of IPC documents? This is like getting
 your IPC Designers Council membership for free! Also, up to three coupons
 can be saved up to use towards seminars or workshops. That's $150.00 off
 the price of a class! These are just some of the value added benefits that
 Designers Council members receive.

 The DC site implies that one may Save money on design by using IPC design
 standards, listing this as a benefit of membership, but it is not
explicit
 that one receives the same discount as IPC members on publications.

 However, on the page about the certification packages, there is a list of
 IPC publications for use in study for the exam, with member and
 nonmember prices. The non-member prices are the same as are advertised
to
 the public. The member prices are half the nonmember prices. When I
joined,
 I got the $50 coupon plus I paid the member prices. I was told that this
 was a benefit of membership.

 Perhaps only those specific publications are offered to DC members, which
 would be a tad misleading

 [EMAIL PROTECTED]
 Abdulrahman Lomax
 P.O. Box 690
 El Verano, CA 95433


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*
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* http://www.techservinc.com/protelusers/leave.html
*  - or email -
* mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum
*
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Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Mike Reagan

it was all the latest 2141, controlled Z, 6011 generic standards, 6012 and
several other design standards.   Maybe I got snuckered, Like I mentioned
they honored it last year but not this year.  I will bring it up at the next
IPC meeting and see if anyone else had the same problem

Mike
- Original Message -
From: Ted Tontis [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Tuesday, July 10, 2001 10:01 AM
Subject: Re: [PEDA] Layer Stackup Info.


 Mike,
 What standards did you purchase? I believe that if you are a IPC
 designer council member you can only purchase standards, visit seminars,
and
 use your coupon on subjects related to design. So assembly stuff is out.

 Abd ul-Rahman,
 I just attended a IPC cert. course. There where a few people from
 Motorola, Northrop, and other companies that have defense contracts with
the
 government. They told me that all of there designers have to be IPC cert.
 and that the MIL. standards are slowly being replaced by IPC standards,
per
 some of there contracts. Most had been in the business for more than 15
 years with feeling the need to be cert. Deter was our instructor and he
had
 stated that in the future all designers will have to be cert. before they
 can get a job. Honestly I cant put much faith in information from some one
 who works for IPC regarding this information. By the way the advanced IPC
 cert. is going to be bataed this year.

 Ted

 -Original Message-
 From: Mike Reagan [mailto:[EMAIL PROTECTED]]
 Sent: Tuesday, July 10, 2001 6:23 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.




 I know what the website says,   I also know what my hard earned money
 says... I just purchased manuals about 2 months ago and had to pay full
 price.Read my last post again , The IPC will not accept your coupon
 unless you are full member of the IPC,  however they did honor the coupon
 from the designer's council  in previous years.

 Mike Reagan




 - Original Message -
 From: Abd ul-Rahman Lomax [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Tuesday, July 10, 2001 1:38 AM
 Subject: Re: [PEDA] Layer Stackup Info.


  At 08:55 PM 7/9/01 -0400, Mike Reagan wrote:
 
  I would like to correct you about the discount IPC offers. The coupon
 they
  issue to the designers council members is not redeemable, you must be
an
 IPC
  member not a member of the designers  council.   They must have started
 this
  policy this year because I redeemed my coupons in the past, but his
year
  they did  not honor it when I purchased additional manuals.  Have they
  honored yours?  I had to pay full price.
 
   From the Designer's Council web site:
 
  Free Designers Council Membership!
 
  Did you know that when you join or renew your IPC Designers Council
  membership we give you a $50.00 coupon to be used towards attending a
  workshop or seminar or the purchase of IPC documents? This is like
getting
  your IPC Designers Council membership for free! Also, up to three
coupons
  can be saved up to use towards seminars or workshops. That's $150.00 off
  the price of a class! These are just some of the value added benefits
that
  Designers Council members receive.
 
  The DC site implies that one may Save money on design by using IPC
design
  standards, listing this as a benefit of membership, but it is not
 explicit
  that one receives the same discount as IPC members on publications.
 
  However, on the page about the certification packages, there is a list
of
  IPC publications for use in study for the exam, with member and
  nonmember prices. The non-member prices are the same as are advertised
 to
  the public. The member prices are half the nonmember prices. When I
 joined,
  I got the $50 coupon plus I paid the member prices. I was told that this
  was a benefit of membership.
 
  Perhaps only those specific publications are offered to DC members,
which
  would be a tad misleading
 
  [EMAIL PROTECTED]
  Abdulrahman Lomax
  P.O. Box 690
  El Verano, CA 95433
 


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Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Mark E Witherite
 


Re: [PEDA] Layer Stackup Info.

2001-07-10 Thread Brad Velander

Ted  or Mark,
I hope you realize that those figure will be approx. averages for
differing materials of the general construction type. Don't rely on those
figures too heavily because individual constructions, resins and weaves
could vary those figures significantly (at least 10 - 15%, possibly 20 -
25%).

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Mark E Witherite [mailto:[EMAIL PROTECTED]]
 Sent: Tuesday, July 10, 2001 9:09 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 Thanks Ted,
  I have that book and knew I seen them somewhere.
 Cheers
 Mark
 At 03:24 PM 7/9/01 -0500, you wrote:
 
 
 Coefficient*10^-5
 
 MaterialLength  Cross
 XXXP1.2 1.7
 XXPC1.2 1.7
 FR-21.2 2.5
 FR-31.3 2.5
 CEM-1   1.1 1.7
 CEM-3   1.0 1.5
 FR-61.0 1.0
 G-101.0 1.5
 FR-41.0 1.5
 G-111.0 1.5
 FR-51.0 1.5
 GI  1.0 1.2
 
 HIGH FREQUENCY
 GT  1.0 2.5
 GX  1.0 2.5
 POLYSTYRENE 7.0 7.0
 CROSS LINKED
 POLYSTYRENE 5.7 5.7
 
 the table above is the change in length per unit of length 
 per degree
 change in temp. the coefficient may vary in different temp. 
 ranges so the
 temp. range must be specified.
 
 The table and the quote came from the Clyde F. Coombs JR. 
 Printed Circuit
 Handbook p8.21-p8.22.
 
 Hope this helps,
 
 Ted

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Mark E Witherite
 


Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Michael,
while I can generally agree with your advice you leave one aspect
wide open. If you do not specify your layer thickness, you could get a board
that works fine from manufacturer A, switch to manufacturer B and have a
board that doesn't work fine. The problem, one manufacturer used a stack up
with inter-layer thickness X, manufacturer B used inter-layer thickness Y
and the board now has different impedance, inductance characteristics. In a
lot of designs this would not cause a problem but then there could be that
one slightly longer clock trace or other timing or very level transition
sensitive signal which may not meet specs and cause a board failure. You ran
thousands of boards from one manufacturer and they worked fine, purchasing
changed manufacturers, ordered 10,000 and now none of them work reliably. Or
the techs nightmare, 50% of them fail but very unreliably.
Specifying just the minimum prepreg thickness does not give you any
control over the repeatability of that design and therefore does not meet
the IPC condition that any manufacturer should be able to build a working
version of your PCB. If you do not specify your total laminated prepreg
thickness, you are rolling the dice. I know of some manufacturers who will
by default use a 30 - 40 mil core, others will use a 20 mil core, if you do
not think this is significant to your design, that 'may' just be because you
don't know your design well enough. It is not always a matter of specifying
only for controlled impedances, it is a matter of specifying such that you
can get a reliable 'known' product from multiple manufacturers as the IPC
spec suggests.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Michael Reagan [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 8:28 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 Jeff,
 
 Word of advice...and this is a rule and a fab note we use for 
 all designs.
 We specify  a MIN  core and prepreg  thickness for all 
 layers, in one fab
 note. We spec .0035 inch min.   This gives your fabricator 
 the latitude to
 adjust for copper distribution, laminates he has in stock, epoxies,
 pressing, over all thickness variations, etc.  The only 
 conditions in which
 we specify a thickness and we only spec it for these layers, 
 are controlled
 impedance, and where the min dielectric breakdown voltage is 
 required for
 Bell-Core, FCC, and space applications.   My advice is to 
 leave the majority
 of your stack up determined by your board house, unless you 
 have specific
 reason to do otherwise.
 The IPC spec in 6012 for level 3 is to specify a design so 
 that any board
 house can build your design with the same result.   Remember you are
 designing/ writing  a specification,  give the fabricator 
 some latitude
 
 
 Mike Reagan
 EDSI
 Frederick  MD

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Michael Reagan


Brad,
You failed to either comprehend what I  wrote or I failed to communicate
what I wrote.

to clarify  IPC states
 Class C is a fully documented procurement package. Documentation is to the
extent that the information is self sufficient and be sent to multiple
vendors, with each producing the identical product. This documentation
package requires that all the full manufacturing allowances are disclosed
and documented.   This is an IPC spec and a very important one.   I write
specifications all the time, I did aprox 80 designs last year ranging in
various sizes and speeds to 2.7 Ghz. ( fast enough)  Any specification
should be written with the minimum requirements without tying your vendors
hands.   I am disappointed with you, that you would attack my credibility
for design.  My reputation stands fairly solid  and I am proud and confident
and outright cocky about my ability to understand high speed design issues,
impedance, propagation, wavelength, and any other topic you wish to take
offline.   I have never blasted anyone on this list, but I take issue with
your comments below

Mike Reagan



 Michael,
   while I can generally agree with your advice you leave one aspect
 wide open. If you do not specify your layer thickness, you could
 get a board
 that works fine from manufacturer A, switch to manufacturer B and have a
 board that doesn't work fine. The problem, one manufacturer used
 a stack up
 with inter-layer thickness X, manufacturer B used inter-layer thickness Y
 and the board now has different impedance, inductance
 characteristics. In a
 lot of designs this would not cause a problem but then there could be that
 one slightly longer clock trace or other timing or very level transition
 sensitive signal which may not meet specs and cause a board
 failure. You ran
 thousands of boards from one manufacturer and they worked fine, purchasing
 changed manufacturers, ordered 10,000 and now none of them work
 reliably. Or
 the techs nightmare, 50% of them fail but very unreliably.
   Specifying just the minimum prepreg thickness does not give you any
 control over the repeatability of that design and therefore does not meet
 the IPC condition that any manufacturer should be able to build a
 working
 version of your PCB. If you do not specify your total laminated prepreg
 thickness, you are rolling the dice. I know of some manufacturers who will
 by default use a 30 - 40 mil core, others will use a 20 mil core,
 if you do
 not think this is significant to your design, that 'may' just be
 because you
 don't know your design well enough. It is not always a matter of
 specifying
 only for controlled impedances, it is a matter of specifying such that you
 can get a reliable 'known' product from multiple manufacturers as the IPC
 spec suggests.

 Brad Velander,
 Lead PCB Designer,
 Norsat International Inc.,
 #300 - 4401 Still Creek Dr.,
 Burnaby, B.C., V5C 6G9.
 Tel. (604) 292-9089 direct
 Fax (604) 292-9010
 website www.norsat.com


  -Original Message-
  From: Michael Reagan [mailto:[EMAIL PROTECTED]]
  Sent: Monday, July 09, 2001 8:28 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Layer Stackup Info.
 
 
  Jeff,
 
  Word of advice...and this is a rule and a fab note we use for
  all designs.
  We specify  a MIN  core and prepreg  thickness for all
  layers, in one fab
  note. We spec .0035 inch min.   This gives your fabricator
  the latitude to
  adjust for copper distribution, laminates he has in stock, epoxies,
  pressing, over all thickness variations, etc.  The only
  conditions in which
  we specify a thickness and we only spec it for these layers,
  are controlled
  impedance, and where the min dielectric breakdown voltage is
  required for
  Bell-Core, FCC, and space applications.   My advice is to
  leave the majority
  of your stack up determined by your board house, unless you
  have specific
  reason to do otherwise.
  The IPC spec in 6012 for level 3 is to specify a design so
  that any board
  house can build your design with the same result.   Remember you are
  designing/ writing  a specification,  give the fabricator
  some latitude
 
 
  Mike Reagan
  EDSI
  Frederick  MD


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* mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum
*
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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Mike,
please settle down.  I am sorry that you felt I was attacking you
personally. I did not attack you or your comments, challenge you or your
experience, I only responded to your statement quoted below.

The only conditions in which we specify a thickness and we only
spec it for these layers, are controlled impedance, and where the min
dielectric breakdown voltage is required for Bell-Core, FCC, and space
applications.

Now does that not sound like the situation I was describing, it
sounds as though you were saying that you do not specify the dielectric
(laminate) thickness except in the specified conditions mentioned.

I cannot remember everyone's experience or abilities to best judge
when a statement may have been written poorly or conveyed the wrong idea. My
comment was to point out the possible danger (even in non-specific
performance requirements, i.e. basic digital circuits) of not specifying the
dielectric thickness in all cases. I hope that you can now see the issue
which I responded to, it was not a personal attack nor was it questioning
your abilities and I am sorry that you mistook it as such.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Michael Reagan [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 9:44 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 
 Brad,
 You failed to either comprehend what I  wrote or I failed to 
 communicate
 what I wrote.
SNIP
 
 Mike Reagan
 
 

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Dennis Saputelli

this is why business guys still fly all over to meet face to face, it's
easier and better
Dennis Saputelli

-- 
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Mark E Witherite
 


Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Thanks Mark,
the only one that I couldn't make a 'reasonable' guess at was the DS
(dimensional stability hadn't occurred to me), but then I would argue this
is a spec and one shouldn't have to guess. DS doesn't make much sense to me
when they talk of tolerance and CTE separately or by other titles (not
necessarily within the tables). The missing X/Y stabilities mystifies me
because I am sure that these various materials, weaves and resin contents
will vary significantly on X/Y stabilities and if those X/Y stabilities are
too mismatched in a stack up, watch out for your bow and twist spec.
I stopped trying to learn or use the IPC specs for materials a long
time ago because it just confused too many fabricators. I now just work
closely with them to determine which manufacturers materials meet our
requirements from their standard selection using standard required
performance details specific to our designs. I don't really care about the
weave or %RC but do care about the x/y/z stabilities, DK, thickness and loss
tangent.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Mark E Witherite [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 12:04 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 Hi Brad,
  Your right about the tables they are mislabeled. 
 They were correct 
 in the 9-26-99 document put out by The Copper Connection Inc.
 
 DS= dimensional Stability
 CHEM= Chemical resistance
 + = better
 - = worse
 %RC = % of resin content
 as for XY CTE you got me
 Cheers
 Mark

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Frank Gilley

Brad  Mark

XY CTE are Coefficient of Thermal Expansion, X and Y directions.

-Frank



At 02:03 PM 7/9/2001 -0500, you wrote:
Hi Brad,
 Your right about the tables they are mislabeled. They were 
 correct in the 9-26-99 document put out by The Copper Connection Inc.

DS= dimensional Stability
CHEM= Chemical resistance
+ = better
- = worse
%RC = % of resin content
as for XY CTE you got me
Cheers
Mark
At 09:21 AM 7/9/01 -0700, you wrote:
Mark,
 I read your comments and went to my IPC-. I am no IPC expert by
any stretch but aren't the tables you specify (4-2 ... 4-6) only for copper
clad laminates, where are the prepregs? Or is this a typical IPC f***up and
they have mislabeled their tables to imply something which was not intended,
I hate their documents because of these types of incongruities.
 Can anybody answer these questions in regards to these tables?

What is DS?
Where is the X  Y CTEs? Why are they not included?
What exactly is CHEM?
What do the +, - and blanks mean in the last three columns?

Damn the IPC is so stupid when it comes to their documents, you need a guide
to their guides because they don't adequately support their information.

 Oh, spotted one for Mike Reagan, see IPC- section 4.3.2. There
is your requirement for specifying individual dielectric thickness within
the stack up or else the manufacturer can do anything down to 0.09mm
(3.5mil) minimal thickness. Note that in all legal documents the word
Shall is synonymous with must, it is a requirement for the standard.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


  -Original Message-
  From: Mark E Witherite [mailto:[EMAIL PROTECTED]]
  Sent: Monday, July 09, 2001 9:35 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Layer Stackup Info.
 
 
  Hi Jeff,
   The IPC- is the one that has the prepreg and
  core info you
  want.  I have always let the board house decided how they are
  going to meet
  my specks of board thickness and layer separation.  Then have
  them send me
  the stack up configuration that they propose to use.  I then
  check their
  stack up with the tables (4.2 to 4.6) just to insure a good stack up.
  Cheers
  Mark
 

Mark Witherite
Assistant Research Engineer
Astronomy  Astrophysics
Penn State University
2565 Park Center Blvd
Suite 200
State College, PA.  16801
email [EMAIL PROTECTED]
telephone 814 865 9839
fax   814 865 9100
IPC PWB  Certified


Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Frank,
I am quite sure that both Mark and I both understood that. I (we?)
were wondering why they were not included in the IPC tables as a significant
piece of information when the materials quoted have such varying weaves and
resin contents. If significantly mismatched X/Y CTEs were mixed in a
stackup, it would contribute negatively to the board bow and twist.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Frank Gilley [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 11:35 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 Brad  Mark
 
 XY CTE are Coefficient of Thermal Expansion, X and Y directions.
 
 -Frank
 

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Frank Gilley

At 12:04 PM 7/9/2001 -0700, you wrote:
Frank,
 I am quite sure that both Mark and I both understood that. I (we?)
were wondering why they were not included in the IPC tables as a significant
piece of information when the materials quoted have such varying weaves and
resin contents. If significantly mismatched X/Y CTEs were mixed in a
stackup, it would contribute negatively to the board bow and twist.

Yes it would.  Sorry, I should have known you guys knew what that meant :)
Misunderstandings all round today, I guess.

Frank


Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Mark E Witherite
 


Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Ted Tontis

Warning
Could not process message with given Content-Type: 
multipart/mixed;boundary=_=_NextPart_000_01C108B5.1E11F280




Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Abd ul-Rahman Lomax

At 08:41 AM 7/9/01 -0700, Brad Velander wrote:
Michael,
 while I can generally agree with your advice you leave one aspect
wide open. If you do not specify your layer thickness, you could get a board
that works fine from manufacturer A, switch to manufacturer B and have a
board that doesn't work fine.


I want to underscore this.

If one is comfortable with a particular fabricator, there is no harm asking 
that fabricator what thicknesses they would recommend based on what is 
easily available, and then writing that into the board stackup 
specification. Work with the fabricator.

The down side of this would be that a less than scrupulous fabricator might 
suggest a thickness that they happen to have a lot of and need to dump. But 
that is not very likely.

IPC- does have a table of laminates.

If you join the IPC Designer's Council, $50, you get -- last time I looked 
-- a $50 credit toward publications, *and* you get the publications at the 
member prices.

The sizes of FR-4 material marked in the chart as low cost are, in mm.:

0.07
0.11
0.13
0.18
0.26
0.32
0.37
0.43
0.53
0.61
0.64
0.74
1.52 is not given the lowest cost value, but it is very available.


Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA license resales
Sonoma, California, USA
(707) 939-7021, efax (419) 730-4777
[EMAIL PROTECTED]
[EMAIL PROTECTED]


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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Michael Reagan

Abdul and Brad,
If your design is critical to   a particular thickness, then yes you must
specify it. no doubt, however if it aint, specify the min acceptable and
give your design house the latitude to build up.   Funny we are all on this
subject, I plan to submit a paper to PCD magazine, about board specification
and fab notes later this month or early next month.

 -Original Message-
 From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 5:15 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.


 At 08:41 AM 7/9/01 -0700, Brad Velander wrote:
 Michael,
  while I can generally agree with your advice you leave
 one aspect
 wide open. If you do not specify your layer thickness, you could
 get a board
 that works fine from manufacturer A, switch to manufacturer B and have a
 board that doesn't work fine.


 I want to underscore this.

 If one is comfortable with a particular fabricator, there is no
 harm asking
 that fabricator what thicknesses they would recommend based on what is
 easily available, and then writing that into the board stackup
 specification. Work with the fabricator.

 The down side of this would be that a less than scrupulous
 fabricator might
 suggest a thickness that they happen to have a lot of and need to
 dump. But
 that is not very likely.

 IPC- does have a table of laminates.

 If you join the IPC Designer's Council, $50, you get -- last time
 I looked
 -- a $50 credit toward publications, *and* you get the
 publications at the
 member prices.

 The sizes of FR-4 material marked in the chart as low cost are, in mm.:

 0.07
 0.11
 0.13
 0.18
 0.26
 0.32
 0.37
 0.43
 0.53
 0.61
 0.64
 0.74
 1.52 is not given the lowest cost value, but it is very available.


 Abd ul-Rahman Lomax
 LOMAX DESIGN ASSOCIATES
 PCB design, consulting, and training
 Protel EDA license resales
 Sonoma, California, USA
 (707) 939-7021, efax (419) 730-4777
 [EMAIL PROTECTED]
 [EMAIL PROTECTED]



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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Mike,
re-reading your original post a couple of times, and this new
message, I am still a little confused about not what you are spec'ing but
the possible variations one could see in circuit performance. 

I am pretty sure I now understand exactly what you are spec'ing and
'your' reasons for doing such. Then my thoughts immediately flash to the
possible variation in your build-up and the possible electrical
ramifications of that methodology. I may be wrong because of the sensitivity
of our company's circuits but I would think that somewhere your method could
be a disaster for the unwary. And on that note, it is my belief that most
design shops do not do 'any' signal integrity simulation, especially across
such a possible wide variation of build up profiles.

Well I look forward to your article in PCD. I am betting it will
probably be a useful article, rather then the usual articles telling us
everything that we already knew or didn't know, in general terms and not
really supplying any useful knowledge or techniques.

Mike, do you know it will be published, or is this a hopeful
submission?

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Michael Reagan [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 2:41 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 Abdul and Brad,
 If your design is critical to   a particular thickness, then 
 yes you must
 specify it. no doubt, however if it aint, specify the min 
 acceptable and
 give your design house the latitude to build up.   Funny we 
 are all on this
 subject, I plan to submit a paper to PCD magazine, about 
 board specification
 and fab notes later this month or early next month.
 

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Abd ul-Rahman Lomax

At 09:21 AM 7/9/01 -0700, Brad Velander wrote:
Mark,
 I read your comments and went to my IPC-. I am no IPC expert by
any stretch but aren't the tables you specify (4-2 ... 4-6) only for copper
clad laminates, where are the prepregs? Or is this a typical IPC f***up and
they have mislabeled their tables to imply something which was not intended,
I hate their documents because of these types of incongruities.
 Can anybody answer these questions in regards to these tables?

What is DS?
Where is the X  Y CTEs? Why are they not included?
What exactly is CHEM?
What do the +, - and blanks mean in the last three columns?

Damn the IPC is so stupid when it comes to their documents, you need a guide
to their guides because they don't adequately support their information.

I'm not convinced that the IPC specifications were put together by the best 
and brightest in our field, but let's assume that it was. Unfortunately, 
being the best and brightest designer or engineer does not make one the 
best and brightest technical writer.

As to a guide to the guides, they will also sell you that. (The IPC PWB 
Designer Certification Study Guide). Unfortunately -- I've been using that 
word a lot today, haven't I? -- it does not cover the questions Mr. 
Velander asked.

However, if you read the specification several times, you might notice that 
4.3.6 explains that the tables provide information on the properties of 
finished bare laminates for different prepreg constructions. To establish 
final laminate thickness with copper, add 35 um for each oz. of copper on 
the laminate.

I could guess at what some of the abbreviations mean, but it would be just 
that: a guess.

Here are my guesses:

DS: Dielectric Strength (this would be measured in volts/mm, for example)
Or it might mean Dimensional Stability.

Z CTE: Coefficient of Thermal Expansion in the Z axis (i.e., thickness). I 
don't know why the X and Y CTEs are not given.

By the way, looking into this made me realize that the tables cover 
laminate, not prepreg. There are other specs for prepreg, IPC-L-109 and 
IPC-4101. Full employment for IPC staff!

+ means better, and - means worse, and a blank is in between. It's an 
intelligence test. As a consolation, it took me about an hour to figure 
this out. There is a little + after the Better label on the symbol chart.

What DRILL means in this chart I find obscure.

I've managed to avoid, in my career, highly-specified boards for military 
or other use; other boards have simply referred to the specification, and 
the engineer did not understand the specification any more than anyone 
else. I think the idea is that if the board turns out to have a problem, 
and you just made 10,000 of them, you could do the research to find out 
what the spec means and thus if the fabricator violated it. But if one has 
specified the prepreg material, that won't work, since the fabricator will 
have followed specific instructions, and the chart was merely a design 
guide, not a specification, per se.

In other words, the IPC has mixed a design guide with a specification. They 
are different animals and should not be combined. They have done this all 
over the place. It makes the documents hard to read as design guides and 
even harder to read as specifications.

Sorry, mention the IPC and I tend to get a little steamed. They are living 
in a world about twenty years old, before the internet.

I asked them why the CD version of the design certification kit was more 
expensive than the printed version. I was told that it was because they had 
a warehouse full of the printed versions and they needed to get rid of 
them. Way to go!

Not only does this mean that they made a serious error in their print run, 
but they also apparently never heard of print-on-demand, which for 
specifications is most appropriate. Otherwise you end up delaying the next 
rev until that warehouse starts to look empty.

g

I was a member of the Designer's Council, it recently lapsed and I haven't 
renewed yet. The Designer's Council is not responsible to the members, it 
is a top-down organization. You can find the list of the Board of Directors 
on http://www.ipc.org/html/designeb.htm

The site is not specific about this, but from that fact that I never heard 
of anything like elections, as a member-at-large, I would assume that it is 
a typical non-profit with a self-electing board; that is, the board elects 
its successor members. They might pay attention to local council 
recommendations, they might not.

Such organizations tend to become turgid bureaucracies in spite of the best 
intentions. It can be just as bad when the members can vote, if the 
organizations are very large and the members not highly motivated to vote, 
and proxy voting is allowed, and the board has privileged access to the 
members for the issuance of proxies. An example is the California State 
Automobile Association, which is largely a device for selling insurance. 

Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Brad Velander

Adb ul-Rahman,
sometimes you make me laugh because your thoughts, although written
differently, are identical to mine.
You stumbled onto the same conclusion that I had, these charts do
seem to be for finished laminate not prepreg. Then one must wonder about
what was being checked for stackups if a main component was missing
(prepreg)?
Mark, do you have one of these stackups in electronic form? I would
be interested in seeing what you fabricator does for this as compared to my
contact with other fabricators.

My take on the Drill column was that it was a general rating for
drilling of the material. Better, 'blank'  worse.

I believe that I have just found a glaring technical error in the
charts for FR4 and High Tg FR4. Notice how there are absolutely no
differences in the Dk across the two sets of materials? My experience tells
me that this is impossible, different Tg = different resin, different resin
= different Dk, I have never seen the same Dk spec from any manufacturer
across their regular or high Tg rated materials, there is always a variance.
Seems somebody at IPC might have taken a shortcut instead of actually
researching their materials.
See even the IPC knows that nobody is actually supposed to read all
their material. 8^

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
 Sent: Monday, July 09, 2001 3:45 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Layer Stackup Info.
 
 
 At 09:21 AM 7/9/01 -0700, Brad Velander wrote:
 Mark,
  I read your comments and went to my IPC-. I am 
 no IPC expert by
 any stretch but aren't the tables you specify (4-2 ... 4-6) 
 only for copper
 clad laminates, where are the prepregs? 
SNIP
 
 However, if you read the specification several times, you 
 might notice that 
 4.3.6 explains that the tables provide information on the 
 properties of 
 finished bare laminates for different prepreg constructions. 
 To establish 
 final laminate thickness with copper, add 35 um for each oz. 
 of copper on 
 the laminate.
 
snip
 
 By the way, looking into this made me realize that the tables cover 
 laminate, not prepreg. There are other specs for prepreg, 
 IPC-L-109 and 
 IPC-4101. Full employment for IPC staff!
 
SNIP

 What DRILL means in this chart I find obscure.
 
SNIP
 
 [EMAIL PROTECTED]
 Abdulrahman Lomax
 P.O. Box 690
 El Verano, CA 95433

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Abd ul-Rahman Lomax

First of all, none of what I have written was intended as a personal 
attack, you stupid idiots!

***JOKE!!!*** No one writing here is stupid, though sometimes some of us 
could use a little coffee.

At 05:41 PM 7/9/01 -0400, Michael Reagan wrote:
Abdul and Brad,
If your design is critical to   a particular thickness, then yes you must
specify it. no doubt, however if it aint, specify the min acceptable and
give your design house the latitude to build up.

Brad's point, and mine, is that one may not think the thickness critical, 
but thickness *will* vary the high-speed performance of the board (and a 
few other things which are not so likely to cause trouble). If the board is 
all low frequency analog, no problem. But if the board has even one or two 
digital nets with fast transitions, thickness variations will cause 
differing amounts of ringing, crosstalk, and radiated noise.

So a board that works from one vendor might not work with another. It would 
be a shame to discover that after one has tested a board with prototypes 
from one vendor and maybe a small production run, and then, for a large 
batch where the economics are forceful, has bought the boards elsewhere.

*I have seen this happen.*

Now, I have actually followed Mr. Reagan's described practice. The vast 
majority of my designs, over the years, have not specified many details of 
board fabrication but have instead relied upon the fabricator's standard 
production characteristics. So I have not followed the advice I am now 
giving. I should.

Funny we are all on this
subject, I plan to submit a paper to PCD magazine, about board specification
and fab notes later this month or early next month.

Therefore it is a great time to review the subject and to consider new ideas.

In another post, Mr. Reagan wrote:

to clarify  IPC states
  Class C is a fully documented procurement package. Documentation is to the
extent that the information is self sufficient and be sent to multiple
vendors, with each producing the identical product. This documentation
package requires that all the full manufacturing allowances are disclosed
and documented.   This is an IPC spec and a very important one.   I write
specifications all the time, I did aprox 80 designs last year ranging in
various sizes and speeds to 2.7 Ghz. ( fast enough)  Any specification
should be written with the minimum requirements without tying your vendors
hands.

IPC 2221 4.2.1.2 notes that some laminate or prepreg characteristics 
*shall* not be included on the master drawing. I do not specify the 
thickness of the material, but of the finished product. How the fabricator 
gets there is his business; but if the board is a multilayer board, the 
finished internal dimensions are normally a critical attribute. Normally, 
I've seen layer distances specified as nominal value without stated 
tolerances, unless the board is controlled impedance, in which case 
impedance may be specified, with tolerance, rather than dielectric gap. 
Again, the fabricator can figure out how to get there.

The advantage of specifying impedance is that it can be measured without 
slicing up the board.

So, unless it is critical, fully specifying dielectric thickness can be 
omitted, but the nominal values should *not* be omitted, because it would 
then be possible for a fabricator to wildly vary the thickness, making it 
more likely that a significant change will take place in board performance.

I don't have a copy of D-325, which is the PWB documentation standard, but 
I would read the certification guide's restatement of it on this point as 
requiring nominal dimensions on the master drawing for Class B 
documentation (5.1, p. 132). Class C documentation, essentially, is fully 
defined including tolerances, Class B is less formal. Class A is usually 
used for internal use.

What is the difference, by the way, between usually used for internal 
use, usually for internal use, or normally for internal use, the 
latter two being good writing? But for the IPC publications, this is not 
bad, at least it is reasonably clear!

Mike, why not submit your article to a few designers for review before it 
is finalized for publication? Many heads, almost always, think better than 
one; you'd still be the organiser and writer!

The best list for discussion of this topic is probably the Designer's 
Council list Most Protel people are electronics engineers less involved 
with formal specifications and more likely to do a Class A-documented 
design. There are exceptions, of course.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Mike Reagan



 Mike, why not submit your article to a few designers for review before it
 is finalized for publication? Many heads, almost always, think better than
 one; you'd still be the organiser and writer!

 The best list for discussion of this topic is probably the Designer's
 Council list Most Protel people are electronics engineers less
involved
 with formal specifications and more likely to do a Class A-documented
 design. There are exceptions, of course.



Mr. Lomax,
I currently am a member of the Chesapeake Designers Council and have spoken
and at several meetings.  I am also a member of the Washington Chapter SMTA.
I make every effort to attend every meeting I can.  I find the forum
valuable.  As for submitting a  preliminary to anyone on this list, I would
be glad to  submit my article  for critic and input.   I have spent the past
several months honing a set of 24 design notes that I feel are very
important to the fabrication of boards.   Don't laugh ...yes it took me
several months because my primary duties are design and cough cough
management.   Anyone interested in helping me, please email me directly.   I
still need to contact Ronda Faries at PCD this week, but I am going on
vacation in the next few days so you wont have me kick around anymore. ( BAD
BRAD)
I would like to correct you about the discount IPC offers. The coupon they
issue to the designers council members is not redeemable, you must be an IPC
member not a member of the designers  council.   They must have started this
policy this year because I redeemed my coupons in the past, but his year
they did  not honor it when I purchased additional manuals.  Have they
honored yours?  I had to pay full price.


Mike Reagan
[EMAIL PROTECTED]

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Re: [PEDA] Layer Stackup Info.

2001-07-09 Thread Abd ul-Rahman Lomax

At 08:55 PM 7/9/01 -0400, Mike Reagan wrote:

I would like to correct you about the discount IPC offers. The coupon they
issue to the designers council members is not redeemable, you must be an IPC
member not a member of the designers  council.   They must have started this
policy this year because I redeemed my coupons in the past, but his year
they did  not honor it when I purchased additional manuals.  Have they
honored yours?  I had to pay full price.

 From the Designer's Council web site:

Free Designers Council Membership!

Did you know that when you join or renew your IPC Designers Council 
membership we give you a $50.00 coupon to be used towards attending a 
workshop or seminar or the purchase of IPC documents? This is like getting 
your IPC Designers Council membership for free! Also, up to three coupons 
can be saved up to use towards seminars or workshops. That's $150.00 off 
the price of a class! These are just some of the value added benefits that 
Designers Council members receive.

The DC site implies that one may Save money on design by using IPC design 
standards, listing this as a benefit of membership, but it is not explicit 
that one receives the same discount as IPC members on publications.

However, on the page about the certification packages, there is a list of 
IPC publications for use in study for the exam, with member and 
nonmember prices. The non-member prices are the same as are advertised to 
the public. The member prices are half the nonmember prices. When I joined, 
I got the $50 coupon plus I paid the member prices. I was told that this 
was a benefit of membership.

Perhaps only those specific publications are offered to DC members, which 
would be a tad misleading

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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