Re: [PEDA] Padstack

2001-12-02 Thread Michael Beavis
Free pads, by definition, do not appear on the schematic. I read this post from Mr. Beavis and was pretty shocked. I was about to start railing at the programmers who would allow Free-padname to be deleted as if it were a component. But I tried it first. I could not get free pads to

Re: [PEDA] Padstack

2001-11-30 Thread Ian Wilson
On 11:59 PM 29/11/2001 -0500, Abd ul-Rahman Lomax said: At 11:27 AM 11/30/01 +1100, Michael Beavis wrote: Free pads allow for more powerful design rules to be employed but it is possible to lose them when synchronising from SCH if care is not taken. If the 'Delete component' option is selected in

Re: [PEDA] Padstack

2001-11-30 Thread Brooks,Bill
: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 29, 2001 9:00 PM To: Protel EDA Forum Subject: Re: [PEDA] Padstack At 11:27 AM 11/30/01 +1100, Michael Beavis wrote: Free pads allow for more powerful design rules to be employed but it is possible to lose them when

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
Hi Wesley, This is what I would do, if I understand what you described... Make a physical clearance in the inner plane where you put the via so it will not connect... If you are using power/gnd planes and not polygon fills then you need to just put a fill or pad in the area on the negative

Re: [PEDA] Padstack

2001-11-29 Thread rlamoreaux
Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want the voltage to see them before the leg of the

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 10:55 AM 11/29/01 -0500, Wesley Webb wrote: Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 08:40 AM 11/29/01 -0800, Brooks,Bill wrote: Make a physical clearance in the inner plane where you put the via so it will not connect... If you are using power/gnd planes and not polygon fills then you need to just put a fill or pad in the area on the negative layer where the via is, and make

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
:[EMAIL PROTECTED]] Sent: Thursday, November 29, 2001 9:30 AM To: Protel EDA Forum Subject: Re: [PEDA] Padstack Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
PROTECTED]] Sent: Thursday, November 29, 2001 10:19 AM To: Protel EDA Forum Subject: Re: [PEDA] Padstack At 10:55 AM 11/29/01 -0500, Wesley Webb wrote: Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want

Re: [PEDA] Padstack

2001-11-29 Thread Geoff Harland
Can anyone tell me if it is possible make a via or pad that is connected to the Vcc net on the top and bottom layers only. TI do not want to connect it to the inner Vcc plane as the decoupling caps are on the secondary side of the pcb and I want the voltage to see them before the leg of the

Re: [PEDA] Padstack

2001-11-29 Thread Michael Beavis
Place a free PAD out there and call it '1', connect the net to 'gnd'. Then you can define a rule for plane connect and set the power plane connect style filter kind to PAD and and look for free pad 1 and set the Rule Attributes to No Connect. This will make a clearance around the pad

Re: [PEDA] Padstack

2001-11-29 Thread Brooks,Bill
/bbrooks/pca/pca.htm -Original Message- From: Michael Beavis [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 29, 2001 4:27 PM To: Protel EDA Forum Subject: Re: [PEDA] Padstack Place a free PAD out there and call it '1', connect the net to 'gnd'. Then you can define a rule

Re: [PEDA] Padstack

2001-11-29 Thread Abd ul-Rahman Lomax
At 11:27 AM 11/30/01 +1100, Michael Beavis wrote: Free pads allow for more powerful design rules to be employed but it is possible to lose them when synchronising from SCH if care is not taken. If the 'Delete component' option is selected in the sync process and the free pads do not appear on the