Re: [PEDA] polygon plane clearance question

2002-12-05 Thread Rene Tschaggelar
Hmm,
a 300 Volt track should perhaps have a bit more clearance
than just 10mil. Set that under Design rules, clearances,
there make a new one and do it for one or more specific nets.


Rene


rimas wrote:

hi there protel users,

this question has two parts - one specific to protel and one not.  first 
the general PCB design question - what kind of clearance should there 
usually be between traces and a polygon plane that surrounds them?  is 
manufacturability the only issue (so use the same clearance you use 
between any two traces on the rest of the board)?  or is there some 
reason to keep the ground pour further away ?  is there a way in protel 
to set this clearance?  also i'm not clear on why sometimes solid pours 
are used and sometimes hatch filled pours are used.  and what are 
standard values to use for grid size, track width, and minimum primitive 
size length ?

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Re: [PEDA] polygon plane clearance question

2002-12-05 Thread ajenkins
Yup, exactly what I intended to write when I first saw the query...

For the author of the original query or anyone else who's interested and
isn't yet up-to-speed on the subj of trace/track spacing and working
voltages, an example article that covers this topic with some specificity is
located at: http://www.vutrax.co.uk/vbook3.htm#voltage
where 1 short page of reading w/working eq. sums up this side of the query
rather well, IMO...

aj

 -Original Message-
 From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
 
 Hmm,
 a 300 Volt track should perhaps have a bit more clearance
 than just 10mil. Set that under Design rules, clearances,
 there make a new one and do it for one or more specific nets.


I dunno...If you're designing an arcing short circuit PCB...;)
 
 rimas wrote:
  hi there protel users,
  
  this question has two parts - one specific to protel and 
  what kind of clearance one not.  first the general PCB 
  design question -should there usually be between traces
  and a polygon plane that surrounds them? is
  manufacturability the only issue?...

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Re: [PEDA] polygon plane clearance question

2002-12-05 Thread Brad Velander
Cmon Rene,
I didn't have time to write a book. Likewise one wouldn't typically
route 300volts at 4 mil tracks and spaces now would you? There are always
other confining requirements and regulations.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

Check out our fall promotion at www.norsat.com. Limited quantities. Sale
ends December 24, 2002.
Contact your Account Manager or call 1-800-NII-4LNB or email
[EMAIL PROTECTED]



 -Original Message-
 From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
 Sent: Thursday, December 05, 2002 3:51 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] polygon plane clearance question
 
 
 Hmm,
 a 300 Volt track should perhaps have a bit more clearance
 than just 10mil. Set that under Design rules, clearances,
 there make a new one and do it for one or more specific nets.
 
 
 Rene

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Re: [PEDA] polygon plane clearance question

2002-12-03 Thread Brad Velander
Rimas,
first of all there are no standard answers to most of your questions
it varies greatly. Here are my answers to those issues. First I assume that
you are using P99SE SP6.

Controlling polygon clearance separate from trace-trace clearance in P99SE.
You can set-up Design Rules that define the spacing requirements
for polygons separate from the general space clearance. Under clearance
constraints add a new rule. For item one use Object Type and then check
the polygon checkbox. You can add other conditions by adding further rules
scopes to that item. Secondly, define the second item as specifically as
needed or just generically as Board. Set your desired spacing.

Spacing a polygon from traces.
There is no generic answer for this one. Consider fabrication
issues, so many points spaced just X amount from the other traces (both
sides of the traces as well). Consider the polygon in close proximity
reduces trace impedance. Consider how your spacing will effect pouring the
polygon into every point that you desire connectivity across the polygon.
Generally I would space polygons approx. 15 - 20 mils from other traces
while routing a 8 mil trace and space board. 
 On a tighter board I might go down to 10 mils but always would maintain a
polygon clearance that is wider than my narrowest trace gap. Why temp fate?

Cross-hatched or Solid polygons.
This used to be much more of an issue because of technology
limitations at the fabrication end. Today it is usually not an issue
depending on the specifications of your board. Soldermask never stuck good
to tin-lead, thus in past days it would not stick well to a solid tin-lead
plated polygon. They got around this by using cross-hatched polygons where
the mask could adhere to the laminate between the cross-hatching. Same story
from some vendors regarding gold plating. A large number of vendors do not
even mention this today because of the advances in soldermask adherence to
most plating types. another issue that reduced this complaint was the advent
of SMOBC (Soldermask Over Bare Copper) boards, no tin-lead under the mask.
Another issue was copper balance for plating and etching, large
chunks of unplated/unetched copper while trying to maintain even
controllable copper plating and etching across a whole board or panel of
boards. Copper balance is still an issue today although it has been greatly
minimized except in the most rigid conditions.
Sorry I never used cross-hatched polygons enough in the good old
days to recommend a good grid sizing.

General Features of a Polygon.
Here are my comments about the set-up features for a Polygon. Track
width, as large as you can allow. Grid spacing, set it to 0mils, this will
space the tracks reliably edge to edge regardless of track size. Minimum
primitive length, I use 3 mils.

Not the end all answer to your questions but should point you in the right
directions for further questions. 

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

Check out our fall promotion at www.norsat.com. Limited quantities. Sale
ends December 24, 2002.
Contact your Account Manager or call 1-800-NII-4LNB or email
[EMAIL PROTECTED]



 -Original Message-
 From: rimas [mailto:[EMAIL PROTECTED]]
 Sent: Tuesday, December 03, 2002 12:15 PM
 To: Protel EDA Forum
 Subject: [PEDA] polygon plane clearance question
 
 
 hi there protel users,
 
 this question has two parts - one specific to protel and one 
 not.  first 
 the general PCB design question - what kind of clearance should there 
 usually be between traces and a polygon plane that surrounds 
 them?  is 
 manufacturability the only issue (so use the same clearance 
 you use between 
 any two traces on the rest of the board)?  or is there some 
 reason to keep 
 the ground pour further away ?  is there a way in protel to set this 
 clearance?  also i'm not clear on why sometimes solid pours 
 are used and 
 sometimes hatch filled pours are used.  and what are standard 
 values to use 
 for grid size, track width, and minimum primitive size length ?
 
 thanks for any help, sorry for the naive question
 
 -rimas

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