Re: [PEDA] Thermal Reliefs to Internal Planes

2001-07-12 Thread Dennis Saputelli
the pad is round in the inner layers Dennis Saputelli [EMAIL PROTECTED] wrote: Hi, I'm completing my first board, in 99SE SP5, with connections to internal planes. I've noticed some questionable behavior and I'd like to confirm my experience is normal. 1.) Protel does not create

Re: [PEDA] Thermal Reliefs to Internal Planes

2001-07-12 Thread Steve Smith
Square pads are usually designating pin 1 or some other such special designation and would serve no purpose on an internal layer as you can not see them on the finished board. Remember that internal planes are viewed as negative images i.e. that where you see a pad there is no copper so that if

Re: [PEDA] Library problem, global search replace.

2001-07-12 Thread Brian Guralnick
Hi Richard, Actually, there might be a dirty way to do almost exactly what you want. Brian's dirty way, I think this should work, haven't tried it yet. Place library, or all components in a schematic keep this schematic. When you want to do a global search replace, or change in your

Re: [PEDA] Thermal Reliefs to Internal Planes

2001-07-12 Thread Brad Velander
Steve, OK seems that I did not understand all the details of the pad straddling a split plane but I was partly correct at least. In other words, the DRC may not reliably catch the possible faults. I said I was no expert. You seem to understand the basics of the error message. It is

Re: [PEDA] Library problem, global search replace.

2001-07-12 Thread Abd ul-Rahman Lomax
At 02:04 PM 7/12/01 -0400, Brian Guralnick wrote: Actually, there might be a dirty way to do almost exactly what you want. Brian's dirty way, I think this should work, haven't tried it yet. I did try it before writing my post on this subject, and I gave the results: Another path, through the

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Ted Tontis
You would hope that with as many people who have had this problem or needed a work around, Protel would realize that they should add something to the design rules. Possibly a design rule that lets you have a zero clearance between a net. Or the ability to open the track attributes and check a box

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Brad Velander
Well Ted it is supposed to be possible through the Short Circuit Constraint in the Other Design Rules Tab. Last anybody ever tried it, it still didn't work but that was a little while ago. That might have been before SP6, I don't remember. Brad Velander, Lead PCB Designer, Norsat International

Re: [PEDA] Thermal Reliefs to Internal Planes

2001-07-12 Thread Abd ul-Rahman Lomax
At 02:18 PM 7/12/01 -0400, [EMAIL PROTECTED] wrote: I just ran the full DRC and it's a bit worked up. I'm not sure I understand what it's trying to tell me. Violation Net NetR100_2 Warning - Connection to overlapping split planes I think this means that R100 is placed over two

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Brad Velander
I believe that Ian may be the keeper of the Wish list. I am not sure that I like the sounds of editing a trace to allow a short. My preference would be through the design rules so that it can be found and checked down the road instead of being hidden in the trace properties. Brad Velander, Lead

Re: [PEDA] perimeter stitched ground vias question

2001-07-12 Thread Mark E Witherite

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Brendon Slade
Hi Steve. The responses I have seen so far were in answer to the original dilemma of joining analogue gnd and digital gnd at one point without DRC errors. I think this solution doesn't meet your requirements - tha is if I'm reading your intentions correctly. I have used these shorted jumpers

Re: [PEDA] perimeter stitched ground vias question

2001-07-12 Thread Jon Elson
Brad Velander wrote: I did recently see an article on this exact question. It was thoroughly tested using field solvers and the field solvers confirmed the reduction of radiation from traces designed to the 20H rule. Sorry can't look for the article right now and have no recollection of

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Ian Wilson
On 04:03 PM 12/07/2001 -0400, [EMAIL PROTECTED] said: Protel is doing its job. I'm looking for a better way to do my job. I have a footprint which performs as a jumper for me. That is, two pads connected together by a trace. My schematic symbol for this part is two pins with different

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Brad Velander
Steve, I believe that you are giving up too easy, regardless of what Brendon had said, I am sure that a variation of the virtual short will do what you want. Use two pads which are narrow to make your shorting bar, use fills, traces or anything else to make the rest of the pattern. Using

Re: [PEDA] Trace jumpers generate DRC violations

2001-07-12 Thread Abd ul-Rahman Lomax
At 04:03 PM 7/12/01 -0400, [EMAIL PROTECTED] wrote: Protel is doing its job. I'm looking for a better way to do my job. Yes. Some designers would just suffer through, perhaps cursing the program because it is limited in certain ways. But it is not as limited as it might seem, so the small

[PEDA] 20H rule, Planes etc (Ex: perimeter stitched ground vias question)

2001-07-12 Thread Ian Wilson
G'Day all. I have been wondering about this (the 20H rule for planes) for some time. I have been trying to think of practical situations (rather than theoretical) why there may be some advantage. First off - I agree that if both planes are equally noisy then keeping them the same extents is

Re: [PEDA] 20H spacing to plane boundaries.

2001-07-12 Thread Brad Velander
Jon, yes it is a different story as I had mentioned myself if you had read far enough. If you did read far enough then you must just be looking for something or someone to bitch at. The response was a flow of thoughts, not a technical paper. I didn't have time to go back and edit it as I

Re: [PEDA] 20H rule, Planes etc (Ex: perimeter stitched ground vi as question)

2001-07-12 Thread Bruce Walter
My understanding of the 20H rule, was with regard to planes. If the planes have noise fields between them (I don't know how this can be avoided, regardless of component/trace/via placement), when the planes end equally at the edge of the board, this makes a nice dipole antenna, and the noise

Re: [PEDA] 20H rule, Planes etc (Ex: perimeter stitched ground vi as question)

2001-07-12 Thread Bruce Walter
That's exactly what I was implying. The effect would be local to where the trace and the plane edge coincide, and the radiation would be a function of field strength (i.e. dc/analog/slow control signals would have very little, 5GHz clock would be very high). -Original Message- From:

Re: [PEDA] need uMAX10 footprint

2001-07-12 Thread Dennis Saputelli
having been in such a situation before i would suggest just making your own based on the mech dwg with pad dimensions adjusted according to your experience. there are not a lot of pins on those uMax the slight (but important) differences in footprints are as much a matter of the particular assy