Jim,
There are more than 1000 Certified Designers worldwide.
Personally, I'm proud to be one of them. As far as I know,it is the only
international qualification, recognising the baseline skills and knowledge
required to be a board designer.
Phil.
Phil Dutton C.I.D.
Senior CAD Technician
IPC
Hi Brad
/\say this is the track i just placed (for the outline)
net name = outline
| /
|/(ooops, forgot the key part) add a small track named
fill inside the
area, then drag a polygon completely over it
- Original Message -
From: Dan G. [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, July 20, 2001 9:23 AM
Subject: [PEDA] more footprints
Greetings all,
When editing a library part, the component description only allows 4
footprints to be associated with that
Hi guys,
Can anyone explain why the autorouter is giving me this error message
please?
one or more connections cannot be routed due to design rule violations
this happens even if i try to just route a single component or net as well
as the whole board. i have done a done a complete drc (and
Yesterday there was a thread on file formats for PCB manufacturers. Here is
where you can find the gerber specification in .pdf format.
http://www.barco.be/ets/data/rs274xc.pdf
Regards,
Ted Tontis C.I.D.
Engage Networks
316 N. Milwaukee Street
Suite 214
Milwaukee WI, 53202
PH 414-273-7600 ext.
Well...I have been tempted to use a single schematic object (say a Schottky)
and associate it with a number of different footprints (DO-41, C-16,
DO-204AR, TO-220AC, D-PAK.. so on). Maybe that is what the original poster
was asking about??
Madhu
-Original Message-
From: [EMAIL
Thanks Richard,
now I got it. I had missed the effect of the two nets. Thanks for
re-explaining it, I must of been having one of those challenged moments.
That is tricky.
Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Steve,
It would be very easy to get more then 4 footprints if a person was using a
generic transistor symbol. Especially if they are numbering pins using the
EBC/DGS method. Using that method you could then come up with probably no
less then 40 to 50 orientations/footprints. (One reason that I
Hi Richard,
I would suggest that you check your setup on Design Rules for the
autorouter. It may be that the spacing you are telling the program to
maintain is so large that there are no paths for the router to take that
would not violate the spacing rule.
- Bill Brooks
Bill Brooks
PCB Design
On normal 2 layer PCBs, I've seen my boards stay flat fine through the SMT mounting
process, but after the wave pass, they would have an arch in them. When I changes the
design to a 4 layer board, it no longer happened. I think the material on the 4 layer
was of better refinement than the 2
It sounds like your wave soldering process is not set up correctly. The
boards should be evenly heated through before wave soldering, then cooled
uniformly.
What you describe happens when the board is heated mostly on the solder
wave side, causing softening of the resin and differential
yes I'm sure that was the problem on a few occasions
Dennis Saputelli
Harry Selfridge wrote:
It sounds like your wave soldering process is not set up correctly. The
boards should be evenly heated through before wave soldering, then cooled
uniformly.
What you describe happens when the
Try increasing the pre-heater temp or slow the conveyer speed. You need the
top side of the board at 200 degrees F before contacting the wave.
Bill Pullen
-Original Message-
From: Harry Selfridge [mailto:[EMAIL PROTECTED]]
Sent: Friday, July 20, 2001 12:54 PM
To: Protel EDA Forum
I checked the archive for a thread regarding this but its not
there. I want to take a power PCB v3.6 file and import it into protel. I was
told at one time this could be done?
How far back does the archive go? is there a more extensive one, or
am I looking at the wrong archive?
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