[PEDA] Antwort: tenting vias

2001-08-23 Thread ga
Hello Ivan. tent the vias. You will most probably risk short under the BGA if you don't. By the way, I never understood why many PCB designs come with open vias, unless you want to use them as testpoints. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To

Re: [PEDA] How to create a IPC-356 or Mentor-Neutral netlist with Protel 99SE?

2001-08-23 Thread Florian Finsterbusch
Thanks to all who have tried to help me with the IPC-356 netlist problem. In the first stepi will give the manufacturer of the PCB the netlist created with the Protel testpoint function. I will tell you if it is working or not. Florian Finsterbusch

[PEDA] Preview Setup

2001-08-23 Thread ga
Hi all, is it possible to make global changes to the properties of a layer set in Print/Preview? It is somewhat annoying to have to make changes to layer settings 25 times for one set of layer definitions. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

[PEDA] Info :Auto Router

2001-08-23 Thread Walter Muth

Re: [PEDA] Antwort: tenting vias;what Intel says

2001-08-23 Thread Wamnet
In a message dated 8/23/2001 4:03:21 AM Eastern Daylight Time, [EMAIL PROTECTED] writes: [EMAIL PROTECTED] Here's an excerpt from one of Intel's datasheet concerning the tenting of BGA vias: Intel recommends tenting the via’s on the bottom side of the board to minimize heat transfer to the

Re: [PEDA] Antwort: tenting vias;what Intel says

2001-08-23 Thread Andy Gulliver
A couple of years back we did some work for a Japanese customer who was insistent that vias shouldn't be tented. This was apparently to avoid reliability problems if process chemicals became trapped by the tenting. I've always tented vias, except for prototype boards with via holes large

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Terry Harris
On Thu, 23 Aug 2001 11:14:19 +0200, Florian Finsterbusch wrote: i have just seen your new layer-stackup for your 8-layer PCB. But i'm wondering about the numbers of prepregs. I think when you put 4 cores with copper on both sides together, you need only 3 prepregs. Not so simple. I believe

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Tim Hutcheson
Got it. Thanks. Does anybody have any ideas about how much the dielectric constant generally changes as a result of the pressing process and by how much a 5-mil trace shrinks on average? If I had a general idea about this I could make a better estimate of the target configuration needed for

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Tim Hutcheson
Thanks Florian. I visited Polar's site and notice that CITS25 Impedance calculator, now replaced by Si6000 controlled impedance design software. So I am having a look at Si6000 right now. I have implemented much of several good books on my TI-92 calc though and continue to refine that as I

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Brad Velander
Tim, the quoted dielectric constants for the materials should be stated for the completed product (laminated). Therefore it will be that figure specified for the material. There are some variances due to the variations in pressing, but that is the fabricators responsibility to properly

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Brad Velander
Tim, I will just warn you on the SI6000 software, it is not cheap. I forget what the exact price was, I was expecting $800 - $1000USD. I gagged when I found the actual price, thousands, many thousands. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Florian Finsterbusch
Hello Tim, you are right, the CITS25 is no longer on the Polar homepage. I have downloaded the Si6000A demo version some month ago. But there are too much restrictions (not all calculations are allowed). The CITS25 trial software is only restricted in time you use it and some not so important

[PEDA] Resource for design (inpedance calculator etc.)

2001-08-23 Thread Samuel Cox \Sam\
Tim, below are some very valuable resouces, http://www.robertsondne.com/ http://www.ultracad.com/articles.htm http://www.merix.com/resourcecntr/res_intro.html UltraCad as well as Chris Robertson's site have impedance Calculators. Merix has a great DFM manual.. Enjoy Sam Cox *

Re: [PEDA] one or the other

2001-08-23 Thread Colby - PowerStream
Unfortunately there is no way to tell the synchronizer to ignore a symbol(not that I know of) And although you don't want them on the schematic I think this is the only way to do it(aside from unchecking the Delete components box in the synchronizer) To get around the issue of having wire pads,

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Jon Elson
Terry Harris wrote: On Wed, 22 Aug 2001 16:24:37 -0500, Tim Hutcheson wrote: Since my source resistance is 53 ohms, I have less than 2% mismatch. Just to inject a little reality here. Board houses can not control layer thickness to anything like 2%. The can mic up the cores and maybe get

Re: [PEDA] tenting vias

2001-08-23 Thread Jon Elson
Waldemar Kulajew wrote: Mr. Baggett, some answers for your questions 3 and 4. My experience is either to tent the vias only half or tenting them with selkscreen (if this is the right word for the lacquer used to show the component-positions). 1) The first Idea means to

Re: [PEDA] tenting vias

2001-08-23 Thread Tim Hutcheson
What about the issue of whether to use a solder mask around the BGA ball land patterns? I though I read somewhere that there are pros and cons about this as it might cause ball breakdown during placement. If so, what would be the correct SM diameter to use with a 25-mil ball land? Tim

Re: [PEDA] Export / Import ERC Rule Matrix

2001-08-23 Thread Colin Weber
Steve, I looked at something similar a couple of weeks ago. What you can do is setup a process container on your schematic sheet somewhere, and (once off task) type in the values you need for your particular ERC configuration. Use this container to execute your ERC. This typed in setup can

Re: [PEDA] tenting vias

2001-08-23 Thread Colin Weber
Ivan, I just looked at this a short while ago. I am also using a 388 1.27mm PBGA, by AMD - ELANSC520. We are intending to tent the Vias as the folks on this group suggested. I have noticed your Via pad is smaller than we were asked to use by our fab house. We were asked to use 0.71mm pad and

[PEDA] Updating Sheet Symbols

2001-08-23 Thread Nicholas Cobb
Hi All, I was wondering if anyone can tell me how I can update sheet symbols to reflect changes in the names of ports of the subsheet. I know that I can delete the sheet symbol and create a new one, but it just seems like there should be a better way. Thanks, Nick Cobb * * * * * * * * *

Re: [PEDA] Updating Sheet Symbols

2001-08-23 Thread Brian Guralnick
I remember once awhile back, an automated sheet entry generator server was once mentioned in this news group. Perhaps somebody remembers what it was called. Brian Guralnick - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED]

Re: [PEDA] Updating Sheet Symbols

2001-08-23 Thread John Williams
Take a look at: http://www.aspiring-technology.com/prt_xrf.html John Williams Brian Guralnick wrote: I remember once awhile back, an automated sheet entry generator server was once mentioned in this news group. Perhaps somebody remembers what it was called. Brian

Re: [PEDA] Export / Import ERC Rule Matrix

2001-08-23 Thread Colin Weber
To clarify how to do this: 1. Set the Process name to Netlist:RunElectricalRulesCheck 2. Execute this container 3. Enter Parameters - Change 4. Edit the MatrixLines to suit your requirements Note: You may want to remove the FileName1= line For other users you want to provide this setup to, you

Re: [PEDA] Updating Sheet Symbols

2001-08-23 Thread Ian Wilson
On 05:19 PM 23/08/2001 -0700, John Williams said: Take a look at: http://www.aspiring-technology.com/prt_xrf.html John Williams Brian Guralnick wrote: I remember once awhile back, an automated sheet entry generator server was once mentioned in this news group. Perhaps somebody

Re: [PEDA] IBIS

2001-08-23 Thread Clive . Broome
See my post from 8 August re IBIS models. I have managed to use the IBIS converter on some of the devices designed here and can confirm that Protel does convert and load models correctly and seems to produce the sort of waveforms expected. The models I checked where from the IDT website and I