It appears that my polygons are in direct connect mode when my design rules
state that they are in relief mode. Is there something I'm missing?
Tim Fifield
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Hi all,
I completed the layout of a small PCB (99SE) designed for enclosure in a
moulded case, then realised I needed an additional hole for mechanical
locking. So I added a free pad, with no copper - just the correct hole size.
Everything looks good in PCB, but now, when I output the gerber
At 17:30 14.01.2004 -0500, you wrote:
At 02:06 AM 1/14/2004, Juha Pajunen wrote:
Pleace see this file:
http://groups.yahoo.com/group/protel-users/files/junk/PLANE_ERROR.jpg
You are seeing a composite display, not just the plane. You can tell
because, inside one of the thermal reliefs, there is a
Help!
It may just be my memory playing tricks (already pulled over 40 hours this
week), but I thought that the annular ring design rules used the same math
(i.e. the difference between the radii) for both pads and vias.
During rework of a project that should have been at the fabhouse last week,
At 06:14 PM 1/14/2004 -0600, you wrote:
Ray Mitchell wrote:
Hello,
In the past I've developed my Xilinx FPGAs by creating a schematic in
Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then
compiling the XNFs using the Xilinx 3.1i application. To be compatible
with the newer
Have you got x and y pad sizes same as the hole size? And untick the 'Plated' box.
Regards,
Igor
-Original Message-
From: Drew Mills [mailto:[EMAIL PROTECTED]
Sent: Thursday, 15 January 2004 2:54 PM
To: 'Protel EDA Forum'
Subject: [PEDA] Gerber output problems
Hi all,
I completed the
You don't say whether or not you added the hole after you first ran a set
of Gerbers. If you went back after generating a Gerber set, did you
remember to generate a new aperture file that includes the hole
definition? Try selecting the pinprick you mention and see what D code is
assigned,
Well my problem is solved, but I still cannot explain why. The pad was on
the top layer, instead of multilayer as I intended. Changing to multilayer
and re-generating the gerbers sorted it. I would have thought though that it
doesn't matter what layer the pad is on, so long as a hole size is
At 03:01 AM 1/15/2004, Edi Im Hof wrote:
[I had written:]
By the way, it appears you have vias thermally relieved. That is probably
not the best practice, it is better to set a design rule so that all vias
are direct-connect. Vias do not generally need thermal relief, and direct
connection has
At 01:11 PM 1/15/2004, Leo Potjewijd wrote:
Help!
It may just be my memory playing tricks (already pulled over 40 hours this
week), but I thought that the annular ring design rules used the same math
(i.e. the difference between the radii) for both pads and vias.
Some of the Protel documentation
At 09:12 PM 1/15/2004, Drew Mills wrote:
Well my problem is solved, but I still cannot explain why. The pad was on
the top layer, instead of multilayer as I intended. Changing to multilayer
and re-generating the gerbers sorted it. I would have thought though that it
doesn't matter what layer the
-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]
Sent: Friday, 16 January 2004 13:30
To: Protel EDA Forum
Subject: Re: [PEDA] Gerber output problems
The Protel programmers didn't anticipate that you'd have a
surface pad with
a hole, it seems. If you
What!?
How are single sided through hole boards supposed to be done then?
We just use Multilayer pads and uncheck plating when doing single sided
boards. Every manufacturer I've come across has no problem with this.
TC
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