Re: [PEDA] [PROTEL EDA USERS]: Rectangle holes

2001-05-07 Thread Jon Elson
Lloyd N. Johnson wrote: Message text written by Hamid It is a bad idea to use an inside radius same as your router bit radius. This requires the router to come to a complete stop and then start moving at 90 degrees. There will invariably be some chatter and the router will cut into the

Re: [PEDA] [PROTEL EDA USERS]: IMPORTING TANGO FILES

2001-05-07 Thread Jon Elson
iris mejma wrote: HI! DO YOU KNOW IF IT'S POSSIBLE TO IMPORT A SCHEMATIC FILE FROM TANGO TO PROTEL? The only way I know to do it is to write a program yourself or pay a database conversion company to do it. there is an outfit that specializes in this, but they have not done this

Re: [PEDA] [PROTEL EDA USERS]: Offtopic: Where can I get information

2001-05-07 Thread Jon Elson
Alfonso Manuel Cuesta Hernández wrote: Hi list. I've noticed a discussion about Power print in the forum. As well as working with Protel everyday, I'm also in charge of a sever in my school. I've been trying to find a Printer server that is reliable for me and I've not found one that is

Re: [PEDA] [PROTEL EDA USERS]: Give up,there is no point (Ex: Confused Newbie on Footprints)

2001-05-07 Thread Jon Elson
Ian Wilson wrote: On 10:10 AM 6/03/2001 +1100, John Haddy said: By definition, 1 inch = 25.4mm exactly. This was standardised some decades ago. Off topic a little... But the metre (and hence inch) are derived quantities (variables) so all our footprints are totally useless! Do you hear

Re: [PEDA] [PROTEL EDA USERS]: Deleteing the contents of the TEMPdrawer.

2001-05-07 Thread Jon Elson
Brian Guralnick wrote: Hi, I was cleaning up my system. The drawer Design Explorer 99 SE\System\Temp\ contained about 190 megabytes of data. Is it safe to delete? These are temporary backups made when files are saved back into the database. If the project is in good shape in the

Re: [PEDA] Windows 2000 Professional fatal exception errors

2001-05-07 Thread Jon Elson
Gordon Price wrote: Ladies Gents, I have a new Dell 1GHZ Pentium III with 128 megs of ram using 99SE SP6 using Windows 2000 Professional. When I am drawing schematics or manually placing components everything seems to run very stable. I have a medium sized project that has 5

Re: [PEDA] P99SE opening Tango PCB files

2001-05-07 Thread Jon Elson
Tony Karavidas wrote: I found my old Protel 2.8 floppies and installing it on a Window2000 system. #1: it runs (good to know) #2: it reads the old Tango ascii format I asked about earlier. Protel: Why did you break the importer!?? Please fix it! I don't what to have to drag around

Re: [PEDA] Mapping connected copper to the same net

2001-05-07 Thread Jon Elson
van de Werken, Matthew (DEM, PH) wrote: I'm pulling my hair out here - there must be a way of doing this, but I can't find it: I've inherited a board from someone else, with most of the tracks routed (I've had to modify it slightly), but all the tracks are missing netlist information. Is

Re: [PEDA] BOARD WILL NOT ROUTE

2001-05-07 Thread Jon Elson
Bryan Bernesi wrote: Hello everyone, Once again my board will not route. - I have a single schematic project. - I have run ERC, no errors - I made my PCB template using the board wizard - I have placed all components - I have run the DRC, no errors - All my layers are set up When I

Re: [PEDA] Reference

2001-05-07 Thread Jon Elson
Nicholas Cobb wrote: In a post about a month ago Mr. Lomax mentioned that leaving a CMOS input open could cause problems on a board. Are there any references that will help me learn the details that might cause problems like this in commercial devices? Up to this point I have been making

Re: [PEDA] [PROTEL EDA USERS]:PCB's with D2PAK

2001-05-07 Thread Jon Elson
Heart wrote: I don't know if this is an old message, but I don't remember seeing it a month ago, so here goes : Actually, what I was hoping to do was use 4 oz. copper on one side and 2 oz. copper on the other. I suppose a circuit board fabricator can do this, but it will incur extra

Re: [PEDA] need a work around for the 100 sq in restriction

2001-05-07 Thread Jon Elson
Hi Everyone I've been assigned to design a simple flex circuit. The problem is it will be 110 X 3.75 inches long. Is there a way to work around the 100 X 100 inch maximum work area? Any suggestions would be greatly appreciated. How about making the board at 45 degrees, then it will fit

Re: [PEDA] OT: Unused CMOS inputs (was: Reference)

2001-05-07 Thread Jon Elson
Dwight Harm wrote: Is there a reason to prefer Vdd over GND? The spec sheets often just say tied high or low..., and my knowledge of theory is too weak to even guess at an answer. :) Sometimes it doesn't matter, as in a completely unused gate. Sometimes it does matter, such as a

Re: [PEDA] schematic on my PCB ??

2001-05-07 Thread Jon Elson
Robison Michael R CNIN wrote: hello, i changed some things around on a multipage schematic for a previously built board, and now for some reason or other after i updated the pcb, i have red crosshatched squares on my pcb file that correspond to the pages of the schematic. i've tried

Re: [PEDA] any multi-layer prototype PCB house with great price?

2001-05-07 Thread Jon Elson
Mike Ingle wrote: http://www.advancedcircuits.com/ They have an online estimator so you decide if the price is great. They had a $200 special for first time users. Their prototype prices are now good. I stopped using them for a while because their prices got a bit high, they seem to have

Re: [PEDA] Negative Text and/or Components

2001-05-07 Thread Jon Elson
Thomas Sprunger wrote: I am trying to find a way to place text and components on ground planes (or polygon fills) and to make them an absence of copper (or Anti Copper in Orcad). Is this possible in the PCB portion of Protel? I think you can ONLY place anti-copper objects on the plane. It

Re: [PEDA] OT: Unused CMOS inputs (was: Reference)

2001-05-07 Thread Jon Elson
Mike Reagan wrote: Is there a reason to prefer Vdd over GND? The spec sheets often just say tied high or low..., and my knowledge of theory is too weak to even guess at an answer. :) TIA, Dwight Harm. Dwight, Here is my guess, the input of a cmos circuit (inside of the IC)

Re: [PEDA] EDIF/PLD software

2001-05-07 Thread Jon Elson
Nicholas Piccinich wrote: Jon Ron, The Xilinx representative said it was not possible to import an EDIF netlist unless I used device specific architecture of the target device, which I did not do. I imported a Xilinx 3000 library. which seems to be structurally the same as the Spartan

Re: [PEDA] SV: HP Laser Printer Issue - Extra pages printed

2001-05-07 Thread Jon Elson
Peder K. Hellegaard wrote: I encountered the same problem with my QMS 6100 color laserprinter which is a postscript printer also. However, this was not related using the Protel software but other programs as well. My solution was: Somewhere in the printerdriver you can chose if you want a

Re: [PEDA] Off topic / Need formula to calculate F in Mhz Wave length.

2001-07-11 Thread Jon Elson
Brian Guralnick wrote: Hi all, Little off topic, I figured I might get a quick response here. I need the formula to determine the Wave Length in Meters with regard to a specified frequency in MHz. Is that the wave length in free space, or on a PC board? In free space, it is L = C /

Re: [PEDA] perimeter stitched ground vias question

2001-07-11 Thread Jon Elson
Abd ul-Rahman Lomax wrote: At 10:09 AM 7/11/01 -0500, Mark E Witherite wrote: At the 1999 PCB east conference I learned about the 20H rule. This rule simply put states that EMI can be substantially reduced by keeping the power planes back from the edge of the ground planes by 20 time the

Re: [PEDA] perimeter stitched ground vias question

2001-07-12 Thread Jon Elson
Brad Velander wrote: I did recently see an article on this exact question. It was thoroughly tested using field solvers and the field solvers confirmed the reduction of radiation from traces designed to the 20H rule. Sorry can't look for the article right now and have no recollection of

Re: [PEDA] need uMAX10 footprint

2001-07-13 Thread Jon Elson
Bagotronix Tech Support wrote: one last thought on this it may not matter what footprint you use because when you really get rolling and really need the chips they won't be available it is Maxim you know :) Yeah, they stink when it comes to parts availability. Their parts are

Re: [PEDA] opening Orcad DSN into Protel 99SE

2001-07-27 Thread Jon Elson
Hello, all: I am trying to open an Orcad DSN file into Protel 99SE with no success. The message I get is: Error reading Orcad Cache! Try to Cleanup Cache first! Any idea what that means and how to work around it? Or is this another Protel advertised feature that doesn't really work?

Re: [PEDA] Surface Mount Boards

2001-08-01 Thread Jon Elson
[EMAIL PROTECTED] wrote: Dear All, When I edit foopprints' names in schematic in spreadsheet view all names like 0805, 0603 and etc. are loosing first 0. So synchronizer can find footprint 805. Can somebody help me to stop changing the cell by spreadsheet editor? I don't use the Protel

Re: [PEDA] 5/5 Manufacturing Issues

2001-08-06 Thread Jon Elson
[EMAIL PROTECTED] wrote: I'm skeptical. Even with source terminations, you've got a nasty mismatch at the destination, Right. The reflection bounces off the far end, back toward the source, and is absorbed as completely as possible by the source impedance. If you need incident wave

Re: [PEDA] 5/5 Manufacturing Issues

2001-08-06 Thread Jon Elson
Mike Reagan wrote: Tim, I have to respond to your concerns and about controlled impedance. First of all if the resistors you are claiming to eliminate are located at the source as is a commmon practice, These resistors are not in the circuit for impedance purposes. I will stay away

Re: [PEDA] 5/5 Manufacturing Issues

2001-08-06 Thread Jon Elson
Tim Hutcheson wrote: Actually I was thinking the authors meant that the driver absorbs about 5/6 of the signal at frequency, while the resistor absorbs the remaining 1/10, at any frequency. Is that incorrect? That is correct. Keep in mind that only a resistor can absorb. A PCB trace

Re: [PEDA] 5/5 Manufacturing Issues

2001-08-06 Thread Jon Elson
Tim Hutcheson wrote: Cool. Traces are short, less than 2.5 max, getting shorter as I eliminate resistors. :-) Rise time is large, nominally it is 2 nsec. This should work. 2 nS Tr is pretty generous. The wavefront with a 2 nS Tr is about 15 long, so you won't even see the incident wave

Re: [PEDA] 5/5 Manufacturing Issues

2001-08-06 Thread Jon Elson
Tim Hutcheson wrote: equations than one with two ground planes, termed stripline. In his case, the two ground planes lower the effective impedance for a given trace width. I never said I was using stripline stackup. I said in the beginning it was a conventional 4-layer board and

Re: [PEDA] save copy as is worthless

2001-08-07 Thread Jon Elson
Jeff Adolphs wrote: Hello! Does Protel99SE crash about daily for you? It does for me, I'm using the Database format and running on a Compaq IPAQ ( crap compared to the Dell I had before) with Windows 2000. I'm running it under Windows 95 (not recommended by Protel, but it works). I do

Re: [PEDA] Public open-source PCB software. was- Changes to the Protel company name

2001-08-07 Thread Jon Elson
Brian Guralnick wrote: This made me think of an interesting question. Is there a public domain open source PCB schematic capture software? This way, users have the ability to make significant changes themselves publicly post them. Yes, there are several projects going. One is at

Re: [PEDA] Logo's for FCC, UL and CE ?

2001-08-08 Thread Jon Elson
Brad Velander wrote: Relax Jon, the CE requirements do not cover use of normal components in an assembly. It covers the product/assembly but the individual components are not covered separately as far as it effects you or I. The best example of this is computer power supplies, it

Re: [PEDA] Naughty bits (from Benny Hill)

2001-08-13 Thread Jon Elson
Evan Scarborough wrote: I get these naughty bits too using the same process and I see them in many Protel generated gerber files from other designers. It seems to me that the auto-router leaves extra line segments after cleanup (and it seems to be worse if the routing grid and the

Re: [PEDA] DRC warns: Primitives found on Internal Planes

2001-08-13 Thread Jon Elson
[EMAIL PROTECTED] wrote: Hello all, I dont know what I have done to get this warning, but it keeps me bothering. I never had the intention to place any prims on the internal plane. Does anyone know how this can happen, or better how to find this prim. to delete it. Make sure the

Re: [PEDA] ddb transfer failure ??

2001-08-13 Thread Jon Elson
Robison Michael R CNIN wrote: hi everybody, well, i'm not having a banner day here. somebody else here needs to look at a pcb of mine in protel. since i'm using ddb's (it was either ddb's or not be able to read the footprints libraries) of course, there is no actual powsup.pcb. so i

Re: [PEDA] ddb transfer failure ??

2001-08-13 Thread Jon Elson
Robison Michael R CNIN wrote: it isn't broke on my system... ivan just can't open it on his machine. like i said, since i can't send him an actual powsup.pcb, i sent him the whole darned ddb. maybe thats not the way to move a job from one pc to another, but thats the method i tried,

Re: [PEDA] ddb transfer failure ??

2001-08-14 Thread Jon Elson
Robison Michael R CNIN wrote: hi chris, ivan is a mechanical engineer who is gonna do a heat sink for the board. i built this pcb from crude old hardcopy drawings and an stripped board. he was wanting to open it in protel so that he could mouseover the layout and get dimensions. For

Re: [PEDA] ddb transfer failure ??

2001-08-14 Thread Jon Elson
Robison Michael R CNIN wrote: thanks brad, i sent it over the intranet and i believe they've got that running at 100MB, so no, i didn't zip the file. Zip not only compresses files, it also makes sure that the file is undamaged when it uncompresses it. Some systems will alter binary files

Re: [PEDA] Protel 99 cannot auto-route BGA components

2001-08-14 Thread Jon Elson
From: [EMAIL PROTECTED] Sent: Monday, August 13, 2001 4:58 PM To: proteledaforum Subject: [PEDA] Protel 99 cannot auto-route BGA components I have been unable to autoroute a 10 layer design which has 2 fine grid BGA packages. Protel support has not been able to

Re: [PEDA] ddb transfer failure ??

2001-08-14 Thread Jon Elson
Robison Michael R CNIN wrote: thanks colby, i just called ivan and asked if he had tried the zipped ddb that i sent him. the file was also not opened in protel when i zipped it. protel wasn't even open. ivan's gonna give it a shot immediately. but one thing you mentioned definitely

Re: [PEDA] ddb transfer failure ??

2001-08-14 Thread Jon Elson
Brad Velander wrote: Specifically that FAQ should also mention that the Protel ddb Access database doesn't get along well with standard email, possibly due to mime encoding. I think the problem is that it DIDN'T get MIME-encoded, as MIME doesn't have a known file type for a DDB or PCB,

Re: [PEDA] unselectable polygon

2001-08-14 Thread Jon Elson
Brad Marshall wrote: Hello, I have an old board that I recently reopened to modify. When I opened it up there is a polygon plane on the Mid Layer 1. When I try to delete it nothing happens, when I try toselect it nothing, try show/hide from tools/preferences it does dissappear when I

Re: [PEDA] duping parts in a multi-part component ??

2001-08-15 Thread Jon Elson
Robison Michael R CNIN wrote: hello, i've set up a 6-part component in my component library and i built up the first part and now i want to copy this first part into the second part and then edit the pin numbers and remove the vcc and gnd, but i can't figure out how to copy the first

Re: [PEDA] Antwort: duping parts in a multi-part component ??

2001-08-15 Thread Jon Elson
Robison Michael R CNIN wrote: hi gisbert, it works fine now. i would swear that i was doing exactly that earlier, and more than once. geez. i tried several variations trying to find what i was doing wrong but now i can't get it to do anything but what i want it to do. didn't even

Re: [PEDA] Customize layer pairs

2001-08-21 Thread Jon Elson
Brad Velander wrote: Dave, Yu-Ming Luo, just to join the consensus here. I do exactly the same procedure that Dave has explained. It would be a great boost to Protel if they would implement a paired mechanical layers scheme. As boards get more dense and 2 sided assemblies the

Re: [PEDA] Customize layer pairs

2001-08-21 Thread Jon Elson
Brad Velander wrote: Am I missing something guys? With P99SE you can have keepouts on any layer that you want, right? I thought this was the current situation, am I wrong? Possibly you hadn't noticed? In P99SE, draw a line on any layer any shape, edit the properties, click on the

Re: [PEDA] one or the other

2001-08-22 Thread Jon Elson
Richard Thompson wrote: Hi Can anyone tell me how to place a component on to a schematic without being on a pcb and vica versa? (using syncronizer on Protel 99SESP6) ie. on a scematic I have symbols in the library for safety critical information etc by certain components. info only, no

Re: [PEDA] DRC issue

2001-08-22 Thread Jon Elson
Ken Pelic wrote: Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them

Re: [PEDA] Warping on small odd layer boards.

2001-08-22 Thread Jon Elson
Tim Hutcheson wrote: Has anyone any experience building small (4x7 inch) 7-layer .063 boards? I would like to have a certain stack up impedance that is best met with 4,9,9,9,9,4 for the 5-mil trace widths I am using but I know from what I have read that warping can be a problem. I

Re: [PEDA] Warping on small odd layer boards.

2001-08-22 Thread Jon Elson
Tim Hutcheson wrote: I'm learning, thanks. I have only just gotten to the point of trying to understand how the layers are put together. And it is real easy to miss the practical details. This is somewhat of a problem. Unless you read the trade journals of the PCB industry, or have done

Re: [PEDA] Warping on small odd layer boards.

2001-08-23 Thread Jon Elson
Terry Harris wrote: On Wed, 22 Aug 2001 16:24:37 -0500, Tim Hutcheson wrote: Since my source resistance is 53 ohms, I have less than 2% mismatch. Just to inject a little reality here. Board houses can not control layer thickness to anything like 2%. The can mic up the cores and maybe get

Re: [PEDA] tenting vias

2001-08-23 Thread Jon Elson
Waldemar Kulajew wrote: Mr. Baggett, some answers for your questions 3 and 4. My experience is either to tent the vias only half or tenting them with selkscreen (if this is the right word for the lacquer used to show the component-positions). 1) The first Idea means to

Re: [PEDA] Clearly Visible - On-Screen Error

2001-08-28 Thread Jon Elson
Andrew J Jenkins wrote: One thing that I didn't see in your post...Have you changed magnification levels, to see if it's not just an artifact? (one would suspect you have, but one must also be sure) Yes, I've seen this on at least one of our systems running Protel. When certain

Re: [PEDA] How to Kill Spam (was FYI: addresses @ ib-systems (was spam trawlers))

2001-08-28 Thread Jon Elson
I never bother dealing with the spam artists themselves. If they use various commercial services as their web hosts, mail hosts, SMTP servers, atc. I send email to their [EMAIL PROTECTED] address asking that they stop heling the spam artists to do their dirty work. I have gotten a number of

Re: [PEDA] Sv: Isolated Island on PCB

2001-09-04 Thread Jon Elson
Abd ul-Rahman Lomax wrote: At 02:04 PM 9/1/01 -0400, Mike Reagan wrote: I doubt if you will find a decent board house that is willing to fabricate poygon pours on internal layers.notice I said decent Talk to some manufacturing engineers to find out why this is frowned upon I

Re: [PEDA] None

2001-09-04 Thread Jon Elson
Evan Scarborough wrote: Greetings all, Is there a way to set up a design rule so that the defined keepout areas only affect the outer layers (other than ignoring or turning off online DRC)? I am routing an 8 layer pcb and the surfaces have rather complicated keepout areas for a metal

Re: [PEDA] 2 P99 quirks

2001-09-04 Thread Jon Elson
Evan Scarborough wrote: Greetings Jon, I have the missing dot syndrome also with the default font , but when I use the san serif font I get dots again. Ah, thanks. That is a useful workaround, as it might take Altium a while to get this fixed and in the next SP release. Another thing

Re: [PEDA] 2 P99 quirks

2001-09-05 Thread Jon Elson
Brad Velander wrote: Jon, your DXF problem is not so strange at all. Because of the complexities of differing DXF versions and different tools generating the DXFs, reading them into Protel can be real hit and miss. For example, I have one DXF that reads perfectly into P98. Reading

Re: [PEDA] the letter i in gerber, was 2 P99 quirks

2001-09-05 Thread Jon Elson
Abd ul-Rahman Lomax wrote: Indeed, with the default font, the dot on the i is missing in gerber. It also disappears in draft display mode. I looked directly at the gerber file; there is no attempt to draw the dot. It is not a case of a zero-length draw. I know this is correct, as my

Re: [PEDA] Diode pads

2001-09-05 Thread Jon Elson
[EMAIL PROTECTED] wrote: Hello all, I just had our test engineer come and complain that his test software chokes on the use of A and K for diode pad identifers. I have used A and K for 15 years and know many others that use the same convention. I assume it originated so there is no

Re: [PEDA] Diode pads

2001-09-05 Thread Jon Elson
Brad Velander wrote: Lloyd, I never use the A, K, or E, B, C, conventions myself. I stick to numbered pins. Many years ago (on another CAD package) I had seen some problems and issues with alpha designated pins and just ran away from them as fast as I could go. Today I set out a

Re: [PEDA] Altera 144Pin TQFP Landing Pattern

2001-09-06 Thread Jon Elson
Michael Schmitt wrote: No Problem, i can send it to you, we use this device so the footprint is very well tested :-) But, watch out for pin 1 orinetation. I just had to redo a board, because I forgot to check that. Some chips have pin 1 in the middle of a side, some at a corner. Some

Re: [PEDA] Removal From List

2001-09-06 Thread Jon Elson
Jim McGrath wrote: Hi All, Has Anyone else received this messege? Last time I got this messege it was not my problem. I do NOT want to be removed from this list! I received 20 messeges this morning and others since then. Techserv's Internet Service Provider apparently had a link outage

Re: [PEDA] Altera 144Pin TQFP Landing Pattern

2001-09-07 Thread Jon Elson
[EMAIL PROTECTED] wrote: All, Thanks for responding. It looks like I have several paths to explore. 1. I was able to get IPC's website footprint generation tool to spit out a footprint. 2. Brian Gurlanick's QFP generator. 3. Michael Scmitt provided a footprint he uses for the Altera

Re: [PEDA] Diode pads

2001-09-10 Thread Jon Elson
Abd ul-Rahman Lomax wrote: supporting numbering for TO-92 packages. On the other hand, being able to change from a TO-92 package to a different package, say a SOT-23, without changing the schematic symbol, would be an advantage to using letters. And some people really may do this, ie.

Re: [PEDA] Bug query?

2001-09-17 Thread Jon Elson
Richard Thompson wrote: Hi group Can anyone confirm if this is a bug or not please? in protel 99se pcb editor. if i click left mouse and drag over components to select them it only selects the surface mount components and not conventional through hole. This is on a simple single sided

Re: [PEDA] Antwort: True statement?

2001-10-05 Thread Jon Elson
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** [EMAIL PROTECTED] wrote: Hello, just another 2c: Try Mentor's

Re: [PEDA] Using equations rather than logic gates?

2001-10-22 Thread Jon Elson
Ian Wilson wrote: On 01:31 PM 20/10/2001 -0700, Ray Mitchell said: Is there a (reasonable) way to enter equations into the Protel 99SE schematic tool rather than placing logic symbols? Usually the logic symbols are fine but in some cases equations seem like a more straightforward approach.

Re: [PEDA] Altium Total Support (ATS)

2001-10-31 Thread Jon Elson
Ian Wilson wrote: On 12:11 AM 1/11/2001 +1100, Darren Moore said: All, You may what to have a look at the Protel site, they (Altium) have a new support plan... Darren I read this as the coming end of the free service packs. No, they say in this document

Re: [PEDA] ATS

2001-10-31 Thread Jon Elson
David Want wrote: Oh come on and stop whinging, USD2000 a year is a small price to pay to keep all those accountants, administration, and marketing people in a job. Not for a one-man shop! Protel was a BIG one-time investment for me, $2000 a year will be unlikely to be affordable. Jon * *

Re: [PEDA] Altium Total Support (ATS)

2001-10-31 Thread Jon Elson
Bagotronix Tech Support wrote: The last time I did my own taxes (about 2 years ago), you could take Section 179 expense deduction up to $19,000 in that tax year. This means you don't have to do the depreciation schedule for anything you can expense off. Of course, if you have more than

Re: [PEDA] PCB promo

2001-10-31 Thread Jon Elson
Tony Karavidas wrote: This is a little off topic, but you're the right crowd to ask. I received a promo postcard from some PCB vendor (I think they were in Colorado) offering 2 PCBs for $33 each. The claim was something like almost any size two layer FR4 board. Can anyone recall this???

Re: [PEDA] keepoutlayer and planes ??

2001-11-08 Thread Jon Elson
Robison Michael R CNIN wrote: hello, we're duplicating some legacy boards. in order to avoid flight testing i hand-routed the traces to match the old artwork. i believe that i just came close to making a SERIOUS mistake. i used the pcb wizard to generate the board but then hand-editted

Re: [PEDA] keepoutlayer and planes ??

2001-11-12 Thread Jon Elson
Abd ul-Rahman Lomax wrote: It should not have been much more expensive. In fact, as I recall, depending on the process, panel edges plate if you don't do something to prevent it! Yes, that is true. But, because of the way boards are made, the edge of the panel is cut away in the routing

Re: [PEDA] keepoutlayer and planes ??

2001-11-12 Thread Jon Elson
Brad Velander wrote: My 2 cents worth, since we do this regularily. The edge plating will make a significant difference in board emmisions with GHz frequency signals depending on the board material used. It gets worse the higher your frequencies go. The problem is that the board

Re: [PEDA] keepoutlayer and planes ??

2001-11-12 Thread Jon Elson
Brad Velander wrote: My 2 cents worth, since we do this regularily. The edge plating will make a significant difference in board emmisions with GHz frequency signals depending on the board material used. It gets worse the higher your frequencies go. The problem is that the board

Re: [PEDA] minor display refresh bug

2001-11-12 Thread Jon Elson
Abd ul-Rahman Lomax wrote: The multilayer layer causes all kinds of problems. For example, vias live on multilayer, intrinsically. But blind and buried vias are most certainly not on every copper layer. As as result of how Protel treats multilayer and vias, one cannot get a true, simple,

Re: [PEDA] Schematic Bug?

2001-11-13 Thread Jon Elson
[EMAIL PROTECTED] wrote: Hi all, I just recently changed over to SP6 running on Win2K professional. I tried to global edit a schematic part using the selection as the common feature. The customary screen saying I was about to change 16 parts OK? yet when I clicked yes, nothing changed. Has

Re: [PEDA] Schematic Bug?

2001-11-13 Thread Jon Elson
Dwight wrote: Jon, you're confusing PCB global edit with Schematic (what the thread is about). Probably so. It all sort of blends into one another when I don't have it on the screen in front of me at the moment. But, other than the free/all listbox, I think everthing ELSE I said was mostly

Re: [PEDA] Old v3.1 PCB Question

2001-11-13 Thread Jon Elson
Ian Wilson wrote: They did offer Adv Route3. I bought it. It was not worth the price. The router did a reasonable job on some boards and a shocker on others. It had very poor copper sharing, so it would run a stringer from virtually every SM to gnd and a separate pad even if they were

Re: [PEDA] Holes

2001-11-14 Thread Jon Elson
Wayne Trow wrote: Hi All We have mounting holes in our pcbs - amazingly enough :-) but when I left-click-hold to move a hole it disappears leaving only the crosshairs. WHY OH WHY OH WHY ? When you long-click to move ANYTHING, it disappears. Some objects have an outer boundary, and

Re: [PEDA] Multi-Part Components

2001-11-14 Thread Jon Elson
Abd ul-Rahman Lomax wrote: At 01:06 PM 11/13/01 -0800, Dennis Saputelli wrote: every time i tried that there was something it did that i didn't want to do too bad it's almost useful I had the opposite experience it has always worked for me. Hmmm. maybe reference designator positions

Re: [PEDA] None

2001-11-14 Thread Jon Elson
Wayne Bickers wrote: Hi all, I am in the process of taking a schematic to a PCB, using the update PCB function, I am getting an error as below Macro 1: New Node Add node FS1-2 to net NetFS1_2 Error: Node not found I usually get rid of this by playing around with the part schematic and

Re: [PEDA] dual-sided connector footprint ??

2001-11-16 Thread Jon Elson
Robison Michael R CNIN wrote: hello, i just finished a board that had an connector with little smt-type feet, some that contacted with the top, some that contacted with the bottom of the board. i played with getting a footprint with top and bottom pads, but it didn't seem to want to

Re: [PEDA] Copper Calculations

2001-11-16 Thread Jon Elson
Ted Tontis wrote: Minimum Conductor Widths For PCBs Temperature Rise Above Ambient For 1/2 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .013 1.5 AMP 45C (113F) .025 2 AMP 45C (113F) .033 3 AMP 45C (113F) .050 4 AMP 45C (113F) .073 5 AMP 45C (113F) .110 6 AMP

Re: [PEDA] Protel usage

2001-11-19 Thread Jon Elson
Dwight Harm wrote: Schematic, PCB, Powerprint, CAM Mgr, Autorouter, Camtastic (a bit). PLD I used a bit, but it was easier to switch to Xilinx's tools than to figure out how to get intermediate files from one to the other. (But it's a pain using Xilinx's schematic capture.) I put serious

Re: [PEDA] Antwort: Antwort: Autorouter

2001-11-19 Thread Jon Elson
[EMAIL PROTECTED] wrote: Steve, same here. Even medium designs won't route and end up with an unable to initialise. Does anyone know a reason and workaround for this effect? A couple well-known, but not well documented things. The most important is to have a keepout border around all the

Re: [PEDA] Protel usage

2001-11-19 Thread Jon Elson
[EMAIL PROTECTED] wrote: The following is my usage of Protel - Schematicyes - PCB yes - Powerprint yes - CAM Manageryes - Simulatorsometimes - still have great difficulty providing models for many components. -

Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)

2001-11-19 Thread Jon Elson
Jason Morgan wrote: Protel crashes, its protel's fault (even you admit that). Protel still crashes on a machine running Win 95, which is strongly NOT recommended. I also have it on a machine running Win 2000, and it is much more reliable. Can't clearly say this is Protel's fault! As for

Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)

2001-11-19 Thread Jon Elson
Jason Morgan wrote: The files in question were returned to Protel under NDA, they confirmed the problems as reported and indicated that at present there was no fix. Sorry, but I can't transmit designs to the public, at least without NDA, thanks for the offer anyway. I can say that there

Re: [PEDA] Protel usage

2001-11-19 Thread Jon Elson
Fred A Rupinski wrote: - Global EditingYESThis feature doesn't do what I expect. It is too involved and confusing for rapid, productive editing. In some cases it is necessary to revise a library component to edit a repeated schematic or sheet component. I use global edit, in

Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)

2001-11-19 Thread Jon Elson
Jason Morgan wrote: Nice idea, but I don't think errant dram bits hunt and seek just Protel, if the dram were faulty, I'd expect 2K (or any component of it) to dump at least some of the time, also the bist would be likely to fail... No, the self test detects functioning memory as different

Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)

2001-11-19 Thread Jon Elson
Chris Mackensen wrote: most of this memory stuff also has ECC (error correction code) of some sort that should be fault tolerant on the board/chip/asic level (not the software/application level)... I don't know much more about it, but if in the software, you assign a memory pointer

Re: [PEDA] Copper Calculations

2001-11-19 Thread Jon Elson
Rene Tschaggelar wrote: This unit 'ounces of copper', does it apply to 1)square foot ? 2)square yard ? 3)square meter ? It is ounces Avoirdupois per square foot, and is about .0014 thick, which should equal about 55 uM, if I did the conversion right. Jon * * * * * * * * * * * * * * * * *

Re: [PEDA] Protel usage

2001-11-20 Thread Jon Elson
Abd ul-Rahman Lomax wrote: At 03:35 PM 11/19/01 -0600, Jon Elson wrote: In PCB, you have much more flexibility, as you can change an individual pad, hole or whatever on a component. You can't MOVE a pad or hole with reference to the part, however. While I generally agree with most

Re: [PEDA] MS versus Linux wrt Protel

2001-11-21 Thread Jon Elson
Bagotronix Tech Support wrote: Oh boy, a chance to stir the Windows/Linux pot! But seriously: We use both Linux and Windows 9X, 2K. Linux is used so far only as the LAN server/gateway. All of the desktop work is done on Windows. Linux is a great server OS, but still needs a lot of GUI

Re: [PEDA] MS versus Linux

2001-11-21 Thread Jon Elson
Bagotronix Tech Support wrote: Has any of the *nix users here tried protel under VMware ?? as I have been I think you still need a copy of Windows to run Windows apps under VMware when you run VMware hosted on Linux. Yes, certainly. VMware just provides you with a virtual PC, with no

Re: [PEDA] How to use objects as keepouts?

2001-11-21 Thread Jon Elson
Jenkins, Charlie wrote: I noticed at some point that a keepout check box was added to the fill properties. I have long wanted to place a top or bottom only keepout in between certain surface mount pads such that copper pours were prevented from filling in between pads that had a layer

Re: [PEDA] Power Plane Clearance

2001-11-21 Thread Jon Elson
Tim Fifield wrote: I have a few square thru-hole pads on a PCB, but when I set up a design rule to create a rectangle clearance on the GND plane it still produces a circular clearance so the corners of the pad are still touching the GND plane. Filter Kind is Pad Specification. Hole, XY

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