-Sen explains how to use Perl to keep your secrets... secret.
[Perl.com]
--
D. Chris Mackensen, EIT
Electrical Engineer
Software Engineer
-Original Message-
From: Brian Guralnick [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, August 07, 2001 12:33 PM
To: Protel EDA Forum
Subject: Re: [PEDA
hmmm it's been years since I've played with programming under MS-Win~1
for multi-proc systems I think the OS will obviously take advantage of
the multi-proc (and the OS scheduler may schedule separate processes of apps
on different processors), but I think (if I recall) the applications
the 5 times hitting of the key may be related to the accessibility options
in the control panel stickey keys is one option in the accessibility
control panel widget
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, August 08, 2001 3:22 PM
To:
Using another signal layer is probably the best, if not a manual
administrative regime. Don't let that layer gerber accidentially slip to
the fab house
but if you are maxed out on signal layers (and routed to max density), here
is a very fragile alternative ( I do not know how well this
The problem may not be just limited to protel ascii 2.8 limitations.
There are a few homebrew options but some may seem more impractical than
others
1) get a clip file of the allegro board write a clip file parser that
handles the recursive LISP like structure of clip language..
Yes, please keep posted... I still occasionally work for a service bureau
that uses Allegro/Mentor/Valor/SpecctraQuest/CCT (even though I really am an
EE that writes software for a living rather than lay out boards for a
living)...
yes, some of these scripts can take some time to write...
The conversion back into allegro would be interesting on text file basis
I would write it into a clip file language format and then generate a script
(*.scr) file to put testpoints back in (if there are test points) But
other than that, since it has been a while since I have touched
I'm *wearing* my virtual shorts right now good thing this is radio and
not television
-chris
-Original Message-
From: Don Ingram [mailto:[EMAIL PROTECTED]]
Sent: Monday, September 03, 2001 3:41 AM
To: Protel EDA Forum
Subject: [PEDA] Virtual Shorts
Just got PCB Fab Magazine
can not is usually _spelt_ cannot
;-)
but to our friends from abroad, we get the idea...we love phonetics... try
speaking Japanese
it ain't easy... but the person usually can understand pigeon Nihongo with a
lot of trials and hai soo desu...
romaji: doomoarrigatoogoziamasu,
-chris
P.S.
Howdy,
You could just *not* submit the gerbers for the solder mask layers
You can also play with what layers you wish to or wish not to CAM..
Yes, turning off the viewing of the solder mask layers does just exactly
that we have boards that are both solder masked and conformal coated
thanks to all who responded. i've absorbed some of it and i'm still
chewing on the rest.
that's what we're here fer. ;-)
there was also talk about just deleting the mask where the heat sink
goes, and a polygon pour or fill was suggested here. i have never
done this before.
in the
Hi,
I could be wrong, but it sounds like the actual elusive traces are on
another layer that is *not* visible. When you go to route or select a net,
traces on some of the non-visible layers will temporarily appear to
fix, turn on those layers and delete as appropriate..
do not
yah I talked to them last month last month was supposed to be the last
month of the deal, but they (were, at the time, thinking of) extended it
unfortunately, I'm stuck writting software for a dealine at work to finish
my artwork for my boards at home to take advantage of the deal for
most of this memory stuff also has ECC (error correction code) of some sort
that should be fault tolerant on the board/chip/asic level (not the
software/application level)... I don't know much more about it, but if in
the software, you assign a memory pointer incorrectly and then try to use
it,
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