At 09:29 PM 3/30/2003 -0800, you wrote:
Hi all,
I would like to do complex buses in Protel99SE. For example, I would like
to combine memory signals such as, nCS, nRAS, nCAS, nWE, into one bus
signal and then send this complex bus to a port for hierarchical style
design. It does not pass the ERC. Is this possible at all?
Hey Loc,
Unless this has been added in DXP (anyone know?) Protel has the
limitation that all signals on a combined bus (thru a port) need to be
numerically sequential, or at least the same save for the numeric
component. (i.e. AD0, AD1, AD2, etc etc) It's an often annoying feature,
but was probably done in the interest of reducing design errors.
I used to do busses this way, until I began spreading my designs
out to multiple pages and simply applying ports directly to the devices the
bus connected to, labeling them after the 'master' device on any multi-drop
busses, things like CPU.D0, CPU.D1, CPU.WR, CPU.A0, CPU.A1 etc etc and I
don't think I'd ever go back to the older style - the new schematics are
considerably less cluttered, easier to read (since you don't have to follow
traces with your finger!) take a LOT less time and effort to produce, and
are a lot easier to debug and modify when you're flipping between board
layouts and schematics to optimize things. They're also handy because
connecting multiple sheets together is a breeze - just throw them all on
the same page as sheet symbols, and all of your inter-connections are
immediately taken care of. :D
Hope this helps!
-- Matt
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