Thank you Ian for your detailed hints. I could solve the problem. see below:
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Monday, August 13, 2001 1:59 PM
To: Protel EDA Forum
Subject: Re: [PEDA] DRC warns: Primitives found on Internal Planes
On 12:25 PM 13/08/2001 +0200, [EMAIL PROTECTED] said:
Hello all,
I dont know what I have done to get this warning, but it keeps me
bothering.
I never had the intention to place any prims on the internal plane. Does
anyone know how this can happen, or better how to find this prim. to delete
it.
A few things could be happening here:
1) the simplest - there is some text or line or fill or something that has
been placed/moved the internal plane. In this case you can get rid of it
(assuming you want to) by turning the internal layer on, change to the
internal plane and then use S-Y (Select all on laYer). This should
highlight any free entities on the layer.
HH: It was a short piece of track, and it was not high ligthed, but
selected. It layed 'unter' a pad. After I deleted it the pad got a hole,
were the track was before, as long as the screen was not updated. Very
strange!
Before you delete anything make
sure that you have not got extra bits selected (use X-A before the
S-Y).
HH: Very good hint. I did this multible on my green days, causing some pain.
One way of identifying what is causing the problem if it is not
clear from the selection is to copy and past the selection into a new blank
PCB and then zoom all should show what the primitive is, at least, and this
may help you track it down. You can also use M-S (Move-Selection) to try
to gauge how big the object is by seeing how big the move selection
rectangle is. If the object is smaller than the selection box then you
should find that the cursor is hugging the opposite corner of the move
selection box. This can help narrow the search.
HH: I agree, but it was not neccessary.
It is common to have tracks around the outside of the PCB on the internal
layers to pull back the plane from the edge of the board. So all my
release boards that have internal planes will get this warning. In fact I
know I have forgotten something if I do not get it.
Layer clocks or stack-up indicators will usually have fills and text on the
internal layers. These will cause the warning to appear.
*But* since it is also possible that the entities that are on the internal
layer are not free entities and so 1) will not work...most of what remains
assumes that the offending primitive is small and so easily missed. If the
offending primitive(s) are large then they will show up by simply turning
on all the internal plane layers.
2) Painful and care required - make all the other layer colours dim or turn
them off but each internal layer a bright bold colour. Then scan carefully
looking for something standing out. This is not always reliable when the
offending primitive is small. (I have never had a case where I was tracking
down a small primitive on an internal plane - this is a technique I use in
other situations.)
3) Produce gerbers for the board and check to see if anything strange
appears - other than automatic blowouts and reliefs.
4) Do the same with a printout.
5) Check library components for embedded primitives on the internal layer.
6) Save the PCB file as an ASCII file and then open it in a text editor and
search for anything on the any internal layers. It may help to
deliberately add a known track on one or more internal layers so you can
determine the format of the layer specification and you know if your search
is working correctly. This method should be pretty reliable in finding the
objects. Interpreting the information so you can determine what component,
or union or polygon or whatever is a little more complex but with some
thought and a bit of study of the ASCII format it can be done. If things
are getting tough this is my big hammer.
There are probably other things as well. Have you got any more info.
Ian Wilson
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