Re: [PEDA] FW: Access violation -- Is it a Protel bug?
I have tried to reproduce this behaviour by creating a schematic symbol which is associated with footprint BLANK. No ERC errors in the schematic. Generating a PCB using PCB WIZARD and using UPDATE PCB does not cause a problem. The updated PCB displays two of 6 components (not including the BLANK) the rest are not visible. FIT BOARD and FIT DOCUMENT causes a zoom to maximum size (10mil). With designators and comments hidden the two visible components can be selected and moved. With either designators or comments unhidden attempting to move either of the visible components causes a selection choice of the visible component and BLANK. Selecting in free space selects BLANK. Hiding Designators and comments, then using MOVE COMPONENT and SELECT COMPONENT with move component to cursor selected all components except BLANK were moved to within the PCB outline. FIT BOARD and FIT DOCUMENT now behave as normal. Looks like a BLANK creates a very large invisible footprint. Hope someone finds this useful. I can send the .ddb to anyone if interested. Thanks, Dave Buckley -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: 18 April 2002 00:03 To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? On 02:40 PM 17/04/2002 -0700, Shuping Lew said: I use some notes on every schematic project. So I created a schematic symbol named note for it. To avoid the warning of missing footprint, I also created a footprint named blank to associate with that symbol. For some reason, Protel does not like the footprint Blank(there is not primitive on the footprint at all). I deleted component note from the netlist, it seems ok now... Shuping Interesting - can this be validated (if someone validates I will add to the bug list). Proposed entry (if validated): Summary: PCB:Netlist load specifying a footprint with no primitives causes access violation. Details: PCB 99SE SP6 A netlist load which includes a footprint with no entities (a completely blank PCB footprint) can cause an access violation during netlist load. This does not affect the synchroniser. Workaround: Completely blank footprints should be avoided. Protel should make netlist import bullet-proof such that any file, even complete binary garbage, should not cause a crash. Reported by: Shuping Lew Validated by: I would especially like validation that this indeed the only way of triggering the issue or whether it requires other conditions as well such as large number of components, multiple instances of the blank component (maybe all with the same or possibly blank ref designators). Also, checking what the effects of the blank footprint on the board is (is it reported in BOM, does it affect Zoom-ALL). Maybe there is another bug in that a blank footprint causes the database to become unstable in some fashion. As per usual, I will do the database if others put in some time on the validation, thanks. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Thanks Dave, One more thing, can you try creating a netlist and then try loading that into a PCB using the Netlist Manager | Netlist Load command (as opposed to using the Update PCB synchroniser). Does it crash? This would then confirm Shuping's bug and the proposed bug database entry. Probably, be a good idea not to have too many other important files open when you do this :-) Sounds like there are lots of reasons to avoid using footprints that are blank (that is have no entities). Ian Wilson On 03:33 AM 18/04/2002 -0700, Buckley.Dave said: I have tried to reproduce this behaviour by creating a schematic symbol which is associated with footprint BLANK. No ERC errors in the schematic. Generating a PCB using PCB WIZARD and using UPDATE PCB does not cause a problem. The updated PCB displays two of 6 components (not including the BLANK) the rest are not visible. FIT BOARD and FIT DOCUMENT causes a zoom to maximum size (10mil). With designators and comments hidden the two visible components can be selected and moved. With either designators or comments unhidden attempting to move either of the visible components causes a selection choice of the visible component and BLANK. Selecting in free space selects BLANK. Hiding Designators and comments, then using MOVE COMPONENT and SELECT COMPONENT with move component to cursor selected all components except BLANK were moved to within the PCB outline. FIT BOARD and FIT DOCUMENT now behave as normal. Looks like a BLANK creates a very large invisible footprint. Hope someone finds this useful. I can send the .ddb to anyone if interested. Thanks, Dave Buckley * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Ian, Creating netlist and Load Nets produces the same behaviour with no crashes. Perhaps having a small number of components makes the difference or maybe it's the size of the BLANK footprint. The system I run on is WIN NT4 P99SE sp6. Dave Buckley -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: 18 April 2002 13:01 To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? Thanks Dave, One more thing, can you try creating a netlist and then try loading that into a PCB using the Netlist Manager | Netlist Load command (as opposed to using the Update PCB synchroniser). Does it crash? This would then confirm Shuping's bug and the proposed bug database entry. Probably, be a good idea not to have too many other important files open when you do this :-) Sounds like there are lots of reasons to avoid using footprints that are blank (that is have no entities). Ian Wilson On 03:33 AM 18/04/2002 -0700, Buckley.Dave said: I have tried to reproduce this behaviour by creating a schematic symbol which is associated with footprint BLANK. No ERC errors in the schematic. Generating a PCB using PCB WIZARD and using UPDATE PCB does not cause a problem. The updated PCB displays two of 6 components (not including the BLANK) the rest are not visible. FIT BOARD and FIT DOCUMENT causes a zoom to maximum size (10mil). With designators and comments hidden the two visible components can be selected and moved. With either designators or comments unhidden attempting to move either of the visible components causes a selection choice of the visible component and BLANK. Selecting in free space selects BLANK. Hiding Designators and comments, then using MOVE COMPONENT and SELECT COMPONENT with move component to cursor selected all components except BLANK were moved to within the PCB outline. FIT BOARD and FIT DOCUMENT now behave as normal. Looks like a BLANK creates a very large invisible footprint. Hope someone finds this useful. I can send the .ddb to anyone if interested. Thanks, Dave Buckley * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
At 03:23 PM 4/16/2002 -0700, Shuping Lew wrote: I tried to load a netlist file to PCB. It has over 1,100 components. I receiced a warning of access violation. It says: Access Violation at address OF086CC6 module Exception Occurred in PCB: Netlist... First of all, yes, I would strongly suspect a bug, though a damaged executable is a possible but unlikely culprit. Mr. Wilson is correct, it should not be possible to cause an access violation with bad (or good) netlist data. One factor not stated so far: did the Schematic pass a full ERC? Many designers, trying ERC, find so many errors and warnings that they do not bother to clean it up. After all, the job is due, etc. But that quickly-done job is going to be a problem if the PCB contains errors that could have been avoided if errors or warnings in the ERC had been found and fixed. Most experienced Protel designers take the trouble to track down and fix *every* error and warning. If a warning is verified to come from a condition that is intended, a no_ERC directive (Place Directive) is placed on the error marker to suppress the report. For example, I'll put such a directive on every unconnected pin, because I want to check for unconnected pins, for a very high percentage of schematic errors will result in an unconnected pin, or a net with no driving pin. As others have mentioned, a possible cause of the crash is a duplicated pin, i.e., a pin which is in more than one net, or possibly a net which is found in the list more than once. The former condition can be created by a bad symbol or by more than one part with the same reference designator. The latter will generally be detected by ERC. A sign of the former would be that an Update PCB will produce macros even after Update has been run twice. I would not trust that a netlist which crashes Netlist Load will produce good results when loaded through the Synchronizer (Update PCB), even if the latter does not crash. I would not be content until I had tracked down the exact cause of the problem, which can be done by cutting down the net list into sections, repeating the process until one has found exactly what causes the problem. (Note that a problem might exist because of two different nets or node in the list, widely separated in the file, so the chunking might need to be done in a more complicated way than merely cutting the file in half each time). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Dear ABD, First of all, yes, I would strongly suspect a bug, though a damaged executable is a possible but unlikely culprit. Mr. Wilson is correct, it should not be possible to cause an access violation with bad (or good) netlist data. One factor not stated so far: did the Schematic pass a full ERC? The schematic passed the ERC, no warning. Netlist loading report is very clear and all macros are validated. Many designers, trying ERC, find so many errors and warnings that they do not bother to clean it up. After all, the job is due, etc. But that quickly-done job is going to be a problem if the PCB contains errors that could have been avoided if errors or warnings in the ERC had been found and fixed. Most experienced Protel designers take the trouble to track down and fix *every* error and warning. If a warning is verified to come from a condition that is intended, a no_ERC directive (Place Directive) is placed on the error marker to suppress the report. For example, I'll put such a directive on every unconnected pin, because I want to check for unconnected pins, for a very high percentage of schematic errors will result in an unconnected pin, or a net with no driving pin. As others have mentioned, a possible cause of the crash is a duplicated pin, i.e., a pin which is in more than one net, or possibly a net which is found in the list more than once. The former condition can be created by a bad symbol or by more than one part with the same reference designator. The latter will generally be detected by ERC. A sign of the former would be that an Update PCB will produce macros even after Update has been run twice. I would not trust that a netlist which crashes Netlist Load will produce good results when loaded through the Synchronizer (Update PCB), even if the latter does not crash. I would not be content until I had tracked down the exact cause of the problem, which can be done by cutting down the net list into sections, repeating the process until one has found exactly what causes the problem. (Note that a problem might exist because of two different nets or node in the list, widely separated in the file, so the chunking might need to be done in a more complicated way than merely cutting the file in half each time). ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote: ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. If the problem was, for example, that you had an incorrect scope such that some net names were duplicated between sheets even though you did not intend to connect them, or there were duplicate designators, with one on one sheet and another on another sheet, each sheet would still load correctly, but the combination would fail in some way. A common error is the use of flat hierarchy with named nets on each sheet, but the sheet numbers are not added to the net names. This will cause duplicate net names, quite a mess. What Mr. Velander wrote should also be noticed. I'd be interested to see that net list. Mr. Lew, if he is concerned about proprietary data, could make a copy of his .ddb, edit the schematic to remove all type data, generate a net list -- which should still crash Protel, that should be verified -- and send it to me or to anyone else interested. Don't send it to the list! (A net list without data regarding the types of parts contains zero IP. I would not reveal the data to anyone else anyway, even if it did contain type data.) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Regardless of ERCs or not, a netlist generated by Protel SHOULD NOT crash Protel. Period! I'd say if this 'crash' occurs on more than one machine, then it probably is a bug. If it only happens on his machine, it might be something goofy with his setup (bad bits on the hard disk, EXE tweek, etc) It should go to Protel for eval. Tony -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 12:25 PM To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote: ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. If the problem was, for example, that you had an incorrect scope such that some net names were duplicated between sheets even though you did not intend to connect them, or there were duplicate designators, with one on one sheet and another on another sheet, each sheet would still load correctly, but the combination would fail in some way. A common error is the use of flat hierarchy with named nets on each sheet, but the sheet numbers are not added to the net names. This will cause duplicate net names, quite a mess. What Mr. Velander wrote should also be noticed. I'd be interested to see that net list. Mr. Lew, if he is concerned about proprietary data, could make a copy of his .ddb, edit the schematic to remove all type data, generate a net list -- which should still crash Protel, that should be verified -- and send it to me or to anyone else interested. Don't send it to the list! (A net list without data regarding the types of parts contains zero IP. I would not reveal the data to anyone else anyway, even if it did contain type data.) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Thanks for all of your help. I found the problem. One hardware component was causing the trouble. I deleted it and now the program works normal. Shuping -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 12:25 PM To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote: ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. If the problem was, for example, that you had an incorrect scope such that some net names were duplicated between sheets even though you did not intend to connect them, or there were duplicate designators, with one on one sheet and another on another sheet, each sheet would still load correctly, but the combination would fail in some way. A common error is the use of flat hierarchy with named nets on each sheet, but the sheet numbers are not added to the net names. This will cause duplicate net names, quite a mess. What Mr. Velander wrote should also be noticed. I'd be interested to see that net list. Mr. Lew, if he is concerned about proprietary data, could make a copy of his .ddb, edit the schematic to remove all type data, generate a net list -- which should still crash Protel, that should be verified -- and send it to me or to anyone else interested. Don't send it to the list! (A net list without data regarding the types of parts contains zero IP. I would not reveal the data to anyone else anyway, even if it did contain type data.) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Was it your motherboard? ;) What hardware component did you delete Tony -Original Message- From: Shuping Lew [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 1:25 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? Thanks for all of your help. I found the problem. One hardware component was causing the trouble. I deleted it and now the program works normal. Shuping -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 12:25 PM To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote: ---I created netlist for each sheets. There are total 25 sheets. I then loaded them individaully. There were no problem. If the problem was, for example, that you had an incorrect scope such that some net names were duplicated between sheets even though you did not intend to connect them, or there were duplicate designators, with one on one sheet and another on another sheet, each sheet would still load correctly, but the combination would fail in some way. A common error is the use of flat hierarchy with named nets on each sheet, but the sheet numbers are not added to the net names. This will cause duplicate net names, quite a mess. What Mr. Velander wrote should also be noticed. I'd be interested to see that net list. Mr. Lew, if he is concerned about proprietary data, could make a copy of his .ddb, edit the schematic to remove all type data, generate a net list -- which should still crash Protel, that should be verified -- and send it to me or to anyone else interested. Don't send it to the list! (A net list without data regarding the types of parts contains zero IP. I would not reveal the data to anyone else anyway, even if it did contain type data.) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
On Wed, 17 Apr 2002 14:07:39 -0700, Tony Karavidas wrote: Was it your motherboard? ;) What hardware component did you delete Lew -- Yes, please elaborate. Telling us exactly what the problem was and how you fixed it might help some other list member in the future. It might also be seen by Altium personnel trolling the list... ;-) Matt Pobursky Maximum Performance Systems * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote: I use some notes on every schematic project. So I created a schematic symbol named note for it. To avoid the warning of missing footprint, I also created a footprint named blank to associate with that symbol. I think there is a better way. You can copy notes to the clipboard and then paste them repeatedly wherever you want. To set up these notes for repeated use, just create a schematic sheet from which you can copy them each time you create a project. You could also make the notes part of your drawing format, i.e., the template file. I'd guess that the problem was caused by whatever was in that blank footprint. If it had no primitives, that would very likely be an unanticipated data structure, it is not surprising that it would crash Protel. Yes, the data should have been tested before being crunched, but the reality is that programmers simply don't think of everything We should perhaps verify this bug, I don't have time, but it should not be difficult. Once it is a reported bug, if we can verify it, future versions will be tested, by us if not by Protel * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Thank you. ABD. I like the idea. Shuping -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 3:21 PM To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote: I use some notes on every schematic project. So I created a schematic symbol named note for it. To avoid the warning of missing footprint, I also created a footprint named blank to associate with that symbol. I think there is a better way. You can copy notes to the clipboard and then paste them repeatedly wherever you want. To set up these notes for repeated use, just create a schematic sheet from which you can copy them each time you create a project. You could also make the notes part of your drawing format, i.e., the template file. I'd guess that the problem was caused by whatever was in that blank footprint. If it had no primitives, that would very likely be an unanticipated data structure, it is not surprising that it would crash Protel. Yes, the data should have been tested before being crunched, but the reality is that programmers simply don't think of everything We should perhaps verify this bug, I don't have time, but it should not be difficult. Once it is a reported bug, if we can verify it, future versions will be tested, by us if not by Protel * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
On 02:40 PM 17/04/2002 -0700, Shuping Lew said: I use some notes on every schematic project. So I created a schematic symbol named note for it. To avoid the warning of missing footprint, I also created a footprint named blank to associate with that symbol. For some reason, Protel does not like the footprint Blank(there is not primitive on the footprint at all). I deleted component note from the netlist, it seems ok now... Shuping Interesting - can this be validated (if someone validates I will add to the bug list). Proposed entry (if validated): Summary: PCB:Netlist load specifying a footprint with no primitives causes access violation. Details: PCB 99SE SP6 A netlist load which includes a footprint with no entities (a completely blank PCB footprint) can cause an access violation during netlist load. This does not affect the synchroniser. Workaround: Completely blank footprints should be avoided. Protel should make netlist import bullet-proof such that any file, even complete binary garbage, should not cause a crash. Reported by: Shuping Lew Validated by: I would especially like validation that this indeed the only way of triggering the issue or whether it requires other conditions as well such as large number of components, multiple instances of the blank component (maybe all with the same or possibly blank ref designators). Also, checking what the effects of the blank footprint on the board is (is it reported in BOM, does it affect Zoom-ALL). Maybe there is another bug in that a blank footprint causes the database to become unstable in some fashion. As per usual, I will do the database if others put in some time on the validation, thanks. Ian Wilson -Original Message- From: Matt Pobursky [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 17, 2002 2:23 PM To: Protel EDA Forum Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug? On Wed, 17 Apr 2002 14:07:39 -0700, Tony Karavidas wrote: Was it your motherboard? ;) What hardware component did you delete Lew -- Yes, please elaborate. Telling us exactly what the problem was and how you fixed it might help some other list member in the future. It might also be seen by Altium personnel trolling the list... ;-) Matt Pobursky Maximum Performance Systems * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] FW: Access violation -- Is it a Protel bug?
Warning Unable to process data: multipart/mixed;boundary==_NextPart_000_0005_01C1E55A.A530A310
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Ian Wilson's questions are good ones. Did you enter the schematic and generate the Netlist? If you entered the schematic, and if it is an option, I would begin by resetting all Identifiers to ?. That is, do a global change of all R's to R?, all C's to C?, etc, for all components. Then use Tools/ Annotate to reannotate all ? components. Then generate a new Netlist and try loading that. Be sure to have all required PCB Libraries open for component footprints called for by the Netlist. Good luck! Brian At 04:14 PM 4/16/02 -0700, you wrote: Brian, I am using Protel 99SE sp6. The operation systems is Window 2000. I have over 500 mb of Ram. Tried to load a netlist to a new PCB document. There is no warning for the netlist report. I am not sure what I should do to solve the problem. Do you have any suggestion? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
