Free pads, by definition, do not appear on the schematic. I read
this post
from Mr. Beavis and was pretty shocked. I was about to start
railing at the
programmers who would allow Free-padname to be deleted as if it were a
component. But I tried it first. I could not get free pads to
Hi,
Can anyone tell me if it is possible make a via or pad that is connected to
the Vcc net on the top and bottom layers only. TI do not want to connect it
to the inner Vcc plane as the decoupling caps are on the secondary side of
the pcb and I want the voltage to see them before the leg of
/bbrooks/pca/pca.htm
-Original Message-
From: Wesley Webb [mailto:[EMAIL PROTECTED]]
Sent: Thursday, November 29, 2001 7:56 AM
To: Protel EDA Forum
Subject: [PEDA] Padstack
Hi,
Can anyone tell me if it is possible make a via or pad that is connected to
the Vcc net on the top and bottom
Can anyone tell me if it is possible make a via or pad that is connected
to
the Vcc net on the top and bottom layers only. TI do not want to connect
it
to the inner Vcc plane as the decoupling caps are on the secondary side
of
the pcb and I want the voltage to see them before the leg of the
At 10:55 AM 11/29/01 -0500, Wesley Webb wrote:
Can anyone tell me if it is possible make a via or pad that is connected
to the Vcc net on the top and bottom layers only. TI do not want to
connect it to the inner Vcc plane as the decoupling caps are on the
secondary side of the pcb and I want
At 08:40 AM 11/29/01 -0800, Brooks,Bill wrote:
Make a physical clearance in the inner plane where you put the via so it
will not connect...
If you are using power/gnd planes and not polygon fills then you need to
just put a fill or pad in the area on the negative layer where the via is,
and make
:[EMAIL PROTECTED]]
Sent: Thursday, November 29, 2001 9:30 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Padstack
Can anyone tell me if it is possible make a via or pad that is connected
to
the Vcc net on the top and bottom layers only. TI do not want to connect
it
to the inner Vcc plane
PROTECTED]]
Sent: Thursday, November 29, 2001 10:19 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Padstack
At 10:55 AM 11/29/01 -0500, Wesley Webb wrote:
Can anyone tell me if it is possible make a via or pad that is connected
to the Vcc net on the top and bottom layers only. TI do not want
Can anyone tell me if it is possible make a via or pad that is connected
to
the Vcc net on the top and bottom layers only. TI do not want to connect
it
to the inner Vcc plane as the decoupling caps are on the secondary side of
the pcb and I want the voltage to see them before the leg of the
Place a free PAD out there and call it '1', connect the net to
'gnd'. Then
you can define a rule for plane connect and set the power plane connect
style filter kind to PAD and and look for free pad 1 and
set the Rule
Attributes to No Connect. This will make a clearance around the
pad
/bbrooks/pca/pca.htm
-Original Message-
From: Michael Beavis [mailto:[EMAIL PROTECTED]]
Sent: Thursday, November 29, 2001 4:27 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Padstack
Place a free PAD out there and call it '1', connect the net to
'gnd'. Then
you can define a rule
At 11:27 AM 11/30/01 +1100, Michael Beavis wrote:
Free pads allow for more powerful design rules to be employed but it is
possible to lose them when synchronising from SCH if care is not taken.
If the 'Delete component' option is selected in the sync process and the
free pads do not appear on the
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