Re: [PEDA] Removing IP from PCB (Ex: Protel's Good/Bad points ...)
At 02:16 PM 11/20/01 +1100, Ian Wilson wrote: At 09:46 PM 19/11/01 -0500, you wrote: (This is Design/NetlistManager/Menu/ I forget the exact name, but it is *not* the command that generates a net list from connected copper. It is the other one, that just dumps what is loaded into all the pads.) Design/NetlistManager/Menu/Create Netlist from Connected Copper No, not that one. The other one. It is called export netlist from PCB But this will include the names of the nets. My detailed instructions were largely based on the requirement that the net names needed to be obfuscated as, is common with a clear schematic, the net names themselves may carry significant IP. To mask all the possible IP from the PCB it is necessary to remove the net names and substitute generic netlister/synchroniser allocated names. Normally, there is not significant IP in the netlist, even when fairly descriptive names have been used. It would be very rare that one could extrapolate back from the net list to an understanding of what the board does, unless someone has used *very* descriptive net names, which I have never seen. Knowing that an address bus or a reset line is such would not be sufficient. However, it is possible to edit the net names by a similar procedure to that which can be used when doing netlist translation. A word processor is used to convert the net list net section to a tab-delimited database, one net per record, one node per field beyond the netname field. This is then imported into a spreadsheet, the netname field edited to a numerical sequence which any spreadsheet should be able to accomplish, written back to a tab-delimited database, and then edited back into Protel format. It took me longer to describe it than it would have taken to do it; but then again, I've been doing it for more than ten years -- the Tango format is identical to the original Protel format. I have some translation utilities written in Quickbasic, but I never bothered to make the full translation, it was easy enough in a word processor. (Protel should have used a tab-delimited format from the beginning instead of the one-field per line format that was chosen. It would have not only been shorter but could have been much more easily read and manipulated. I don't know how many times I have seen a client print out a net list that was not translated as I described. Let's see, how many reams do I need to load into the printer. It's not too late, the translation is trivial!) The netlist is necessary in some circumstances as the bug/problem/issue/feature being demonstrated may require a netlist. In the case of a completed board the netlist can be generated from the copper as per the above command sequence. This is not the case in an incomplete board - to be more specific - in a board that is not fully routed. Actually, you can do whatever works, i.e., if the bug persists with all net information removed, so much the better. Basically, before sending off the stripped file, one needs to verify that it still does whatever nasty thing is being investigated. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Removing IP from PCB (Ex: Protel's Good/Bad points ...)
On 04:29 PM 19/11/2001 +, Jason Morgan said: The files in question were returned to Protel under NDA, they confirmed the problems as reported and indicated that at present there was no fix. Sorry, but I can't transmit designs to the public, at least without NDA, thanks for the offer anyway. What I have done with this sort of confidential data (even when sending the file to Protel) is to do a global search and destroy on all PCB parts and change their values to 10k (You see a 10k 256-ball BGA does not contain a lot if IP). I then clear the netlist. If the board is incomplete, and the netlist from the sch is required, then it is a little more complex, but still do-able. I create some dummy schematics and PCB by copying the correct ones, immediately synchronise to make the following processes simpler. I then, globally remove every netlabel of all sheets, rename all the power supplies to meaningless names and change all the component designators to R? or A? or something meaningless. Re-annotate. Then change all the part types to 10k or some other silly value (including all ICs, caps, R's, connectors etc) and synch to the PCB. The resulting netlist and refdesignators convey almost no useful info - just point-to-point connectivity. All identifying text on the PCB is then removed, and all mech layers removed - apart from maybe the outline and the keepout. I then try to remove as many rules and classes as possible to reduce the chance of there being some useful IP embodied in these. However, it is likely that mucking about with the rules is very likely to change the suspect behavior, so this has to be done with some care. I may also rejig the mech outline to mask the target application a little. Possibly remove a few mech holes as well. Then confirm the problem still exists. I then only send it to people who I think I can trust. Not to the public in general. So Jason, if you would like others to try to see if you have hit a limit on the capacity of Protel, this may be one option. I would also be prepared to look at it. So I think you have three long-term members of this forum (at least) who are prepared to see what your file does to their machine. I would be very interested in the results of such a test. (I run Win2K, SP2, 256MB, PIII-450). I for one do not discount the troubles that Jason has reported over some time on this forum. However as others have said, quite a few of us see very very few Protel crashes these days, and there must be significant differences in the hardware we run. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Removing IP from PCB (Ex: Protel's Good/Bad points ...)
At 09:46 PM 19/11/01 -0500, you wrote: At 08:49 AM 11/20/01 +1100, Ian Wilson wrote: If the board is incomplete, and the netlist from the sch is required, then it is a little more complex, but still do-able. If the board has all the footprints, i.e., there is a pad for every node in the net list, it is simple to load the netlist, globally edit all the comments to something innocuous, then dump the net list. It will not contain any of the original part type information, just reference designators, footprints, and nets. (This is Design/NetlistManager/Menu/ I forget the exact name, but it is *not* the command that generates a net list from connected copper. It is the other one, that just dumps what is loaded into all the pads.) Design/NetlistManager/Menu/Create Netlist from Connected Copper But this will include the names of the nets. My detailed instructions were largely based on the requirement that the net names needed to be obfuscated as, is common with a clear schematic, the net names themselves may carry significant IP. To mask all the possible IP from the PCB it is necessary to remove the net names and substitute generic netlister/synchroniser allocated names. The netlist is necessary in some circumstances as the bug/problem/issue/feature being demonstrated may require a netlist. In the case of a completed board the netlist can be generated from the copper as per the above command sequence. This is not the case in an incomplete board - to be more specific - in a board that is not fully routed. Bye for now, Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
