In a recent discussion on re-annotation a regular poster to this forum was
skeptical that the synchronizer would cope with large scale changes to
designators, including resetting and then re-running the Sch annotation
process. This shows signs of "old-style netlist thinking" where one had to
be careful to back-annotate for each re-annotation as mapping was done
solely by designator and a Was/Is file. I am getting quite frustrated at
what seems to be an almost deliberate policy of ignoring how it (the
synchronizer) does work and then having the nerve to throw the odd grenade
over the netlist battlement in order to spread FUD. I use the synchonizer
and have since it became available; I do not really care what others use; I
do care that facts are being confused by throw away statements - especially
from someone respected for the depth of assessment they usually undertake.
I repeat a statement I have made before - when you use the synchronizer it
allocates hidden handles to each component in the Sch and PCB and uses
these to match Sch to PCB. Believe it. You can re-annotate as many times
as you wish in whatever fashion you wish and still the synchronizer will
correctly update PCB or Sch components. I tried it - it works.
(Bugs not withstanding - it does seem that it is possible to confuse the
synchronizer if you mix netlist operations with the synchronizer, if you
try hard enough. I have seen this once in - it was covering in quite a
detail thread on this forum some months ago.)
You do not need to take just my word for this -
http://www.protel.com.au/earticles/design_synchronization.htm
Rant mode over and out,
Ian Wilson
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