Re: [PEDA] adjacent component placement DXP
On 06:45 PM 9/07/2003, Jason Morgan said: Firstly you posted to the wrong list, this list is for Protel 99se, and not DXP, there is a separate list for DXP issues, see http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp PEDA is not just for P99SE but is certainly mainly used for that - the Altium DXP list certainly has a much higher SNR both generally and for DXP related stuff. To answer your question, its the same as in 99se, you create a component-component clearance rule that uses the same component type for each side of the rule. I use this exact method for a mechanical part that sits over some LEDs. e.g. Create a rule in Placement: Component Clearance: New Rule HasFootprint('FOOTPRINT_1') vs HasFootprint('FOOTPRINT_1') you need to specify Full Check and a large negative clearance, e.g. -999mm My experience is that this doesn't work. DXP does not support negative clearance checking (overlaps). It has been something I and others have been asking for for a while now. I just tried a test case and couldn't get it to pass a batch DRC if I had any overlap at all - a negative clearance acted like a zero clearance. Are you sure this has worked for you, Jason. Can you give a little more detail? I would love to know why it doesn't work for me. The only way I have been able to solve this sort of problem is by excluding the affected footprint from testing by making the general (All-All) rule into a: NOT HasFootprint('FOOTPRINT_1') vs NOT HasFootprint('FOOTPRINT_1') This excludes 'FOOTPRINT_1', in this case, from any clearance checking - but this then means that *no* component is checked against any component with footprint 'FOOTPRINT_1'. I thought I had solved this issue to exclude just 'FOOTPRINT_1' from being checked against any other 'FOOTPRINT_1' but all other components being checked against each other and 'FOOTPRINT_1' but I can't recall and it is late. I think there should be something in the DXP forum archive on this. This solution is pretty poor as it doesn't scale well. A number of users have been requesting generalised clearance rules (not just component and electrical) with negative clearance (overlap) capability. Hopefully it will appear in a DXP SP soon. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] adjacent component placement DXP
Ian, I can state that it works for me - honest. The area of the PCB in question is over 2 years old - obviously inherited from 99se. In this case, the components in question are an array of LEDs with a light pipe over them, all tightly packed together. I've not experimented with the actual parameters in DXP, but I know 'full checking' MUST be on and I recall having to play with the negative clearance in 99se, ending up at -127mm. IIRC The online DRC always fails - annoyingly - but a full DRC passes with this rule in place. If I find time I'll take a look at it and see if I can work out *WHY* it works. It seems that this method perhaps does not work in all cases, at least without some messing and plain luck. I agree on the generalised clearance rule. Hm, perhaps this conversation should be on DXP as it seems a little product enhancement is in order ;) J. -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Sent: 09 July 2003 12:59 To: Protel EDA Forum Cc: DXP Technical Forum Subject: Re: [PEDA] adjacent component placement DXP On 06:45 PM 9/07/2003, Jason Morgan said: Firstly you posted to the wrong list, this list is for Protel 99se, and not DXP, there is a separate list for DXP issues, see http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp PEDA is not just for P99SE but is certainly mainly used for that - the Altium DXP list certainly has a much higher SNR both generally and for DXP related stuff. To answer your question, its the same as in 99se, you create a component-component clearance rule that uses the same component type for each side of the rule. I use this exact method for a mechanical part that sits over some LEDs. e.g. Create a rule in Placement: Component Clearance: New Rule HasFootprint('FOOTPRINT_1') vs HasFootprint('FOOTPRINT_1') you need to specify Full Check and a large negative clearance, e.g. -999mm My experience is that this doesn't work. DXP does not support negative clearance checking (overlaps). It has been something I and others have been asking for for a while now. I just tried a test case and couldn't get it to pass a batch DRC if I had any overlap at all - a negative clearance acted like a zero clearance. Are you sure this has worked for you, Jason. Can you give a little more detail? I would love to know why it doesn't work for me. The only way I have been able to solve this sort of problem is by excluding the affected footprint from testing by making the general (All-All) rule into a: NOT HasFootprint('FOOTPRINT_1') vs NOT HasFootprint('FOOTPRINT_1') This excludes 'FOOTPRINT_1', in this case, from any clearance checking - but this then means that *no* component is checked against any component with footprint 'FOOTPRINT_1'. I thought I had solved this issue to exclude just 'FOOTPRINT_1' from being checked against any other 'FOOTPRINT_1' but all other components being checked against each other and 'FOOTPRINT_1' but I can't recall and it is late. I think there should be something in the DXP forum archive on this. This solution is pretty poor as it doesn't scale well. A number of users have been requesting generalised clearance rules (not just component and electrical) with negative clearance (overlap) capability. Hopefully it will appear in a DXP SP soon. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] adjacent component placement DXP
Hi all, Need to place a number of terminal blocks in a row, with the body of each touching that of its neighbour, on a PCB being laid out in Protel DXP. Despite setting the electrical placement and component clearance DRCs for these particular components to 0mm, Protel still flags this a violation when they are placed next to each other. . Anyone come across this problem/know of a workaround? Many thanks Gwyn Roberts Univ of Wales, Bangor * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] adjacent component placement DXP
Firstly you posted to the wrong list, this list is for Protel 99se, and not DXP, there is a separate list for DXP issues, see http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp To answer your question, its the same as in 99se, you create a component-component clearance rule that uses the same component type for each side of the rule. I use this exact method for a mechanical part that sits over some LEDs. e.g. Create a rule in Placement: Component Clearance: New Rule HasFootprint('FOOTPRINT_1') vs HasFootprint('FOOTPRINT_1') you need to specify Full Check and a large negative clearance, e.g. -999mm Make sure that the rule priority puts this rule above the global clearance rule, Press the Priorities button to check. Also, make sure that one of the electrical clearance rules does not also fail, though you should be able to tell the difference of a component clearance fail and a net fail by the colours on the screen. Jason. -Original Message- From: Dr Gwyn Roberts [mailto:[EMAIL PROTECTED] Sent: 09 July 2003 09:21 To: [EMAIL PROTECTED] Cc: Aled Williams Subject: [PEDA] adjacent component placement DXP Hi all, Need to place a number of terminal blocks in a row, with the body of each touching that of its neighbour, on a PCB being laid out in Protel DXP. Despite setting the electrical placement and component clearance DRCs for these particular components to 0mm, Protel still flags this a violation when they are placed next to each other. . Anyone come across this problem/know of a workaround? Many thanks Gwyn Roberts Univ of Wales, Bangor * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] adjacent component placement DXP
The very same thing in 98SE made me quite cross. There is probably a right way to fix this. I couldn't find it and turned off the component clearance rule instead. Dr Gwyn Roberts [EMAIL PROTECTED]To: [EMAIL PROTECTED] ngor.ac.uk cc: Aled Williams [EMAIL PROTECTED] Subject: [PEDA] adjacent component placement DXP 09-Jul-2003 09:20 AM Please respond to Protel EDA Forum Hi all, Need to place a number of terminal blocks in a row, with the body of each touching that of its neighbour, on a PCB being laid out in Protel DXP. Despite setting the electrical placement and component clearance DRCs for these particular components to 0mm, Protel still flags this a violation when they are placed next to each other. . Anyone come across this problem/know of a workaround? Many thanks Gwyn Roberts Univ of Wales, Bangor * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] adjacent component placement DXP
Dr Gwyn Roberts wrote: Hi all, Need to place a number of terminal blocks in a row, with the body of each touching that of its neighbour, on a PCB being laid out in Protel DXP. Despite setting the electrical placement and component clearance DRCs for these particular components to 0mm, Protel still flags this a violation when they are placed next to each other. . Anyone come across this problem/know of a workaround? Many thanks Gwyn Roberts Univ of Wales, Bangor One solution is to draw the component outline of these parts slightly undersize. For example, for 1/4W resistors that I want to place on 0.1 inch centers, I make the component outline 0.090 wide - then, even with .01 wide tracks for the outline, the outlines will not overlap. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *