Where can we get the reference help document for the protel supported
hyp format ?
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Currently we always allowed the individual design engineers to create their
own personal component/footprint libraries. I'm just about to install DXP
and want to standardise a method to maintain a group library. Hopefully we
could then easy identify components already within the library and be
problems
(convergence) are spice related and are no P99 issues.
Rolf Molitor
Ing.Buero i2e
Remscheid/Germany
-Ursprüngliche Nachricht-
Von: Julian Higginson [EMAIL PROTECTED]
An: 'Protel EDA Forum' [EMAIL PROTECTED]
Gesendet: Dienstag, 12. November 2002 08:33
Betreff: [PEDA] help: basic
Has anyone on this list had much luck with the Protel circuit simulator?
Having mentioned it in passing a week or so ago, I've decided that since
I've got it I may as well be using it, but I'm having an annoying problem.
(P99se6, win2k, access ddb, single sheet schematic, stock sim components)
i *did* put the smiley face :)
Dennis Saputelli
Ian Wilson wrote:
On 01:58 PM 8/06/2002 -0700, Dennis Saputelli said:
boy that's a great point pat
i do them on doubles a lot but might have blown it on multi if it ever
came up
of course a board shop would never let that get out would
Mr. Lyons,
Thanks for the advice. No, it is a double sided pth.
Regards
Ken
-Original Message-
From: Pat Lyons [mailto:[EMAIL PROTECTED]]
Sent: Friday, June 07, 2002 7:59 PM
To: Protel EDA Forum
Subject: Re: [PEDA] help, how do i make rectangular holes in components
and on the pcb
boy that's a great point pat
i do them on doubles a lot but might have blown it on multi if it ever
came up
of course a board shop would never let that get out would they ? :)
Dennis Saputelli
Pat Lyons wrote:
On Fri, 07 Jun 2002 10:29:42 -0400, Ken Henrich wrote:
Hi
I want to make
On 01:58 PM 8/06/2002 -0700, Dennis Saputelli said:
boy that's a great point pat
i do them on doubles a lot but might have blown it on multi if it ever
came up
of course a board shop would never let that get out would they ? :)
Wanna bet? On an early board I did (years ago) I forgot to pull
Hi
I want to make rectangular holes in pads for components with metal tabs. For
instance, a hole 40mils by 120 mils. Can this be done in Protel 99SE? BTW,
is hole the proper nomeclature for this?
thanks and regards
Ken
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Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.
-Original Message-
From: Ken Henrich [mailto:[EMAIL PROTECTED]]
Sent: Friday, June 07, 2002 7:30 AM
To: Protel EDA Forum
Subject: [PEDA] help, how do i make rectangular holes in
components
Ken, I've done this by creating cutouts of the proper size (tiny)
using say four 1mil holes on 5mil pads. I included on the Drill Drawing
a detail showing routing a rectangular cutout from these sets of
1mil holes. You _must specify_ Plate Through for all these special
cutouts. Note that you
Hello Ken,
Friday, June 7, 2002, 7:29:42 AM, you wrote:
Hi
I want to make rectangular holes in pads for components with metal tabs. For
instance, a hole 40mils by 120 mils. Can this be done in Protel 99SE? BTW,
is hole the proper nomeclature for this?
thanks and regards
Ken
The best way to do this is to call your fab and ask them how they want the
information provided.
A slot, or rectangular hole, is done at the fab by using a routing bit -
usually after the board is complete, but before finish plating and
masking. Your fab will have its own procedures and
I want to make rectangular holes in pads for components with metal tabs. For
instance, a hole 40mils by 120 mils. Can this be done in Protel 99SE? BTW,
is hole the proper nomeclature for this?
I've done this in the past by placing the appropriate track on the drill drawing
layer, then
: Re: [PEDA] help, how do i make rectangular holes in components
and on the pcb itself?
Hello Ken,
Friday, June 7, 2002, 7:29:42 AM, you wrote:
Hi
I want to make rectangular holes in pads for components with metal tabs.
For
instance, a hole 40mils by 120 mils. Can this be done in Protel 99SE
On Fri, 07 Jun 2002 10:29:42 -0400, Ken Henrich wrote:
Hi
I want to make rectangular holes in pads for components with metal
tabs. For
instance, a hole 40mils by 120 mils. Can this be done in Protel
99SE? BTW,
is hole the proper nomeclature for this?
thanks and regards
Ken
You didn't mention
can anyone advise me on the following please?
i am about to do a design for a 150,000 pc run
for cost reasons (low end commercial product) the bd material must be
made out of night soil (actually phenolic)
the design is SMD and to be a single sided bd (one etch layer)!
the lead pitch is 0.5mm
June 18-21.
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]]
Sent: Thursday, May 30, 2002 9:34 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Help re bd material
can anyone advise me on the following please?
i am about to do a design for a 150,000 pc run
[mailto:[EMAIL PROTECTED]]
Sent: Thursday, May 30, 2002 9:34 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Help re bd material
can anyone advise me on the following please?
i am about to do a design for a 150,000 pc run
for cost reasons (low end commercial product) the bd material must
2G2-09 at CommunicAsia 2002 in Singapore June 18-21.
-Original Message-
From: Dennis Saputelli [mailto:[EMAIL PROTECTED]]
Sent: Thursday, May 30, 2002 10:30 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Help re bd material
thanks for your comments, we hope to do a no via design
Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, May 30, 2002 12:34 PM
Subject: Re: [PEDA] Help re bd material
can anyone advise me on the following please?
i am about to do a design for a 150,000 pc run
for cost reasons (low end commercial product) the bd
Hi everyone,
We have only installed Protel 99SE SP6 this year on our network, and I have
just starting introducing the pcb editor to the students.
I am not a network IT person but will attempt to describe the problem(s).
Most of the students had a problem showing itself when we browsed pcb
Just remember to balance you layer stack thicknesses to prevent the board
from being warped.
- Original Message -
From: Jon Elson [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, February 21, 2002 3:59 PM
Subject: Re: [PEDA] help with a stack ??
Robison Michael
hello,
i've got a negative (ECL) and a positive (TTL) power plane
on a board i'm doing. right now i'm figuring on a matching
ground plane for each power supply, spaced close to the
rail for switching capacitance. here's the stack i'm
thinking of:
critical traces
gnd
-5.2V
noncritical
Mike,
use this stack up
non critical
gnd
critical
-5
gnd
critical
+5 (better if this was ground)
non critical
or
gnd
critical
non critical
power
gnd
non critical
critical
gnd (if power switch critical and non critical)
two reasons why I say put the critical in the
Robison Michael R CNIN wrote:
hello,
i've got a negative (ECL) and a positive (TTL) power plane
on a board i'm doing. right now i'm figuring on a matching
ground plane for each power supply, spaced close to the
rail for switching capacitance. here's the stack i'm
thinking of:
critical
Mike, I've run into trouble by assuming the board house
would equalize dielectric thickness in the layer stack.
Some do, some don't.
I now add a fab note to equalize dielectric thickness +/- 10%
to get an approximately known dielectric thickness. Or you
can specify the prepreg thickness between
At 02:25 PM 2/21/2002 -0500, Robison Michael R CNIN wrote:
hello,
i've got a negative (ECL) and a positive (TTL) power plane
on a board i'm doing. right now i'm figuring on a matching
ground plane for each power supply, spaced close to the
rail for switching capacitance. here's the stack i'm
Hi all,
I'm putting together a session for this year's Australian Surface
Mount Conference, which is an annual affair run by the Surface
Mount and Circuit Board Association (SMCBA) in Australia.
The session's likely to be a whole day seminar covering, broadly,
an introduction to PCB design.
Can anyone offer advice on installing Addons programs into P99SE, as I
downloaded various programs, but very really do they work, mostly Protel
just locks up...
Simple Programs like Hole Size Editor work, and I eventually got the
trial version of ActiVplace to work, after downloading it about
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At 09:21 AM 11/13/01 -0500, Sean James wrote:
Ian, this is a good suggestion, however, the PCB hasn't any named nets. He
just wires point to point, and keeps track of the wiring in his head by
using his rough schematic.
I'll be more explicit.
That is *not* a problem. Design/Netlist/Menu/Create
x33
(FAX) 413.541.6170
- Original Message -
From: Abd ul-Rahman Lomax [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, November 13, 2001 12:38 PM
Subject: Re: [PEDA] HELP!
At 09:21 AM 11/13/01 -0500, Sean James wrote:
Ian, this is a good suggestion, however
At 02:53 PM 11/13/01 -0500, Sean James wrote:
OK, Abdul, I got the first part to work and created a *netlist* on the PCB.
Now how do I load that into the schematic and get the Ref Des to come out
correct and not erase the schematic.
You can't just load it in. This would require more software
PROTECTED]
Sent: Monday, November 12, 2001 2:36 PM
Subject: [PEDA] HELP!
Has anybody out there ever have to upated a schematic's reference
designators based on a PCB layout, when there is NOT a netlist to back
annotate. I have to clean up an engineer's schematics, and he refuses to use
an inteligent
Guralnick
- Original Message -
From: Bagotronix Tech Support [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Monday, November 12, 2001 2:50 PM
Subject: Re: [PEDA] HELP!
| I don't have help for you, but maybe I have help for him.
|
| If the reason he won't use schematic
At 02:36 PM 11/12/01 -0500, Sean James wrote:
Has anybody out there ever have to upated a schematic's reference
designators based on a PCB layout, when there is NOT a netlist to back
annotate.
Sure.
I have to clean up an engineer's schematics, and he refuses to use an
inteligent schematic
I think I would enter the schematic as best as I could from the cryptic
notes and breadboard and then present the engineer with a printout of the
schematic. Then tell him he must sign off on the schematic or any errors
will not be your responsibility. You can then use Protel to create netlist
On 02:36 PM 12/11/2001 -0500, Sean James said:
Has anybody out there ever have to upated a schematic's reference
designators based on a PCB layout, when there is NOT a netlist to back
annotate.
Yes.
I have to clean up an engineer's schematics, and he refuses to use an
inteligent schematic
On 04:07 PM 7/16/2001 -0700, Daniel Webster wrote:
Has anyone ever tried to modify or add to the help menu ? Is this possible ?
If anyone knows how to add menu items which link to text documents in the
help menu structure please let me know.
I don't believe this has been answered yet...
Double
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