Re: [PEDA] IPC Footprint Standards
At 03:36 PM 12/08/02 +1000, you wrote: Greetings all, I have a copy of IPC-SM-782. In it are described various recommended footprints for resistors, capacitors, discrete semis and ICs. I also have some documentation from Philips Semiconductors describing the same items. The problem is that the sizes represented in each publication are vastly different. What dangers are there in straying from the path prescribed by the IPC? If I work from the Philips documents I have smaller footprints for things like generic 0603 and 0805 thus allowing for tighter layouts. My copy of IPC-SM-782 is date 1993 - is it likely that the footprint recommendations would have changed in later revisions of the standard? Linden, I have always found the postage stamp sized IPC footprints for passives ridiculous. The data in the Philips databook has always served us well. We have had one manufacturer say that they would like larger pads - but these were much larger than the IPC std and I simply ignored them (production was reliable, apart from all the solder balls - they have since gone under). I use the Philips book as my bible for 0603, 0805, 1206, SOT-23, SOT223 etc and a number of others. I use their recommendation for wave and reflow footprints. I modify the component outline (silkscreen) so it is a bar at each end of the component (not on each side) - I do not put a full outline box. This works well as my component bars just touch (actually just don't touch) on a 5 mil grid and I do not have to oversize the silkscreen in two dimensions to simply be able to fit the silkscreen outline in. My previous surface mount boards have not been overly tight but this is not the case with the latest job - I need all the space I can get. I find that the width and accuracy of the overlay lines can be a limiting factor in packing in passives. So speak to your PCB maker to find out the smallest overlay line width that looks OK and what sort of registration they can ensure. This will reduce the space required of your components - make sure you still meet the pick-and-place rules though - speak to the assembler and push them a little, they always want it easy. For really tight layouts we find the via sizes can also be an issue so think about minimizing these as much as possible. Oh, for padless vias. By tenting the vias you can bring them quite close to component pads. If they are untented then you need a larger pad/via clearance. Throwing layers at a tight design may not always be helpful - at least in the first instance. We have done a number of very small, but low volume boards. The problem here is trying to optimise cost (we can't go laser micro-vias etc) but still make the space constraints. Having the extra layers available too early in the layout has, in the past, hidden a better layout that we could achieve by that most critical of things, placement. (These boards could also not go 0402 component sizes for cost reasons. They were done a number of years ago.) Ian Wilson * Tracking #: 18633C95F079D643BB95ED85E12F96C6981988A2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] IPC Footprint Standards
Linden, Given the two footprint documents, IPC vs the manufacture's , I will always use the manufacture's first. The manufacture has generally allowed for tolerances specifically designed for their part. Under some circumstances, I have had large contract manufactures provide me with very specific design guidelines which altered footprints for their reflow process. One claimed since he was also responsible to his client to provide warranty, any percent of increased reliability = one percent of his profits. I would set the precedence to follow the manufacture's guidelines then IPC. (which by the way is very good) Mike Reagan - Original Message - From: Linden Doyle [EMAIL PROTECTED] To: PEDA [EMAIL PROTECTED] Sent: Sunday, August 11, 2002 10:36 PM Subject: [PEDA] IPC Footprint Standards Greetings all, I have a copy of IPC-SM-782. In it are described various recommended footprints for resistors, capacitors, discrete semis and ICs. I also have some documentation from Philips Semiconductors describing the same items. The problem is that the sizes represented in each publication are vastly different. What dangers are there in straying from the path prescribed by the IPC? If I work from the Philips documents I have smaller footprints for things like generic 0603 and 0805 thus allowing for tighter layouts. My copy of IPC-SM-782 is date 1993 - is it likely that the footprint recommendations would have changed in later revisions of the standard? My previous surface mount boards have not been overly tight but this is not the case with the latest job - I need all the space I can get. Any comments would be greatly appreciated. Thanks and Best Regards, Linden Doyle Product Development Engineer Zener Electric Pty Ltd. Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] * Tracking #: 7AE998780E1AD14BA518CF969F9E79261307E4BB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] IPC Footprint Standards
Linden, Well the IPC land patterns are in fact a very good place to start. However you are right there is a later version coming out which does in fact address the needs of most situations. The version you have gave a broad range in tolerenaces and yes if you go towards the can be assembled any where range the patterns are somewhat big. The new data provides 3 categories of build it anywhere, to the middle of the road, to the high end leaving the designer with an easy choice pending the technology of the type of designs being done. Rather than try to figure out what tolerances equate to what technology. What I have found though is when it comes to the run of the mill parts ie chip type res's, caps etc and SO parts the IPC has been very acceptable but when it comes to any fine pitch parts you really need to look at the MFG for tolerances of their part. Even if two MFG's call it a TQFP100 the basic dimension could very well be the same but each could have vastly different tolerances, which could sway which way to go ultimately for a land pattern. The MFG have been getting better with respect to this but not quite there yet. I have also strayed from the IPC as far as a maximum material design strategy for land patterns on the basic stuff too as I needed to design much tighter designs moving towards the minimums on these packages. Hope this helped Bob Wolfe - Original Message - From: Linden Doyle [EMAIL PROTECTED] To: PEDA [EMAIL PROTECTED] Sent: Monday, August 12, 2002 1:36 AM Subject: [PEDA] IPC Footprint Standards Greetings all, I have a copy of IPC-SM-782. In it are described various recommended footprints for resistors, capacitors, discrete semis and ICs. I also have some documentation from Philips Semiconductors describing the same items. The problem is that the sizes represented in each publication are vastly different. What dangers are there in straying from the path prescribed by the IPC? If I work from the Philips documents I have smaller footprints for things like generic 0603 and 0805 thus allowing for tighter layouts. My copy of IPC-SM-782 is date 1993 - is it likely that the footprint recommendations would have changed in later revisions of the standard? My previous surface mount boards have not been overly tight but this is not the case with the latest job - I need all the space I can get. Any comments would be greatly appreciated. Thanks and Best Regards, Linden Doyle Product Development Engineer Zener Electric Pty Ltd. Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] * Tracking #: 7AE998780E1AD14BA518CF969F9E79261307E4BB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] IPC Footprint Standards
Re: [PEDA] IPC Footprint Standards
On 07:55 AM 12/08/2002 -0600, Westfeldt, Pat said: Ian Do you have a URL for this particular Phillips databook? Thank you. Patrick Westfeldt, Jr. Patrick, No I don't - the data I have comes from real databooks - you know that old paper stuff. It probably exists on the various Philips www sites http://www.semiconductors.philips.com and http://www.bccomponents.com but I have not looked in detail. A search for footprints on the Philips site did throw up so stuff that may be interesting but I didn't look in detail. The SOT-23, SOT-89, SOT-223 etc wave and reflow footprints that we use are very similar to those in the Surface Mounted Semiconductors SC10a databook (ours is 1994 I think). The 0603, 0805, 1206 etc to 2210 came from one of the passive databooks - Ceramic Capacitors can't recall the number (Tony, what was the number I emailed to you? I am at a different location) (ours is 1991 edition). Both are quite old but the footprints have always worked very well for us. If anyone finds them then a post here would be nice. My main beef with the IPC footprints is that they have to be oversized as they take no account of solder process. A reflow footprint can (and probably should) be smaller than a wave footprint. This improves density. (Smaller improves self-centering and reduces tombstoning - neither of which are a big problem with the IPC std but the point is for reflow a better packing density can be had without a significant drop in reliability). A wave footprint has to take into account the need to pick up solder (oversized in the long dimension), shadowing and thieving requirements (for the ICs) and acceptable pad clearance for the glue dots. The IPC seems to me to be just some worst-case collection of the two requirements -certainly an OK starting point but if packing density is critical then they are certainly not optimum. This was the point in Linden's original post. I have read somewhere (maybe Printed Circuits Handbook (Clyde, 4th Edition), possibly in some notes from elsewhere, that the heel rather than the toe is the most critical part of the join (from a strength perspective). Reflow footprints can theoretically have no toe and still be reliable at least according to the data I read some year ago. The obvious problem with this is the difficulty of inspection for QA - but these days we have that with BGA footprints don't we. I would not suggest that anyone reduces their small device pads this far on my recommendation - I have never gone that far. Disclaimer - few of our boards undergo massive temperature changes, and most are not subject to high vibration environments. There would no doubt be times when I would enlarge my footprint pads to increase reliability in harsh environments. I gather the SMC-plus (is that right?) footprint libraries may have soldering technology specific footprints - at least someone once told me they did. Ian Wilson * Tracking #: 46CA0A63921CE34BADA4C13E495F03077F195FA5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] IPC Footprint Standards
Ian, as for your comments below, I will vouch for your comments 100%. Typically almost 2/3rds of the solder in on a gull wing device is reflowed to the heel area. Thus where is the strongest portion of the joint? Typically the toe supplies a place to probe or apply heat from your hand soldering iron during re-work/touch-up. SMT Plus' land pattern designs are designed for a standard paste application of 6 - 8 mils where the paste mask aperture matches the pad aperture. They are also significantly smaller then the former IPC land patterns. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Monday, August 12, 2002 4:38 PM To: Protel EDA Forum Subject: Re: [PEDA] IPC Footprint Standards SNIP I have read somewhere (maybe Printed Circuits Handbook (Clyde, 4th Edition), possibly in some notes from elsewhere, that the heel rather than the toe is the most critical part of the join (from a strength perspective). Reflow footprints can theoretically have no toe and still be reliable at least according to the data I read some year ago. The obvious problem with this is the difficulty of inspection for QA - but these days we have that with BGA footprints don't we. I would not suggest that anyone reduces their small device pads this far on my recommendation - I have never gone that far. SNIP I gather the SMC-plus (is that right?) footprint libraries may have soldering technology specific footprints - at least someone once told me they did. Ian Wilson * Tracking #: DCA0DE9A4E1A724296D1D2500E3F0CC5B4DA14E5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
