Re: [PEDA] Not routing nets and poly pours...and maybe a bug for the bug list?

2001-09-05 Thread Brad Velander

Phillip,
looking at just your comment below, seems that you had accomplished
your task. However, it sounds like you did not assign the correct netname to
your polygon pour or you did not check the pour over same net checkbox in
the polygon pour control, when you made that attempt.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Phillip Stevens [mailto:[EMAIL PROTECTED]]
 Sent: Wednesday, September 05, 2001 1:23 PM
 To: Protel EDA Forum
 Subject: [PEDA] Not routing nets and poly pours...and maybe a bug for
 the bug list?
 
 Not seeing a direct way to do this,  I tried a few things like making
 rules for VCC/GND nets to be 0 width traces.
 If you do this,  when you do the pours,  you get whatever
 the clearance is on both sides of a 0 width trace,  so you end up
 with holes in the poly pour around a 0 length trace.   In a way what I
 told it to do I guess,  but not what I really wanted...
 
 
 Anyway,  I finished my board.  Wanted to report the router bug,  and
 ask if there is a more direct path I can use for this next time.
 
 ---Phil

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Re: [PEDA] Not routing nets and poly pours...and maybe a bug for the bug list?

2001-09-05 Thread Abd ul-Rahman Lomax

At 04:23 PM 9/5/01 -0400, Phillip Stevens wrote:

How does one specify a Net not be routed,  but still be checked
for in the ERC?  I have a pretty simple 2 layer board.  2 X 2.7
with a few parts on it.  I'm using P99SE SP6 on Win98

What I wanted to do was to route all the signal lines first and then poly pour
VCC/GND.  (This is a simple,  low speed, low cost, 2 layer design btw..)

If the design is so much low speed that you need not pay attention to power 
routing topology, then it is so much low speed that probably doing pours is 
unnecessary. The same arguments apply to both!

Not seeing a direct way to do this,  I tried a few things like making
rules for VCC/GND nets to be 0 width traces.

If you do this,  when you do the pours,  you get whatever
the clearance is on both sides of a 0 width trace,  so you end up
with holes in the poly pour around a 0 length trace.   In a way what I
told it to do I guess,  but not what I really wanted...

Mr. Velander inferred from this, I think correctly, that Mr. Stevens had 
not set pour over same net, which would have accomplished what he wanted.

A *direct* way to not route VCC and GND would be to delete the nets using 
the Netlist Manager. Then resynchronize the PCB and schematic

But I would suggest, for a board like this, unless there is some condition 
which has not been explained, that power and ground be routed *first*, 
manually, which is the only way you are going to get a good low-impedance 
power route (it might not be necessary, but it won't hurt, for sure), then 
route the signals (and if this is a very small design one might skip the 
autorouter anyway, but to each his own...), then do ground pours. Don't do 
a VCC pour.

It's been noted that there is no ground but there sure is when one is 
considering possible shorts to a case or what can happen with a careless 
screwdriver.

Then I tried making the trace width impossibly large.  It's a 2 X 2.7
board,  so I made the (min/max/pref) trace width all 5.  That
way it can't _possibly_ route those nets then I'll just do the poly
pour over it...  The router happily placed 3-4 VCC/GND tracks down
on the board.  At maybe 50-100 mil width.  This has to be a bug?
The router should not put down tracks that fail to meet the design
rules?

Hmmm, a designer considers the program's behavior a bug; perhaps the 
program would have the right to call the designer's behavior a bug! Feeding 
a program data which is outside what would have been thoroughly tested is a 
good way to discover unanticipated results. If it works, great! But don't 
be surprised when it doesn't work!

Another way to prevent the routing of a net, with a through-hole design, is 
to create an inner plane for the net

But there was no good reason I can see to prevent the routing of those 
nets. The pour, if one insists on having one, can then be poured over the 
existing nets. The only problem with this is that there will likely be 
extra copper ties to the pour, which is harmless but unsightly. If the 
original track is highlighted -- which could be easily done with a global 
edit of track with the appropriate net as a selection criterion -- and then 
deleted, this would quickly clean that up.

I also tried net unroute,  but this seems to just take out a segment
of the net,  and not the whole net (though I think this may have
worked in the past).  Even had this worked though,  the traces would
not have been as direct as they could have been without the VCC/GND nets in
the way.

And since it is a low-speed design, why care about that?

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Not routing nets and poly pours...and maybe a bug for the bug list?

2001-09-05 Thread Ian Wilson

On 04:23 PM 5/09/2001 -0400, Phillip Stevens said:

How does one specify a Net not be routed,  but still be checked
for in the ERC?  I have a pretty simple 2 layer board.  2 X 2.7
with a few parts on it.  I'm using P99SE SP6 on Win98

I have not tried it but, under the Design Rules|Routing|Routing Layers 
rule, add a new rule.  Specify Net scope and then disable all the 
layers.  This should prevent the routing routing this net.


What I wanted to do was to route all the signal lines first and then poly pour
VCC/GND.  (This is a simple,  low speed, low cost, 2 layer design btw..)

If you specify Pour over net then it should not matter if the router has 
routed the nets - you can still pour the poly over the top (just make sure 
you specify Pour Over and the correct net name.


Not seeing a direct way to do this,  I tried a few things like making
rules for VCC/GND nets to be 0 width traces.
If you do this,  when you do the pours,  you get whatever
the clearance is on both sides of a 0 width trace,  so you end up
with holes in the poly pour around a 0 length trace.   In a way what I
told it to do I guess,  but not what I really wanted...

As Brad says, sound like you might like to investigate the pour options you 
used.

Then I tried making the trace width impossibly large.  It's a 2 X 2.7
board,  so I made the (min/max/pref) trace width all 5.  That
way it can't _possibly_ route those nets then I'll just do the poly
pour over it...  The router happily placed 3-4 VCC/GND tracks down
on the board.  At maybe 50-100 mil width.  This has to be a bug?
The router should not put down tracks that fail to meet the design
rules?

I agree.  Sounds like a bug.  I have had problems with the rules at times, 
mostly order of priority issues.  What is specified as the width rule for 
the Whole Board?  Maybe the router is incorrectly picking up the whole 
board scope and using it.  Does sound like a bug.


I also tried net unroute,  but this seems to just take out a segment
of the net,  and not the whole net (though I think this may have
worked in the past).  Even had this worked though,  the traces would
not have been as direct as they could have been without the VCC/GND nets in
the way.

Traces should not be in the way of a polygon pour with the same net and 
pour over option set.

If you can investigate further whether the router was picking up another 
width constraint rule and let me know I will get on and add the report to 
the bug list.  I have about 10 bugs and possible bugs to add I think at 
this stage, all reported over the past couple of months on this list, but 
not yet added to the bug list.

Ian Wilson

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