Re: [PEDA] Power supply pins
Laurie Biddulph wrote: Is there any recommended method in Protel 99 of handling the power pins on logic chips similar to my first method above that Protel 99 can handle comfortably? Let me advocate my preferred method. I have the schematic symbol identical to the footprint, the powerpins visible. What the powerpins concerns I tend to work with netlabels, so the schematic is not cluttered with useless wires. The advantage is the ease of debugging with the scope probe. The schematic is sufficient. The small overhead in manually swapping the wires for re- assignment is considered worth the effort. Rene -- Ing.Buro R.Tschaggelar http://www.ibrtses.com Your newsgroups @ http://www.talkto.net * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power supply pins
At 05:58 AM 12/21/2003, Rene Tschaggelar wrote: Laurie Biddulph wrote: Is there any recommended method in Protel 99 of handling the power pins on logic chips similar to my first method above that Protel 99 can handle comfortably? Let me advocate my preferred method. I have the schematic symbol identical to the footprint, the powerpins visible. What the powerpins concerns I tend to work with netlabels, so the schematic is not cluttered with useless wires. The advantage is the ease of debugging with the scope probe. The schematic is sufficient. The schematic is sufficient in either case (i.e., physical layout or functional symbol); likewise either case generates net lists perfectly well. (This is a separate question from power pin visibility, since power pins can be visible with functional symbols, in several ways, as have been discussed.) However, certainly, having a symbol topologically the same as the footprint makes it easier to identify pins on the physical part, hence Rene's comment. But there are other ways of acheiving similar results, maybe a little paint -- or silkscreen pin legend -- on the PCB. And many times I've read a schematic with such footprint symbols and it *really* slows me down in terms of understanding the *function* of the part in question, and thus where a tech would want to probe. Is it an input or an output? How do the signals flow across the page? If you've got a pile of logic, i.e., inverters, nand gates, etc., it is next to incomprehensible if you don't use functional signals; only if there is bus logic, with the pins being physically laid out in a rational sequence, does it make sense to use footprint symbols. Three functions of schematic: (1) Generate net lists and part lists (2) Explain circuit operation (3) Identify part and pin functions for debug/repair. A quick and dirty schematic often falls short with function 2, and function 3 is impaired much more if circuit operation is not clear than if the tech has to do a little translation of pin locations. If pin locations are not really obvious, why not put a non-electrical diagram on the schematic showing the pinout? Best of both worlds! (Likewise, pin 1 indicators are de rigeur on the PCB, even if you don't have a silkscreen on the board, and if there *is* a silkscreen, adding some pin numbers on large parts can really be a service to a tech) The small overhead in manually swapping the wires for re- assignment is considered worth the effort. Rene -- Ing.Buro R.Tschaggelar http://www.ibrtses.com Your newsgroups @ http://www.talkto.net * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power supply pins
Hello and thank you for your extensive response.
I do apologise for not getting back to you earlier but have been fairly busy.
I think it is generally good practise to always have EVERY pin exposed even power
supply pins but I do feel that putting the power pins off to one side is a neater way
than having as part of a main component symbol. The only problem I have found so far,
and I can't explain why, is that putting the power parts on to a separate page
resulted in Protel wanting to add a complete extra chip to the pcb when I did an
update.
I will study your other comments but am often amazed at how much extra work one has to
do sometimes to achieve a basic feature - not bad for ASU$9000!
Best Regards
Laurie Biddulph
http://www.elby-designs.com
- Original Message -
From: Abd ul-Rahman Lomax
To: Protel EDA Forum
Sent: Friday, December 12, 2003 5:07 AM
Subject: Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital supply. This,
by the way, is a very common error in designs we receive as a service
bureau, and we do try to notice it and query the engineer.)
Problem is Protel 99 doesn't like annotating these as it treats the
power part as a real part and really gets messed up. I believe Protel DXP
lets you assign the power supply pins to Part 0 and so, presumably, gets
round the problem.
I haven't looked into that aspect of DXP yet. The problem in P99 (and
earlier) is only with automatic annotation. I think one could get around
the problem by having two libraries: one would be the components with no
power pins (or with them as part of the main symbols), the other would have
the same parts with power pins removed. The schematic would be drawn, at
first, with the parts from the first library, and annotated. Then the
symbols would all be updated from the second library, and then the power
page would be added to the schematic. There are some caveats with updating
symbols, but I'm a bit rusty on that topic
Beyond that, manually assigning parts is normally not such a huge task. If
there is a way in DXP to exclude a symbol part from the autoannotation
task, this would indeed be an improvement.
But there is usually manual attention needed to annotation, to cluster
logic functions, for example, on the same device so that signals remain
local instead of running across the board and back just to run through an
inverter. I'll often allow a few sections to be unused, more than the
absolute minimum, just to keep signals together. Logic functions are
generally cheap.
Hiding power pins is bad news especially if you use different power rails
from, say, VCC and GND which are the common defaults for logic chips and
so if you forget to unhide them you end up with a power net not going
anywhere near your real power supply.
Protel does not handle this probem as well as DOS Tango did. Tango allowed
sheet-wise net
Re: [PEDA] Power supply pins
are you referring to DXP ?
i don't see this prob in 99SE
the topic of power pins being hidden or not and separate parts for
containing power pins only has been hashed over quite a bit here
my 2 cents FWIW
keep the power pins right on logic BLOCK type symbols
with the rest of the pins
these days with so many different core voltages and possibly
separate isolated voltages of the same magnitude it's just plain
easier to control and see what is going on
rather than having to hunt around for a separate section and
then match up the designator, etc.
as to clutter it hardly matters to me since these chips are becoming
porcupines anyway
the messy exception i make to the above statement is for op amps
and maybe something like a QUAD NAND package which from this perspective
is about like an op amp
it's just so annoying to have the power pins jump around and have to
clear the
space, exp. for the byp caps
i think in this case the argument for a power section (aka 'part') makes
sense
BTW
in my practice i am finding that producing a nice looking
and pretty schematic to be less and less important
i.e., once the whole thing is debugged and in production
i seem to have ever decreasing need to look at the schematic
things are so fast moving that the bd is obsolete or junk
before you need to fix it (or so reliable it never comes up)
if it doesn't work on test get another assembler or
fix the process, there just isn't enough time or margin
to debug troubleshoot at the schematic level
remember when they used to repair carburetors?
now they just bolt a new one on
likewise i seem to be seeing less and less published
schematics which would remove another reason for making
a pretty schematic
obviously others will have different needs and perspectives
and i would like to make perfect looking and clear schematic as
much as the next designer but sometimes a bag of net
labels is enough to get the job done
Dennis Saputelli
Laurie Biddulph wrote:
Hello and thank you for your extensive response.
I do apologise for not getting back to you earlier but have been fairly busy.
I think it is generally good practise to always have EVERY pin exposed even power
supply pins but I do feel that putting the power pins off to one side is a neater
way than having as part of a main component symbol. The only problem I have found so
far, and I can't explain why, is that putting the power parts on to a separate page
resulted in Protel wanting to add a complete extra chip to the pcb when I did an
update.
I will study your other comments but am often amazed at how much extra work one has
to do sometimes to achieve a basic feature - not bad for ASU$9000!
Best Regards
Laurie Biddulph
http://www.elby-designs.com
- Original Message -
From: Abd ul-Rahman Lomax
To: Protel EDA Forum
Sent: Friday, December 12, 2003 5:07 AM
Subject: Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital supply
Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital supply. This,
by the way, is a very common error in designs we receive as a service
bureau, and we do try to notice it and query the engineer.)
Problem is Protel 99 doesn't like annotating these as it treats the
power part as a real part and really gets messed up. I believe Protel DXP
lets you assign the power supply pins to Part 0 and so, presumably, gets
round the problem.
I haven't looked into that aspect of DXP yet. The problem in P99 (and
earlier) is only with automatic annotation. I think one could get around
the problem by having two libraries: one would be the components with no
power pins (or with them as part of the main symbols), the other would have
the same parts with power pins removed. The schematic would be drawn, at
first, with the parts from the first library, and annotated. Then the
symbols would all be updated from the second library, and then the power
page would be added to the schematic. There are some caveats with updating
symbols, but I'm a bit rusty on that topic
Beyond that, manually assigning parts is normally not such a huge task. If
there is a way in DXP to exclude a symbol part from the autoannotation
task, this would indeed be an improvement.
But there is usually manual attention needed to annotation, to cluster
logic functions, for example, on the same device so that signals remain
local instead of running across the board and back just to run through an
inverter. I'll often allow a few sections to be unused, more than the
absolute minimum, just to keep signals together. Logic functions are
generally cheap.
Hiding power pins is bad news especially if you use different power rails
from, say, VCC and GND which are the common defaults for logic chips and
so if you forget to unhide them you end up with a power net not going
anywhere near your real power supply.
Protel does not handle this probem as well as DOS Tango did. Tango allowed
sheet-wise net renaming. So you could place a power object on a sheet and a
short piece of wire with a net name. This would rename one of them to the
other (I forget which was which), allowing you to connect, for example, VCC
to +5V. Whatever was VCC on that sheet, as a power object or hidden power
pin, was reassigned to +5V. This had no effect on other sheets, thus
allowing multiple power supplies with the same hidden pins. It was explicit
and easy to understand.
Is there any recommended method in Protel 99 of handling the power pins on
logic chips similar to my first method above that Protel 99 can handle
comfortably?
Protel has no problem dealing with separate power sections, *except* for
automatic annotation. It is a subset of the larger problem, which is that
automatic annotation is a limited tool and often results in undesired
assignments.
However, I think there might be a way, I don't have time to test it at the
moment. The Annotation tool in 99SE has a number of controls. First, on the
basic page, you can set it to ignore selected parts,
Re: [PEDA] Power supply pins
Get my library here, you should find all you need, all my pins are shown on all the components. http://www.proteluser.com/download/Pcb_99SE_add-on/BriansStuff/ The brians_public.txt describes some of the contents. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Laurie Biddulph [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, December 10, 2003 6:10 AM Subject: [PEDA] Power supply pins I hate having power supply pins as part of schematic component symbols (especially opamps and logic gate chips). I prefer to create an additional `component part' in the chip purely for the power supply pins. This makes it easier to assign decoupling components to the chip as well as reduce clutter in the main part of the schematic. Problem is Protel 99 doesn't like annotating these as it treats the power part as a real part and really gets messed up. I believe Protel DXP lets you assign the power supply pins to Part 0 and so, presumably, gets round the problem. Hiding power pins is bad news especially if you use different power rails from, say, VCC and GND which are the common defaults for logic chips and so if you forget to unhide them you end up with a power net not going anywhere near your real power supply. Is there any recommended method in Protel 99 of handling the power pins on logic chips similar to my first method above that Protel 99 can handle comfortably? Best Regards Laurie Biddulph http://www.elby-designs.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
