Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 08:40 AM 3/14/01 -0800, Brad Velander wrote:
Geoff, Abd-ul Rahman or others following this thread,
 first I am curious about the comments on routing to a single layer
unplated pad. I have single layer unplated pads in most everyone of our
designs and find no problem routing to them, what is your comment based
upon, I just don't see it under my circumstances.

That alleged problem was not my report; I have not experienced it; but I 
have also not used surface pads with holes.

 Secondly there are sometimes valid reasons for single-layer pads w/
unplated holes. In our case we have 'feed-thrus' which pass signals from one
machined cavity in our assembly to another, a board may have up to a dozen
of these which are soldered after placing the PCB in place. They are made
unplated to allow easier de-soldering during assembly, test and servicing of
the units.

This is an application for unplated holes. It is not necessary to use 
surface pads to implement this; one would use padstacks with pad size on 
the other layers smaller than or equal to the hole, and the plated 
attribute unchecked.

By the way, I have done spaceflight design where skewers were used to 
connect boards in a stack. I think there might exist pass-through sockets 
which can be used for this. But they might be soldering them for flight 
boards; the holes were plated-thru.

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Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Brad Velander

David,
The drill is a drill and it has a specified (if only by default)
layer pair regardless of the pad layer specifications. Then Protel tries to
say it is not a valid drill, but only for the drill drawing output where a
close manual check is the only possible manner by which to catch the error
or omission? It is by program operation, valid for all manner of definition,
checks and the Excellon drill file output, but not valid for the drill
symbol drawing. It is obviously an unintended oversight which Protel now
excuse with half-baked excuses and unipolar (CYA) logic. Considering it was
a valid operation in P98, I am surprised that the respondent who replied to
my bug report didn't claim that the bug was actually in P98 but that P99SE
now worked correctly. I am pondering another bug report to report that the
program allows this drill definition, doesn't DRC flag this erroneous drill
and doesn't eliminate it from the Excellon drill file output.

I will change my manner of specifying these pads/holes. I knew that
what I'm doing is not unique, within a short period of time after I found
the problem, two other posters had also stumbled onto the same discovery.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


-Original Message-
From: David W. Gulley [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, March 14, 2001 10:52 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Use Pad Stack

I too use non-plated holes with a pad on a single side, but have always
used the multilayer padstack with no problems (99SEsp5, didn't want to
change horses in mid stream). I just set the internal and top layer
sizes to 0, select non-plated, and set the bottom pad size and hole size
as required.

The only time I would consider using a pad placed on a layer is if that
pad were not to be drilled. (If a pad is placed on the bottom layer with
a drill, then it is no longer a pad on the bottom layer since HOW can a
hole be on the BOTTOM layer?)

Anyway, that's my story and I'm sticking to it!

 
David W. Gulley
Destiny Designs

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Geoff Harland

 At 11:17 AM 3/14/01 +1100, Geoff Harland wrote:

 Out of curiosity, what do you suggest should be done in a situation where
 someone wants an unplated hole through a PCB, and this hole is to pass
 through the middle of a pad on the bottom (copper) layer?

 Before making a suggestion, I would preferably want to know *why* the user
 wanted such a feature. It might affect the answer.

 But let me imagine one. One needs to solder a wire or part to the board
 and needs the hole to mount the part, but other constraints, perhaps very
 tight trace density in the area, only allows a minimal hole to be placed
 in the area, and there is no room for a pad on any other layer than, say,
 the bottom.

I did describe a scenario myself, further on in my previous post, in which
the designer might want such a feature. This scenario concerned the pads
used in a footprint for a through-hole crystal, where pads on the top side
of the PCB (were these to be provided) could short with the body of the
crystal, or at least if these were of the same diameter as the pads on the
bottom side of the PCB. (I also said that I use plated pads on the
MultiLayer layer myself, and use the padstacks feature so that the pads on
the top side of the PCB are much smaller in diameter then the pads on the
bottom side (and middle layers) of the PCB.)

 First of all, it should be noted that such a structure could be quite
 weak. This is effectively a single-sided PCB, as far as that part is
 concerned, and pad sizes for single-side PCBs are typically made quite a
 bit larger in order to provide better adhesion of the pad to the board.
 Even then, failure rates where there is any stress on the lead at all will
 be very high. I've  had a number of consumer audio products fail because
 the adhesive did not hold and ultimately the pad or the track attaching to
 the pad (more likely) cracked. Clinched leads can help, but if there is
 room for a clinched lead there is probably room for a pad. It is not the
 plating that is so important, but having a pad/solder fillet on both
 sides, which, with the lead itself, makes a rivet that is not easily
 dislodged.

The observation that the presense of a pad/solder fillet on both sides of
the PCB makes a rivet of robust nature is very pertinent in the
circumstances. It definitely vindicates my usage of plated through pads that
use the padstack feature (over the alternative option of using bottom side
only pads with unplated holes).

Other things being equal, plated-through pads should be used in preference
to single layer pads with unplated holes; the former are more reliable for
the reason described. But my experience with de-soldering through-hole
components from PCBs using plated-through multilayer pads indicates that the
superiority of this type of pad is not unconditional. (That is an
observation rather than an attempt to advocate that single layer unplated
pads be used instead. If you have the right equipment, and keep it in proper
order, de-soldering such components is less of a hassle than is otherwise
the case.)

 Having said that it is probably foolish, I would then go ahead and suggest
 there are a number of ways to accomplish the matter. Putting a hole in an
 SMT pad, as I recall, can confuse Protel in a number of ways, I'm not sure
 it works. Obviously, one might use a padstack and define the pad as
 non-plated, but there are complications with that as well.

 I'd be tempted to place a surface pad and an additional pad in the same
 location which would be through-hole, nonplated. I'm not sure what pad
 size I would use. Zero is too small; it is tempting to make the pad size
 the same size as the hole, but this has a reputation of generating little
 slivers of copper, not from the hole drilling, since the holes are
 generally drilled first, before any pattern has been established, but from
 misregister between the hole and the film. Perhaps it might be better to
 make the pad 5 mils smaller than the hole (10 mils diametric). With
 appropriate clearance rules it would serve as a routing obstacle. Because
 the hole is non-plated, it could come very close to a track without harm,
 perhaps as close as a mil or two, I don't know how close I would want to
 push it.

I concur that this method should work, but my sentiment is that it should
not be necessary to have to use two pads; I would prefer that I could
configure just *one* pad as required.

 Or one could use a single padstack with pads defined in a similar way.

If the pad's plated property is set false, I think that there would be
problems with routing to it. And if its plated property is set true instead,
you would have a plated through hole which would have no copper surrounding
it on the internal and top layers. That would be undesirable (as the rivet
aspect of a multilayer pad would be lost, amongst other things). Of course,
if the hole is surrounded by a minimal amount of copper on those layers,
then you would have a multilayer pad using the 

Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

It's important to realize that CAD programs may be thoroughly checked for 
bugs, but when they hit the real world, they may be fed data that was not 
anticipated and therefore the behavior of the program has not been tested.

Further, whenever we attempt to do something non-standard, we are not only 
entering an area which may not have been anticipated in testing or explored 
even in beta-test, but we may also have expectations regarding the behavior 
of the program that are personal and not necessary what everyone would expect.

In this case, remember that surface pads were conceived as surfaces for 
mounting SMT components. Conceptually, they don't have holes, period. 
Probably the dialog box should suppress the hole attribute when the pad is 
assigned to top or bottom. In my opinion, that is the real oversight, that 
such holes are allowed at all.

Otherwise, if a pad has a hole, it is a through hole: i.e., it's a hole 
through the board. That's exactly what multilayer pads are, if they have holes.

If one wants to put a via in a surface pad, then put a via or free pad in a 
surface pad!

Some of us want the program to have more flexibility and some of us want 
the program to be more secure, foolproof. I don't think that both criteria 
are easy to maximize at the same time.

It is probably more often an error than not that a hole exists in a surface 
pad. It's easy to do: one is making a footprint, and places a pad, and 
because the last pad placed was a through pad, one changes the layer to the 
surface and forgets to remove the hole. Depending on display settings, this 
may not be obvious.

Since everything desireable about surface pads with holes can be attained 
with padstacks (or alternatively with pad combinations), I'd vote for 
locking out holes in surface pads. Existing designs would still allow such 
primitives, that's necessary for legacy designs, but it would become 
impossible to create them through the normal interface. (If a pad already 
had a hole, it should still be possible to edit the hole size. There would 
thus be a workaround if someone really finds a necessity for surface pads 
with holes in their center.)

(Note that we'd love to put vias in pads for bypass capacitors, so that the 
loop area would be minimized. But the ideal location for such a via would 
not be the pad center, but would be shifted toward the cap centroid. In 
fact, the ideal location might not be in the pad at all, but underneath the 
part even farther toward the centroid. Note that this is not a license for 
via-in-pad, which can create serious assembly problems!)
[EMAIL PROTECTED]
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P.O. Box 690
El Verano, CA 95433

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread David W. Gulley

N-Luo/Yu-Ming (   INC) wrote:
 I try to use the pads on multilayer using pad stack. I set the top and
 middle layer pad to 0, and set the hole as a NPTH, But when I chech the
 gerber file, I noticed a round flash with 8mil diameter on the top solder
 mask layer. How to solve that?

and subsequently wrote:

 I get it. I use the default sloder mask expansion setting 4 mil, 
 To move the unwanted solder mask on the top solder mask layer, 
 I should set the top pad to -8 mil but not 0 mil.

You did not specify if you were actually going to drill the pad. It
seems to me that you may be trying to define a bottom layer pad (since
the multilayer and top are both 0) with drill size 0 (since you want top
solder mask set to 0). If this is the case, change the layer of the pad
in the properties tab to bottom, and the internal layer and top layer
features are removed. 


David W. Gulley
Destiny Designs

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 11:17 AM 3/14/01 +1100, Geoff Harland wrote:

Out of curiosity, what do you suggest should be done in a situation where
someone wants an unplated hole through a PCB, and this hole is to pass
through the middle of a pad on the bottom (copper) layer?

Before making a suggestion, I would preferably want to know *why* the user 
wanted such a feature. It might affect the answer.

But let me imagine one. One needs to solder a wire or part to the board and 
needs the hole to mount the part, but other constraints, perhaps very tight 
trace density in the area, only allows a minimal hole to be placed in the 
area, and there is no room for a pad on any other layer than, say, the bottom.

First of all, it should be noted that such a structure could be quite weak. 
This is effectively a single-sided PCB, as far as that part is concerned, 
and pad sizes for single-side PCBs are typically made quite a bit larger in 
order to provide better adhesion of the pad to the board. Even then, 
failure rates where there is any stress on the lead at all will be very 
high. I've  had a number of consumer audio products fail because the 
adhesive did not hold and ultimately the pad or the track attaching to the 
pad (more likely) cracked. Clinched leads can help, but if there is room 
for a clinched lead there is probably room for a pad. It is not the plating 
that is so important, but having a pad/solder fillet on both sides, which, 
with the lead itself, makes a rivet that is not easily dislodged.

Having said that it is probably foolish, I would then go ahead and suggest 
there are a number of ways to accomplish the matter. Putting a hole in an 
SMT pad, as I recall, can confuse Protel in a number of ways, I'm not sure 
it works. Obviously, one might use a padstack and define the pad as 
non-plated, but there are complications with that as well.

I'd be tempted to place a surface pad and an additional pad in the same 
location which would be through-hole, nonplated. I'm not sure what pad size 
I would use. Zero is too small; it is tempting to make the pad size the 
same size as the hole, but this has a reputation of generating little 
slivers of copper, not from the hole drilling, since the holes are 
generally drilled first, before any pattern has been established, but from 
misregister between the hole and the film. Perhaps it might be better to 
make the pad 5 mils smaller than the hole (10 mils diametric). With 
appropriate clearance rules it would serve as a routing obstacle. Because 
the hole is non-plated, it could come very close to a track without harm, 
perhaps as close as a mil or two, I don't know how close I would want to 
push it.

Or one could use a single padstack with pads defined in a similar way.

My understanding is that whenever a hole in a PCB *is* through-plated, then
it is always advisable to have a minimal width of copper surrounding the
hole on each copper layer. As an example, if there should be at least 5mil
of copper surrounding each hole, and a hole's diameter is 20mil, then the
minimum width and height of the associated pad on any layer (Top, Bottom, or
(intermediate) Middle) is 30mil (allowing 20mil for the hole and 5mil on
*each* side of this).

To put this in perspective, you will have 1.4 mils of copper on the wall, 
so, effectively, with a plated through hole, you have a minimum pad size 3 
mils diametric larger than the hole. Considering drill tolerance and hole 
position tolerance, 5 mils radial is about as small as one would want to go.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433


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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Geoff Harland

snip
 As was noted already, it sounds like Luo wants a bottom pad with nothing
 on the other layers. To accomplish this, simply set the pad attribute to
 Bottom. There will then be no pad or soldermask geometry on any other
 layer, assuming that the hole size is zero; and I do not recommend setting
 a non-zero hole size with a surface pad (Top or Bottom). Pad stacks are
 not appropriate for this kind of application.

 Abdulrahman Lomax

Out of curiosity, what do you suggest should be done in a situation where
someone wants an unplated hole through a PCB, and this hole is to pass
through the middle of a pad on the bottom (copper) layer?

My understanding is that whenever a hole in a PCB *is* through-plated, then
it is always advisable to have a minimal width of copper surrounding the
hole on each copper layer. As an example, if there should be at least 5mil
of copper surrounding each hole, and a hole's diameter is 20mil, then the
minimum width and height of the associated pad on any layer (Top, Bottom, or
(intermediate) Middle) is 30mil (allowing 20mil for the hole and 5mil on
*each* side of this).

If you do not want *any* copper surrounding a hole on any layer except for
the bottom layer (or in the case of a through-hole component mounted on the
*bottom* side of a PCB, you do not want any copper surrounding a hole on any
layer except for the top layer), then that suggests that you should set the
pad's Layer (property) to Bottom (signal/copper) (or to Top (signal/copper)
if the associated component is fitted on the PCB's bottom side instead), and
the pad's plated property should be set false.

However, I seem to recall past discussions on this forum in which it was
claimed that tracks can not be wired to unplated pads. I haven't checked
that aspect recently, but I seem to recall that unplated pads could not be
wired to in at least some circumstances.

I do not use such types of pads myself. Ideally, all holes in a PCB should
be plated through, as it costs more to use a mix of plated through holes and
unplated holes. That said, many of the PCBs which I design *do* use a mix of
hole types. However, *all* unplated holes within these PCBs are holes only;
they are *not* surrounded by copper on *any* layer, including *both*
external copper layers.

If I am using a device like a through-hole crystal, where large pads on the
top copper layer could short with the body of the crystal, I use the
padstacks feature with *plated* holes. The pads on the internal (Middle) and
bottom layers are meaty, but I set the pads on the top layer to be as
skimpy as possible. (The associated pads are on the MultiLayer layer.)

However, some users might prefer to totally forsake pads on the top layer
*and* internal layers, and use pads *solely* on the bottom layer. In such
cases, the associated holes should not be plated through. In other words,
each pad is on the bottom copper layer, with a hole of non-zero diameter,
and the pad/hole is not plated.

Can this be regarded as a shortcoming of Protel?

I'd like to talk more about pads (e.g. should the padstacks feature be
disabled *unless* the pad is on the MultiLayer layer?; should the padstacks
feature be enhanced in certain ways?; how should totally copper-less holes
be handled?; and others), but I have other things to do at this stage. But
others are welcome and even invited to comment on such matters.

Regards,
Geoff Harland.
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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Ian Wilson

We seem to be locking horns today ;-)

On 05:58 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said:

It's important to realize that CAD programs may be thoroughly checked for 
bugs, but when they hit the real world, they may be fed data that was not 
anticipated and therefore the behavior of the program has not been tested.

Abd ul-Rahman, I have a problem with the manner in which you are expressing 
things in your post?

Are you saying it is OK to introduce a bug in a new version of software 
that did not exist in a previous version?

There is a bug.  Drill file does not match Drill Drawing = BUG.

Protel allows holes in surface pads *but* doesn't mark those holes in the 
Drill Drawing.  The program does however recognise that a hole should be 
drilled there (it is in the drill file).  So there is a bug.  Drill file 
does not match drill drawing = BUG.  No excuses or discussions on this, 
surely.  This bug did not exist in previous versions of PCB so the argument 
about real-world data is a bit facetious - I think that after all this time 
Protel could reasonably have realised that non-zero sm holes were used in 
the field.  If they wish to change this then making the drill files 
erroneous is hardly a sensible method.

You are broadening the subject to now include your opinion on how it should 
be fixed, which is great. However, I have found that some of your 
discussion on the matter seems to be clouding the issue that there is a 
bug. I think you should clearly accept the bug and then clearly move on to 
express your opinion in how to fix it - not mix the two aspects to the 
discussion.

I think:
1) Protel should make sure the drill drawing and the drill file match, 
exactly.  I would consider doing this by generating the drill file 
internally and using the results to make the drill drawing.  The same 
process would be used for both then - no code synchronisation issues at all.

2) Protel should consult on what, if anything, should be done about 
continuing to allow/not allow non-zero hole sizes to be entered.

In order not to break existing designs Protel *must* maintain support for 
non-zero hole sizes in surface pads but there could be appropriate DRC 
warnings.  New versions of the software could prevent accidental entry of 
non-zero hole sizes in surface pads by, as you say, greying out the hole 
size edit box, in the Change Pad dialog, if the layer is not multilayer.

Ian Wilson

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 03:42 PM 3/15/01 +1100, Ian Wilson wrote:
We seem to be locking horns today ;-)

If one does not lock horns every so often, they become ingrown. :-)

On 05:58 PM 14/03/2001 -0800, Abd ul-Rahman Lomax said:

It's important to realize that CAD programs may be thoroughly checked for 
bugs, but when they hit the real world, they may be fed data that was not 
anticipated and therefore the behavior of the program has not been tested.

Abd ul-Rahman, I have a problem with the manner in which you are 
expressing things in your post?

Are you saying it is OK to introduce a bug in a new version of software 
that did not exist in a previous version?

I don't think I said that. But I do say that when one introduces new 
features to a program, it goes with the territory that bugs may be created 
that did not exist before; or program behavior may change in a way that is 
not technically a bug but which might as well be if one was relying on an 
undocumented feature.


There is a bug.  Drill file does not match Drill Drawing = BUG.

Definitely. I don't know why Mr. Wilson would think I would not agree with him.

My point is that if one is using a program in a non-standard way, the 
probability of running into a bug is greatly increased. It's reality, and I 
don't think that it will change in the next hundred years.

Protel allows holes in surface pads *but* doesn't mark those holes in the 
Drill Drawing.  The program does however recognise that a hole should be 
drilled there (it is in the drill file).  So there is a bug.  Drill file 
does not match drill drawing = BUG.  No excuses or discussions on this, surely.

I prefer to look for causes and remedies than to try to assign blame. 
Excuses imply an assignment of blame. Essentially, some programmer failed 
to anticipate every consequence of what was being done, and someone testing 
the software failed to test a particular aspect of its operation.

I can't do *anything* about either of these factors. But I *can* do 
something about how I use a program and what I expect of it. If I am doing 
something which pushes the envelope, it behooves me to very carefully check 
my output. What I have said is that a surface pad with a hole is pushing 
the envelope. It's a rare beast and thus has seen little testing.

   This bug did not exist in previous versions of PCB so the argument 
 about real-world data is a bit facetious - I think that after all this 
 time Protel could reasonably have realised that non-zero sm holes were 
 used in the field.  If they wish to change this then making the drill 
 files erroneous is hardly a sensible method.

How then, was the bug created? Mr. Wilson, does any one of us think that a 
Protel software engineer *wanted* to make the program behave as he has 
described? If he did, and if it were discovered that he did, I assume that 
he would be out of a job. No, I think that no one even dreamed that this 
bug would be introduced. And we did not discover it in beta test, I 
suspect, though I'm not certain about that.

I think:
1) Protel should make sure the drill drawing and the drill file match, 
exactly.  I would consider doing this by generating the drill file 
internally and using the results to make the drill drawing.  The same 
process would be used for both then - no code synchronisation issues at all.

Good idea. Good ideas are common in hindsight.

2) Protel should consult on what, if anything, should be done about 
continuing to allow/not allow non-zero hole sizes to be entered.

Certainly we agree on that. I give my opinion, and I hope that others give 
their experience, insights and opinions; Protel should value discussion 
that bring out the various ways that users will use the programs and what 
ideas they have for improving it. We will differ, often. It is Protel's job 
to decide which way will be best, though we might assist them in certain 
ways where we can come to some kind of consensus.

In order not to break existing designs Protel *must* maintain support for 
non-zero hole sizes in surface pads but there could be appropriate DRC 
warnings.  New versions of the software could prevent accidental entry of 
non-zero hole sizes in surface pads by, as you say, greying out the hole 
size edit box, in the Change Pad dialog, if the layer is not multilayer.

I do think that we agree on the solution. If a surface pad has a zero hole, 
grey out the hole size edit box so that one may not make it non-zero. If 
one edits a multilayer pad to surface, set the hole size to zero 
immediately. It might be courteous to give a message that this has been 
done. However, if a surface pad exists that has a non-zero hole, allow it 
to remain and also allow copying and editing of the hole size until and 
unless it has been set at zero.
And fix the drill drawing/drill file routines.

If all this is done, there would be the occasional user who would run 
headlong into a brick wall and then complain that we put the wall there. We 
would then inform this 

Re: [PEDA] Use Pad Stack

2001-05-07 Thread Simon

set the solder mask expansion for the pad in the design rules..  (or set the
'tent' option)
I prefer to set a rule to allow 10-20 mil larger solder mask on NPTH pads
with no copper to stop solder mask running down the hole (if its a liquid)

Simon

-Original Message-
From: N-Luo/Yu-Ming (   INC) [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 13 March 2001 16:47
To: Protel EDA Forum
Subject: [PEDA] Use Pad Stack


Dear all,

I try to use the pads on multilayer using pad stack. I set the top and
middle layer pad to 0, and set the hole as a NPTH, But when I chech the
gerber file, I noticed a round flash with 8mil diameter on the top solder
mask layer. How to solve that?

Thanks.

Luo.


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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Bruce admin

Hi Abdulrahman,
 
I read your email and thought I would throw in my two cents worth.  The following 
comments are meant more for educational purposes, and not to flame your email.  The 
technology in our field is rapidly changing, and we need to help each other keep 
abreast of these changes.  After all, isn't that what this forum is all about?  
Anyhow, read on..

-Original Message-
From: [EMAIL PROTECTED] 
Sent: Wednesday, March 14, 2001 7:44 PM
To: Protel EDA Forum [EMAIL PROTECTED]
Subject: Re: [PEDA] Use Pad Stack



It's important to realize that CAD programs may be thoroughly checked for 
bugs, but when they hit the real world, they may be fed data that was not 
anticipated and therefore the behavior of the program has not been tested. 

Further, whenever we attempt to do something non standard, we are not only 
entering an area which may not have been anticipated in testing or explored 
even in beta test, but we may also have expectations regarding the behavior 
of the program that are personal and not necessary what everyone would expect. 

In this case, remember that surface pads were conceived as surfaces for 
mounting SMT components. Conceptually, they don't have holes, period. 
Probably the dialog box should suppress the hole attribute when the pad is 
assigned to top or bottom. In my opinion, that is the real oversight, that 
such holes are allowed at all. 
 
[Bruce:] This will create problems for people trying to do HDI designs.  This is the 
wave of the future with respect to SMD layouts that need to be compressed into smaller 
spaces (better than 50% space savings with HDI over conventional SMT designs).   Many 
Japanese designs have been using HDI for some time now.  I suggest that you read up on 
this topic to gain some insight into where the technology is heading.

Otherwise, if a pad has a hole, it is a through hole: i.e., it's a hole 
through the board. That's exactly what multilayer pads are, if they have holes. 
 
[Bruce:] Not quite true anymore...  HDI requires a laser drilled hole, often only the 
first two layers (incredibly small by the way 0.003 to 0.010).  This is essentially 
a blind via, but should be defined as part of the pad as all interconnects to the 
surface mount pad will be made through these micro vias.  Another issue is raised with 
this technology though  It is important for some of the emerging technology to 
have a window on the surface mount pad for the laser to burn through the outer 
layers (otherwise the laser beam is reflected, etc.).  As far as I know, it isn't 
possible yet to define this copperless window in Protel yet. 

If one wants to put a via in a surface pad, then put a via or free pad in a 
surface pad! 
 
[Bruce:]  Not really an option for HDI.  How difficult do you think it would be to 
make the placement of those HDI micro vias on a fine pitched board?  I suppose it 
would work, but personally I would rather define that in the decal library.

Some of us want the program to have more flexibility and some of us want 
the program to be more secure, foolproof. I don't think that both criteria 
are easy to maximize at the same time. 

It is probably more often an error than not that a hole exists in a surface 
pad. It's easy to do: one is making a footprint, and places a pad, and 
because the last pad placed was a through pad, one changes the layer to the 
surface and forgets to remove the hole. Depending on display settings, this 
may not be obvious. 

Since everything desireable about surface pads with holes can be attained 
with padstacks (or alternatively with pad combinations), I'd vote for 
locking out holes in surface pads. Existing designs would still allow such 
primitives, that's necessary for legacy designs, but it would become 
impossible to create them through the normal interface. (If a pad already 
had a hole, it should still be possible to edit the hole size. There would 
thus be a workaround if someone really finds a necessity for surface pads 
with holes in their center.) 

(Note that we'd love to put vias in pads for bypass capacitors, so that the 
loop area would be minimized. But the ideal location for such a via would 
not be the pad center, but would be shifted toward the cap centroid. In 
fact, the ideal location might not be in the pad at all, but underneath the 
part even farther toward the centroid. Note that this is not a license for 
via in pad, which can create serious assembly problems!) 
 
[Bruce:]  Assembly problems are eliminated in HDI (I'm assuming you are referring to 
the solder paste drain problem) because the holes are so small that the surface 
tension will hold the solder on the SMD pad (rather than flowing through the micro 
via). This is well tested and proven in Japan (you know how important quality is to 
the Japanese).


[Bruce:] Anyone interested in HDI can send me an email and I would be happy

Re: [PEDA] Use Pad Stack

2001-05-07 Thread Brad Velander

Thank you Ian,
for clarifying my point in such a concise manner. I probably didn't
express my issue as clearly as you have below because I was responding to
other peoples comments rather then trying to clearly stating my beef with
the issue. You have hit the mark.

Protel's comments to me indicate that they do not consider the
problem a bug when it clearly is a bug. It is a bug because they are
generating output files and data which does not synch. The Gerber or printed
drill symbol file shows no symbol for a drill which clearly exists in the
ASCII drill file.

I don't care how Protel fix it, I will fix our databases in an
appropriate manner. One fix would mean that I have no work, the present fix
means that I have to change all of our existing designs as necessary. Protel
can fix it to increase the integrity of their software and to keep other's
from experiencing the same difficulty. They can not fix it and allow others
to forever fall into this pitfall in the future, their choice.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, March 14, 2001 8:43 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Use Pad Stack


SNIP

I think:
1) Protel should make sure the drill drawing and the drill file match, 
exactly.  
SNIP
In order not to break existing designs Protel *must* maintain support for 
non-zero hole sizes in surface pads but there could be appropriate DRC 
warnings.  New versions of the software could prevent accidental entry of 
non-zero hole sizes in surface pads by, as you say, greying out the hole 
size edit box, in the Change Pad dialog, if the layer is not multilayer.

Ian Wilson

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Brad Velander

Abd-ul Rahman,
see my comments below.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


 -Original Message-
 From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
 Sent: Wednesday, March 14, 2001 11:12 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Use Pad Stack
 
 I can't do *anything* about either of these factors. But I *can* do 
 something about how I use a program and what I expect of it. 
 If I am doing 
 something which pushes the envelope, it behooves me to very 
 carefully check 
 my output. What I have said is that a surface pad with a hole 
 is pushing 
 the envelope. It's a rare beast and thus has seen little testing.

Abd-ul Rahman how can you define a single layer pad with a hole as
pushing the envelope? I have used this type of design in at least three CAD
packages over the years and extensively in P98, all successfully. So where
is it defined that this is pushing any envelope? With each and every CAD
package there are operations which are not clearly and defined as do-able or
not do-able. We all know there are 101+ things to do with a dead cat. So we
try them, if they work they are do-able, if they don't work they are not
do-able. P98 it was do-able, P99SE it is not do-able, but it also generates
flaky output data so it is a P99SE bug.

 How then, was the bug created? Mr. Wilson, does any one of us 
 think that a 
 Protel software engineer *wanted* to make the program behave 
 as he has 
 described? If he did, and if it were discovered that he did, 
 I assume that 
 he would be out of a job. No, I think that no one even 
 dreamed that this 
 bug would be introduced. And we did not discover it in beta test, I 
 suspect, though I'm not certain about that.

I don't think that this bug was introduced intentionally, not at
all. However the response that I got, supposedly forwarded from a
development team member, was ludicrous. It simply stated that this was not a
bug because single-layer pads should not have a drill or else they are not
single layer pads. If the use of a through hole in a surface mount pad is to
not be allowed from P99 forward then there is still a bug because the output
data does not synch.
There are so many bugs (or if you like, programming oversights) in
Protel that you can drive a semi-trailer through. And the type of response
that I got demonstrates why these bugs exist. The development team members
do not take responsibility for their code and Protel does not take full
earnest responsibility for their product.

For example: Why does Protel allow component footprint names which
exceed their stated name length or contain illegal characters. Then when you
use a name with illegal or excessive characters the program fails during
some mundane operation. Not only that but they do not inform you of these
illegal characters and only state the name limitation on one page of the
documentation in a very obscure area, no where near the library editing or
part creation areas.

I have been around long enough and have even lead product
development teams for a few years, one of the first rules in software
development is that if you have specified limitations on input then you code
these limitations in your program code, no exceptions. This will eliminate
countless other bugs and operational quirks down the road that can take 10
times as much effort to isolate and fix then simply limiting input during
the input process.

For example: I am a new user trying to create a new footprint. I try
to use an illegal character (space for this example), the program will not
accept this character. Even if I have never read the manual (which didn't
state anything anyways) what do I do? I either assume it won't accept that
character or a quick call to Protel confirms the illegal character. As it
stands now, I get no initial error and carry on my merry way possibly for
days or weeks. Then at some juncture I need to modify and update that
footprint from the library, it doesn't update properly to the PCB. What are
the various complexities involved to now discover the root of my problem?
Repeat this scenario for all the possible illegal characters (I don't think
that anybody knows which are all the illegal characters) and then throw in
as well names that exceed the specified 12 character limit (is this even
valid any longer? Has this been increased recently without changing the
manual?). All of these possible problem scenarios just because some
programmer didn't properly limit their input options for one field of user
entry. Pretty sad.

SNIP
 
 [EMAIL PROTECTED]
 Abdulrahman Lomax
 P.O. Box 690
 El Verano, CA 95433
 
 

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 09:18 AM 3/15/01 -0800, Brad Velander wrote:

 Abd-ul Rahman how can you define a single layer pad with a hole as
pushing the envelope? I have used this type of design in at least three CAD
packages over the years and extensively in P98, all successfully. So where
is it defined that this is pushing any envelope?

What I am saying is that defining a surface pad, an entity which in its 
conception was without a hole, as having a hole, is pushing into a 
territory that may not have been as thoroughly tested and debugged as might 
a more normal entity.

Using a multilayer pad to accomplish the same thing would be much safer.

The issue is not the PCB structure, but how one uses the program to produce 
that structure.

  With each and every CAD
package there are operations which are not clearly and defined as do-able or
not do-able. We all know there are 101+ things to do with a dead cat. So we
try them, if they work they are do-able, if they don't work they are not
do-able. P98 it was do-able, P99SE it is not do-able, but it also generates
flaky output data so it is a P99SE bug.

First of all, I'd remind Mr. Velander that the use of undocumented features 
of a program is subject to exactly this hazard: the next version might not 
support it. That risk exists with *documented* features, but the risk is 
much higher when the feature is one that is not anticipated by the 
programmers. That really ought to be obvious.

There is a bug here, definitely. No way should the drill drawing fail to 
match the drill file. It should be impossible to create a PCB that would do 
that. That such an error exists shows a certain weakness in the program 
conception; apparently what should be the same process, at least in the 
first steps, has been implemented in two different ways. That is sloppy 
programming, for sure. But in a software project the size of Protel 99SE, 
there is bound to be some sloppy programming. One could spend ten times 
what Protel spends on programming and still have some problems like this.

[...]
 I don't think that this bug was introduced intentionally, not at
all. However the response that I got, supposedly forwarded from a
development team member, was ludicrous. It simply stated that this was not a
bug because single-layer pads should not have a drill or else they are not
single layer pads. If the use of a through hole in a surface mount pad is to
not be allowed from P99 forward then there is still a bug because the output
data does not synch.

Right. But Mr. Velander is focusing on a misstatement by a Protel 
development team member. It was not ludicrous, however, it was  merely 
short-sighted or incomplete as a response. That the program might not 
support SMT pads with holes is not a bug. That it allows such primitives 
and then does not process them correctly is a bug. He was addressing the 
first issue, not the second.

 There are so many bugs (or if you like, programming oversights) in
Protel that you can drive a semi-trailer through. And the type of response
that I got demonstrates why these bugs exist. The development team members
do not take responsibility for their code and Protel does not take full
earnest responsibility for their product.

As one might imagine, I have a different view of this. It is not that what 
Mr. Velander is saying is false; but rather it is, in my view, misdirected. 
We all make mistakes, and there is no existing software company that takes 
full earnest responsibility for their product. Or if there is, it will not 
last long.

I would also note that Protel does not openly reveal its internal 
processes, and one cannot judge those processes by a comment from member of 
a development team. For all we know, that person is no longer at Protel. Or 
perhaps he is still there because he is a better programmer than he is a 
customer relations person. There are reasons for Protel's secrecy; 
historically, things were worse. In any case, what the programmer (assuming 
that a member of a development team is a programmer) wrote was, within 
its limits, not incorrect. It was merely incomplete, as I noted.

 For example: Why does Protel allow component footprint names which
exceed their stated name length or contain illegal characters. Then when you
use a name with illegal or excessive characters the program fails during
some mundane operation. Not only that but they do not inform you of these
illegal characters and only state the name limitation on one page of the
documentation in a very obscure area, no where near the library editing or
part creation areas.

These too are bugs and documentation shortcomings. They should be fixed. It 
should be *impossible* to enter illegal data into a field. I think we all 
agree on that. Let's focus on fixing the problems, rather than on trying to 
blame the programmers who did a good, if incomplete, job **overall**. Do we 
think that metaphorically yelling at the programmers is going to get the 
problems 

Re: [PEDA] Use Pad Stack

2001-05-07 Thread Brad Velander

Abd-ul Rahman,
Not that it warrants arguing over but you and I just have different
views. You say a single layer pad is a SMT pad. I say a single layer pad is
the most ancient of all pads and originally in it's concept had a drill even
though it is a single layer pad, it was a single sided PCB design the
predecessor of all else. You can call a single-layer pad SMT all you want
but you won't convince me because the single layer pad predated both of our
births, long before SMT was even a glint in anyone's eyes.
On your note about undocumented features you are leaving yourself a
little open there consider Protel's lacking documentation. A lot of what we
all do day in and day out is undocumented or it is just mentioned without
further explanation or qualification of the limitations.

Have a good evening, I am sure we will talk tomorrow.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com



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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Frank Gilley

All,

Here's another example for non-plated pads on one layer...  RF Coax 
launches.  We typically have a grounded pad on the top to solder the 
shield(s) to, and a non-plated hole leading through the board to a pad in 
the output microstrip on the bottom.  We pull back the shield, poke the 
center conductor with insulator through the board and solder the center 
conductor on the bottom there.  This radiates far less than having the 
hotline come up through the board with a nice radiating ring on the 
top.  Seems to match better too.  To do this, we simply use a multi-layer 
pad with  the top and center set to 0,0 and the bottom set to the desired 
pad size, with the appropriate hole.
Like Brad sez, simply using a bottom layer pad will *not* get you a drill 
symbol.

-Frank

At 12:52 PM 3/14/2001 -0600, David W. Gully wrote:
Brad Velander wrote:
  The only shortcoming that I know of in Protel with the use of these
  pads shows up in P99SE where some rocket-scientist at Protel decided that a
  single-sided (non-padstack) un-plated or plated hole is not a valid drill
  point and shouldn't be included in the drill drawing symbol generation. 
 This
  had worked in previous versions until P99 or P99SE. I have to experiment
  over the next few days and see if I can adequately accomplish all my needs
  with a multi-layer padstack and still get a drill symbol. I can't 
 understand
  why someone at Protel would decide that a drill is not a drill and so not
  generate a symbol.
  During the interim I have had to temporarily change these pads to
  multi-layer while generating the drill drawing, yuck, I hate doing these
  sort of things. If we forget to change them back we have many other errors
  which may pop up in the next set of edits to the design.

I too use non-plated holes with a pad on a single side, but have always
used the multilayer padstack with no problems (99SEsp5, didn't want to
change horses in mid stream). I just set the internal and top layer
sizes to 0, select non-plated, and set the bottom pad size and hole size
as required.

The only time I would consider using a pad placed on a layer is if that
pad were not to be drilled. (If a pad is placed on the bottom layer with
a drill, then it is no longer a pad on the bottom layer since HOW can a
hole be on the BOTTOM layer?)

Anyway, that's my story and I'm sticking to it!


David W. Gulley
Destiny Designs

Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 08:43 AM 3/15/01 -0700, Bruce admin wrote:

I read your email and thought I would throw in my two cents worth.  The 
following comments are meant more for educational purposes, and not to 
flame your email.  The technology in our field is rapidly changing, and we 
need to help each other keep abreast of these changes.  After all, isn't 
that what this forum is all about?  Anyhow, read on..

Of course, if we always agreed -- at the outset -- there would be no need 
for discussion. Disagreements, if we approach them properly, cause us to 
expose the underpinnings of our opinions.

 In this case, remember that surface pads were conceived as 
surfaces for
mounting SMT components. Conceptually, they don't have holes, period.
Probably the dialog box should suppress the hole attribute when the pad is
assigned to top or bottom. In my opinion, that is the real oversight, that
such holes are allowed at all.

[Bruce:] This will create problems for people trying to do HDI 
designs.  This is the wave of the future with respect to SMD layouts that 
need to be compressed into smaller spaces (better than 50% space savings 
with HDI over conventional SMT designs).   Many Japanese designs have been 
using HDI for some time now.  I suggest that you read up on this topic to 
gain some insight into where the technology is heading.

Remember, I am *not* talking about the physical structures on the board, 
but about how they are represented in a database. *Of course* we need to 
have pads with holes. But a surface pad is a pad designed for mounting a 
surface mount component; and it has a few other innocuous uses as well. But 
the structure created for representing a pad with a hole is called a 
Multilayer Pad. It is called multilayer because the hole means that it 
has a presence on more than one layer. If there is a hole, it is either a 
multilayer pad, or it is a via.

Now, as Bruce quite correctly points out, there are features, particularly 
BGAs, which might require a surface mounting pad with a hole in the center. 
The database was not designed with these features in mind, so we need to be 
careful how we implement them. Because we want solder paste on these pads, 
we must use a surface pad (or deal with custom shapes on the paste mask 
layer in the footprint, another option). Then we need a hole, typically a 
blind via. Protel does not have any entity called a blind pad or which 
functions like that except for blind vias. So there is really no choice: a 
via must be used for the interlayer hole.

 Otherwise, if a pad has a hole, it is a through hole: i.e., it's 
 a hole
through the board. That's exactly what multilayer pads are, if they have 
holes.

[Bruce:] Not quite true anymore...  HDI requires a laser drilled hole, 
often only the first two layers (incredibly small by the way 0.003 to 
0.010).  This is essentially a blind via, but should be defined as part 
of the pad as all interconnects to the surface mount pad will be made 
through these micro vias.

One might like to define such a hole as part of the pad, but that isn't in 
the guide book! But one could put blind vias in the footprint. I'm not 
certain what the autorouter will do with them, however. If it leaves them 
in and routes to them, we are home free. Otherwise, we got trouble in River 
City.

   Another issue is raised with this technology though  It is 
 important for some of the emerging technology to have a window on the 
 surface mount pad for the laser to burn through the outer layers 
 (otherwise the laser beam is reflected, etc.).  As far as I know, it 
 isn't possible yet to define this copperless window in Protel yet.

Of course it is possible. In the footprint, place a round feature (I'll get 
to that in a moment) at the position of the hole on one of our shiny new 
mechanical layers, which will be dedicated to this purpose. We asked for 
all those layers so we could do things like this. Then instruct the 
photoplotters to merge that layer, as a subtractive negative, with the 
normal component side layer. One might be able to make a single file that 
would do this with CAMtastic; certainly the RS-274X standard allows for 
such. (I've argued for some time that we could get much more efficient 
copper pours by using positive/negative merges than by the present draw 
method.)

As to the round feature, it could be a pad assigned to the mech layer. Or 
it could be an arc of suitable dimensions. Or it could be a very short 
piece of track, just long enough that Protel will not think it doesn't 
exist. I forget if P99SE deletes zero-length tracks or not. Probably better 
to avoid them, because, after all, its undocumented so even if it works, it 
might go away in the next rev. Pads on mech layers would be simple and 
would not need nets, etc.

 If one wants to put a via in a surface pad, then put a via or 
 free pad in a
surface pad!

[Bruce:]  Not really an option for HDI.  How difficult do you think it 
would be 

Re: [PEDA] Use Pad Stack

2001-05-07 Thread Abd ul-Rahman Lomax

At 05:55 PM 3/15/01 -0800, Brad Velander wrote:
Abd-ul Rahman,
 Not that it warrants arguing over but you and I just have different
views. You say a single layer pad is a SMT pad. I say a single layer pad is
the most ancient of all pads and originally in it's concept had a drill even
though it is a single layer pad, it was a single sided PCB design the
predecessor of all else. You can call a single-layer pad SMT all you want
but you won't convince me because the single layer pad predated both of our
births, long before SMT was even a glint in anyone's eyes.

When I was born, printed wiring, I think, had been used but it was not 
common. Radios had masses of wiring in them.

SMT predates CAD systems. I worked with flatpacks in 1975, and they were 
not new.

The first pads had holes associated with them. When CAD programs were 
developed, we had pad definitions, and these initially consisted of pads on 
both sides of the board with a hole. Surface pads, per se, came later. I've 
done a lot of single-sided design and, when I have used a CAD system to do 
it, I never used surface pads. It didn't even occur to me that I might 
want to do that.

The present surface pad option on a primitive was designed for SMT parts. 
Period. That is the history, and the programmers -- or at least one of them 
as just reported -- agree. Calling it a single layer pad and connecting 
it with single-sided PC design is a red herring.

 On your note about undocumented features you are leaving yourself a
little open there consider Protel's lacking documentation.

Leaving myself open for what? I'm not trying to make a case that Protel is 
perfect! It isn't! (But the 99SE manual is much better than the 99 manual.)

  A lot of what we
all do day in and day out is undocumented or it is just mentioned without
further explanation or qualification of the limitations.

What we do every day, especially what most of us do every day, is not what 
I was writing about. Surface pads with holes do not fall into this 
category. Protel was designed to use through holes with variable pads for 
mounting components and for other uses, and to use surface pads for 
mounting SMT parts and a few other uses such as fiducials. As proof, 
consider paste masks. Protel assumes that a surface pad has paste mask 
geometry associated with it.

I'll say this again. There are several bugs here. A big one is the 
discrepancy between drill drawing and drill file when someone has used a 
surface pad with a hole. Another is that Protel allows surface pads to have 
holes at all. Some have chimed in with objections that they use surface 
pads all the time with holes and they need such structures. I'm not talking 
about PCB structures, per se, but about how these structures are 
represented in the database and user interface. The way to make single 
layer pads with holes in Protel is to use a multilayer padstack with 
appropriate pad sizes. Essentially, if it has a hole, it *must* be a 
multilayer pad because a hole is always multilayer (even if it is a blind 
via, it is on more than one layer). You might get away with using a surface 
pad in some applications, but I'm not sure that all aspects used to work 
even with Protel 98. We'd have to look at ground plane blowouts, copper 
pours, clearance DRCs on inner layers, paste masks, etc., etc.


 Have a good evening, I am sure we will talk tomorrow.

I may not talk much; I'll be out and about, most of tomorrow, and I do need 
to do some, uh, work once in a while.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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