Re: [PEDA] eight-layer stackup
Dennis, Please see below. JaMi - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 4:30 PM Subject: Re: [PEDA] eight-layer stackup you just use a via and short track in the component footprint design and then run update free primitives (yes i know they are not 'free') it works no drc probs You are right, this does in fact work fine, and in fact is pretty close to what I do normally anyway. I normally use one separate component for the BGA pad pattern footprint, and then make a second component that contains all of the dogbone traces and vias and all of what I call the BGA escape routing, which is all of the inner routing on the different layers out to the edge of the BGA. I keep all of the escape routing intact in its own component, which is placed in the design directly on top of the BGA component footprint (with free primitives updated)until I have everything in the area of the BGA routed exactly the way I want it. This allows me to easily edit the routing internal to the perimeter of the BGA in the Component Editor, and use Update PCB and then as you point out, use the update free primitives. Once I get everything the way I like it, I then release all of the primitives of the second component into the design, and then all of the traces and vias become part of the design. Using your methodology, I would just keep the dogbone traces and the vias as part of my first component, rather then the second component which I release. For that matter, I could just keep everything from my normal first BGA component and my second routing component, all in one component, and never release any it, and just keep updating free primitives as I go along. I guess it is all a matter of personal preferences. I prefer to have a standard BGA pattern for a component, and have nothing attached to it in the end product, and have all of my vias and traces and routing as normal vias and traces in the end product of the board, where I can go in and change things such as width or layer or whatever one at a time just as a normal trace. This also allows me to do things like highlight a net all the way to the BGA pad, and get the full length of the net in the netlist report. Most importantly, this method allows me to end up with a PCB that does not have any non standard little hidden tricks in it that may not be seen by the next person down the line to work on the board, or even forgotten by me the next time I have to come back in a year or two and work on the design again. In this sense, I would prefer to have the DRC errors showing right out there in plain sight where they can be seen for what they are. My whole point in this post and the earlier post where I discussed this DRC error issue (see the thread on subject quick question on last Saturday (5/31/03)) is simply that sometimes Protel DRC errors really are not errors at all, and I would like a way to handle them. Certainly there are ways to do tricks to make the little iridescent glow go away, but in some cases I just learn to live with them. I personally would rather have a Protel DRC error glowing here and there (which I can simply reset so I do not have to look at them) in the design, than have to play tricks here and there and do some non standard thing to make the DRC happy. I would rather have the DRC error, which anyone could see was not a real error anyway, then have to jump thru the update free primitives hoop on the finished design that gets released to production and sent down the road to the next designer who may work on the design a few years from now after I am gone. There is just something that bugs me about having to play tricks in a design to make a screwed up piece of software happy, especially when the screwed up piece of software in wrong half the time when it comes to DRC errors anyway. am i on the same page as this discussion or maybe i have missed something? Yep. You are in fact on the exact same page. ds JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Julian, Please see below, JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 6:00 PM Subject: Re: [PEDA] eight-layer stackup Jami, you missed a few important points. Generating a netlist and loading it into your PCB is not hard to do. It is a few more mouse clicks (maybe 20 seconds more work) than just hitting update. Your time is surely not that valuable, is it?? I am sure that this may work, but I was not thinking along those lines primarily since the last big mother of a BGA board that I did was done from an OrCAD netlist, where I don't think those options were available to me. Also see below. like I said: generate a netlist - it gives you the option to generate single pin nets if you want - ie a net for every unconnected pin. load the netlist into the PCB. I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. I only would want a net on the unconnected BGA pins that I would want to connect to a via so that that connection would be accessible from the back of the PCB. Juggling the netlist to generate all the extra nets seems to me to be an extra step that is not going to be understood by the next guy who happens to have to work on the design a couple of years from now when I may not be here. Also see below. I could also solve the problem by turning off certain rule checking, but that is not the answer. By doing that, I may miss a real error. I would rather have a dogbone trace and via flagged as an error, than have to override the ability to catch another single node net that really was an error. Now, if this is not the first iteration of the PCB (ie you haven't just placed all the parts on the board, its possible some preroutes will have nets already assigned to them) And particularly if you have just changed nets around on pins, as happens with FPGAs at layout time. you need to go to the net manager in the PCB editor and unlock the primitives of the prerouted BGA, then select all the primitives. Do a global edit on selected tracks, and selected VIAS to set them all to NO NET Then lock them all again. Then, you do that update free primitives from component pads thing. Now you won't have to make up any funny rules in your PCB, and you won't have to sit there after a DRC working out what are valid shorted nets and what aren't. It's a pain, but the only way I know to update prerouted footprints properly. Using the update PCB menu item does not allow this, and so when you're working with pre-routed BGA footprints, it is a better idea to work with netlists, even if it isn't as immediately convenient. This kind of sounds like some of the things you mention here are some of the things we all may do anyway in our approach to BGA routing. In this respect see my parallel resopnse in this thread to Dennis. On the other hand, juggling things around netlist wise, such as your selecting vias above and then setting them to NO NET and then locking them, seems like much more than I want to get into. I don't ever want to have to manually edit any net in the netlist or in the design. To me the netlist is sacred, and I never want to have to diddle around with it. That is my on real baseline in the design that I personally feel should never be touched. Getting back to Michael's original question in this thread: DRC ... is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC?, I simply stated that I didn't think that there was an easy way to do it short of putting them on the schematic. What I should have said, and what I really meant, was that I didn't think that there was an easy way to do it short of putting them on the schematic, without playing tricks on Protel or having to do anything non standard. I have a very strong aversion to having to do anything non standard in Protel, just to get things done and acceptable to Protel DRC. As discussed in your other post on Saturday, Protel DRC is not always right. Yes, there have been times that I have had to explain to someone that something really was not an error, simply because Protel thought it was an error (the error discussed in your other thread on Saturday regarding a trace crossing a split in an unrelated plane is a perfect example). Yes, there is a matter of personal pride in doing a design in Protel that has no DRC errors. I would rather have the DRC error, which to anyone is obviously really not an error anyway, than to have to have something in the final design that could possibly be missed or not understood by the next guy to work on the project. This is why I brought up the issue in the other post as to the acceptability of certain DRC errors. - As for my board
Re: [PEDA] eight-layer stackup
One place where you'd want every pin in a net is if you do a exhaustive connectivity check of your bare board before loading components. John JaMi Smith wrote: I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Julian, Please see below. JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 1:28 AM Subject: Re: [PEDA] eight-layer stackup From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. You have kind of lost me here on this one. It appears that no matter what you do you have to go back and screw around with the schematic somehow so that you can actually get a real live net in the netlist that will represent the little dogbone trace and the via. It also sounds like I have to have make a rule to allow a single pin net, and then actually put that connection into the schematic that would become a single pin net. Kinda sounds just about like I said but without the testpoint. Why on earth would I not want to keep synchronization intact? All in all, it sounds like I am doing more work and asking for more problems then necessary, and then opening the door for some real errors to sneak in undetected. Once again, I would rather have the little DRC error starring me in the face. At least this way I would not miss any other errors due to the fact that I was tricking Protel. I would still like to see a Protel 99 SE server to handle DRC errors like I discussed in my post to you regarding your split plane problem earlier this week, and I would like to see Protel DXP incorporate the solution to the issue that I discussed. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) I'd first like to thank John Haddy and Tom Reineking for the very important points that they both brought up along this line in there related responses to your post. I have spent too many hours out on an FCC OATS (Open Area Test Site) or in an Screen Room or Anacoic Chamber trying to track down EMC / Signal Integrity problems in equipment that I was trying to get certified for FCC or CISPR (or even CTIC) compliance requirements to let this one slide by. It has been my experience that a majority of the emissions problems I have ever seen can be tracked down to a high speed signal or clock line that has crossed a split in a plane. In addition to the reflection issue that was brought up by Tom, there is an even worse problem that has not been discussed. Simply stated, any signal that is traveling along a conductor over a plane will generate currents in the plane that are a mirror of those in the conductor. When you cross a gap in between two different planes, you will generate seperate currents in both of those planes. Those two different currents in each of the two planes will then travel throughout those two planes until they get to a common point and where they can cancel each other out. This may mean that they will travel to a common point on the board to cancel, or it may mean that they will travel all the way back to the power supply to cancel. Whatever the case, these currents will have to travel throughout the planes, affecting everything that is connected to the planes, until they can cancel. While decoupling caps will help the problem somewhat, they will not eliminate it. This is referred to as infecting the planes and supplies with noise. Once you get this noise into a plane or power supply, it gets into everything, and there is no way to get rid of it. The only way to get this kind of noise out of a plane or supply is to keep it out of the plane or supply in the first place. Period. That is why rule number one in PCB Design is to never ever under any circumstance cross a split in a plane with a signal. Period. Rule number two is to never ever forget about or ignore or violate rule number one. I don't care what any of the so called experts have to say on this issue, you simply should not do it. This is such a fundamental rule in the industry that even Protel has this one down right, and will flag this as a DRC error. Respecting your comment that you are the person (who got his
Re: [PEDA] eight-layer stackup
you just use a via and short track in the component footprint design and then run update free primitives (yes i know they are not 'free') it works no drc probs am i on the same page as this discussion or maybe i have missed something? ds JaMi Smith wrote: Julian, Please see below. JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, June 03, 2003 1:28 AM Subject: Re: [PEDA] eight-layer stackup From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. You have kind of lost me here on this one. It appears that no matter what you do you have to go back and screw around with the schematic somehow so that you can actually get a real live net in the netlist that will represent the little dogbone trace and the via. It also sounds like I have to have make a rule to allow a single pin net, and then actually put that connection into the schematic that would become a single pin net. Kinda sounds just about like I said but without the testpoint. Why on earth would I not want to keep synchronization intact? All in all, it sounds like I am doing more work and asking for more problems then necessary, and then opening the door for some real errors to sneak in undetected. Once again, I would rather have the little DRC error starring me in the face. At least this way I would not miss any other errors due to the fact that I was tricking Protel. I would still like to see a Protel 99 SE server to handle DRC errors like I discussed in my post to you regarding your split plane problem earlier this week, and I would like to see Protel DXP incorporate the solution to the issue that I discussed. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) I'd first like to thank John Haddy and Tom Reineking for the very important points that they both brought up along this line in there related responses to your post. I have spent too many hours out on an FCC OATS (Open Area Test Site) or in an Screen Room or Anacoic Chamber trying to track down EMC / Signal Integrity problems in equipment that I was trying to get certified for FCC or CISPR (or even CTIC) compliance requirements to let this one slide by. It has been my experience that a majority of the emissions problems I have ever seen can be tracked down to a high speed signal or clock line that has crossed a split in a plane. In addition to the reflection issue that was brought up by Tom, there is an even worse problem that has not been discussed. Simply stated, any signal that is traveling along a conductor over a plane will generate currents in the plane that are a mirror of those in the conductor. When you cross a gap in between two different planes, you will generate seperate currents in both of those planes. Those two different currents in each of the two planes will then travel throughout those two planes until they get to a common point and where they can cancel each other out. This may mean that they will travel to a common point on the board to cancel, or it may mean that they will travel all the way back to the power supply to cancel. Whatever the case, these currents will have to travel throughout the planes, affecting everything that is connected to the planes, until they can cancel. While decoupling caps will help the problem somewhat, they will not eliminate it. This is referred to as infecting the planes and supplies with noise. Once you get this noise into a plane or power supply, it gets into everything, and there is no way to get rid of it. The only way to get this kind of noise out of a plane or supply is to keep it out of the plane or supply in the first place. Period. That is why rule number one in PCB Design is to never ever under any circumstance cross a split in a plane with a signal. Period. Rule
Re: [PEDA] eight-layer stackup
Michael, http://www.hottconsultants.com/tips.html provides some usefull information about layer stack up. Best regards, Ben Uijtenhaak * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Just one note on split planes. High speed signals crossing splits in either power or ground (they're the same for AC), there will be a reflection due to the sharp impedance change. Of course the effect will vary depending on trace length and split length and locations of nearby bypass caps. In general you should avoid that situation as it will increase the EMI and reduce the signal integrity. Tom Julian Higginson wrote: From: JaMi Smith [mailto:[EMAIL PROTECTED]] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real "net" it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Jami, you missed a few important points. Generating a netlist and loading it into your PCB is not hard to do. It is a few more mouse clicks (maybe 20 seconds more work) than just hitting update. Your time is surely not that valuable, is it?? like I said: generate a netlist - it gives you the option to generate single pin nets if you want - ie a net for every unconnected pin. load the netlist into the PCB. Now, if this is not the first iteration of the PCB (ie you havent just placed all the parts on the board, its possible some preroutes will have nets already assigned to them) And particularly if you have just changed nets around on pins, as happens with FPGAs at layout time. you need to go to the net manager in the PCB editor and unlock the primitives of the prerouted BGA, then select all the primitives. Do a global edit on selected tracks, and selected VIAS to set them all to NO NET Then lock them all again. Then, you do that update free primitives from component pads thing. Now you won't have to make up any funny rules in your PCB, and you won't have to sit there after a DRC working out what are valid shorted nets and what aren't. It's a pain, but the only way I know to update prerouted footprints properly. Using the update PCB menu item does not allow this, and so when you're working with pre-routed BGA footprints, it is a better idea to work with netlists, even if it isn't as immediately convenient. - As for my board (not that I need any more help on it, it's working great! Its a 4 layer baord. 2 signal, 1 ground 1 power. the power and ground planes have split planes on them. Stackup is: Signal GND PWR Signal All the high speed signals go on the top layer over the unbroken ground plane. there is only one ground plane for the majority of the PCB, the other grounds are around connectors where I have isolated grounds for different I/O connections. The power plane IS split under the BGA because it requires 4 power rails. (3 actual power supplies, ome voltage reference for the gigabit transcievers) I could possibly do a screen dump to illustrate this if you want but I guess you know what they look like anyway. What I was saying, is that for a design that requires only two routing layers, a 6 layer board is slight overkill, no? one split power plane is certianly usable if you are careful. Of course the usual caveats apply - Your Mileage May Vary, Not Valid In All States, For Internal Use Only, This Is Not A Guarantee, etc etc etc, blah blah blah. Julian -- Julian Higginson - Design Engineer - Lake Technology. Suite 502/55 Mountain St, Ultimo, NSW 2007, Australia. Phone: +61 2 9213 9000 - Direct: +61 2 9213 9021 mailto:[EMAIL PROTECTED] - http://www.lake.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
oops I mean four internal planes, two being power and two being ground planes.. sorry -Original Message- From: Michael Biggs [mailto:[EMAIL PROTECTED] Sent: Monday, June 02, 2003 3:21 PM To: 'Protel EDA Forum' Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
I'd probably do it this way (top to bottom): sig gnd1 pwr1 sig sig gnd2 pwr2 sig Assumptions: your highest-speed parts are on the top side. gnd1 and pwr1 are your main power rails for the highest-speed parts. Whatever you do, keep each gnd plane and it's matching pwr plane adjacent to each other - the distributed capacitance of this arrangement helps in decoupling the supply rails. This is in addition to your decoupling caps, not to replace them. I don't have anything to say about the dogbones. I'm still using cat treats... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Michael Biggs [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Monday, June 02, 2003 4:20 PM Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
MichaelB, While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. Myself, I have had the very same problem with the identical requirements (needing to take each BGA contact to the back of the board with a via), and I just live with the errors. I have accepted the fact that even if I were to do a perfect board in Protel 99 SE, that there would still be some little DRC error somewhere. Protel DRC just doesn't map to reality in all cases, as there is always some need for some special requirement that Protel just can't handle, so you look at the DRC error, and accept it as is, and live with the error in the report file and that little iridescent glow here and there on the on the screen. I find that the trick for me is to reset the errors once I have examined them, and that way they are not just sitting there staring me in the face as I continue working on the design. Respecting the layer stack up, I myself would prefer to go with 2 outer routing layers, 2 planes under that on each side, and then another 2 routing layers in the middle. But before you even get that far, I think that you need to ask whether any of the signals may have any special requirements, such as controlled impedance, or matched lengths, or isolation, or the necessity to be routed over a specific plane. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. It may well be that due to the type of signals you are dealing with (LVDS / high speed / controlled impedance / susceptible to crosstalk), you might have to go with isolating the internal signal routing layers as layers 3 and 6 with the two power layers as 4 and 5. What type and size of BGA are you dealing with? Any special routing requirements? JaMi * * * * * * * * * - Original Message - From: Michael Biggs [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:20 PM Subject: [PEDA] eight-layer stackup Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Michael The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal thou never actually using 8 layers this is all i can give you. Hope it helps. Nathan BTW the reference is PCB design techniques for emc compliance by mark montrose. 2nd Edition Michael Biggs wrote: Anyone have a preferred method of stackup guidelines of web references to layer stackups for 8 layers using four power planes and four signal layers? I am torn between two methods being that I have two internal power planes. Thanks for any help! Also I have a couple of BGA's on this layout and when I run (using Protel99SE) my DRC everything is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC? Thanks again! MichaelB -- Nathan Horsfield Inspiration Technology P/L Ph: +61 8 8211 9668 Fax: +61 8 8211 9658 www.instech.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
From: JaMi Smith [mailto:[EMAIL PROTECTED] While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real net it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble. yeah there is a way: Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST LOADING. In the netlist generation in schematic, you can tell it to include unnamed single pin nets. You will then get nets assigned to all your unused pins on your BGA. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. Jeez. How many layers does he have spare for power planes?? my BGA needed 3 of the buggers. Split planes are the only way to go. Just be really careful not to bridge them with a through hole pin like I did... Julian (who got his BGA board not reporting errors, and the BGA part of it is fine) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
